Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) DESCRIPTION PLS173 FEATURES The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 12 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 22 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS173 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. • I/O propagation delay: 30ns (max.) • 12 inputs • 42 AND gates • 10 OR gates • 10 bidirectional I/O lines • Active-High or -Low outputs • 42 product terms: PIN CONFIGURATIONS N Package – 32 logic terms • Random logic • Code converters • Fault detectors • Function generators • Address mapping • Multiplexing 23 B9 I2 3 22 B8 I3 4 21 B7 I4 5 20 B6 I5 6 19 B5 I6 7 18 B4 I7 8 17 B3 16 B2 I9 10 15 B1 I10 11 14 B0 GND 12 13 I11 N = Plastic DIP (300mil-wide) A Package Order codes for this device are listed below. APPLICATIONS 24 VCC I1 2 I8 9 – 10 control terms • Ni-Cr programmable links • Input loading: –100µA (max.) • Power dissipation: 750mW (typ.) • 3-State outputs • TTL compatible I0 1 I3 I2 I1 I0 VCC B9 B8 4 3 2 1 28 27 26 NC 5 25 NC I4 6 24 B7 I5 7 23 B6 I6 8 22 B5 I7 9 21 B4 I8 10 20 B3 NC 11 19 NC 14 15 16 17 18 12 13 I9 I10 GND I11 B0 B1 B2 A = Plastic Leaded Chip Carrier ORDERING INFORMATION DESCRIPTION ORDER CODE DRAWING NUMBER 24-Pin Plastic Dual-In-Line 300mil-wide PLS173N 0410D 28-Pin Plastic Leaded Chip Carrier PLS173A 0401F October 22, 1993 25 853–0324 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLS173 LOGIC DIAGRAM (LOGIC TERMS–P) I0 1 I1 2 I2 3 I3 4 I4 5 I5 6 I6 7 I7 8 I8 9 (CONTROL TERMS) I9 10 I10 11 I11 13 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 S9 X9 X8 X7 X6 X5 X4 X3 X2 X1 31 24 23 16 15 8 7 0 NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. October 22, 1993 26 X0 S8 S7 S6 S5 S4 S3 S2 S1 S0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 23 B9 22 B8 21 B7 20 B6 19 B5 18 B4 17 B3 16 B2 15 B1 14 B0 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLS173 FUNCTIONAL DIAGRAM P31 LOGIC FUNCTION P0 D0 D9 TYPICAL PRODUCT TERM: Pn = A ⋅ B ⋅ C ⋅ D ⋅ . . . I0 TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H Z = P0 + P1 + P2 . . . AT OUTPUT POLARITY + L Z = P0 + P1 + P2 + . . . Z = P0 ⋅ P1 ⋅ P2 ⋅ . . . I11 B0 NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the EX-OR gates. 2. ZX, A, B, C, etc. are user defined connections to fixed inputs (I), and bidirectional pins (B). B9 S9 B9 X9 S0 B0 X0 ABSOLUTE MAXIMUM RATINGS1 THERMAL RATINGS RATING SYMBOL PARAMETER Min TEMPERATURE Max UNIT Maximum junction 150°C +7 VDC Maximum ambient 75°C VCC Supply voltage VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents +30 mA IOUT Output currents +100 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C –30 NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. October 22, 1993 27 Allowable thermal rise ambient to junction 75°C The PLS173 is also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Handbook. Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLS173 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT 0.8 V voltage2 VIL Low VCC = MIN VIH High VCC = MAX VIC Clamp3 Output 2.0 VCC = MIN, IIN = –12mA V –0.8 –1.2 V 0.5 V voltage2 VCC = MIN VOL Low4 IOL = 15mA VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = VCC 40 µA VOUT = 5.5V 80 µA VOUT = 0.45V –140 Output current VCC = MAX IO(OFF) IOS ICC Hi-Z state8 Short circuit3, 5, 6 VCC supply current7 VOUT = 0V –15 VCC = MAX 150 –70 mA 170 mA Capacitance VCC = 5V IIN Input VIN = 2.0V 8 pF CB I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs VIL applied to I11. Pins 1–5 = 0V, Pins 6–10 = 4.5V, Pin 11 = 0V and Pin 13 = 10V. 5. Same conditions as Note 4 except Pin 11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0 and I1 = 0V, and I2 – I11 and B0 – B9 = 4.5V. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I11). October 22, 1993 28 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLS173 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 470Ω, R2 = 1kΩ TEST LIMITS SYMBOL PARAMETER FROM TO CONDITION delay2 MIN TYP MAX UNIT tPD Propagation Input ± Output ± CL = 30pF 20 30 ns tOE Output enable1 Input ± Output – CL = 30pF 20 30 ns tOD Output disable1 Input ± Output + CL = 5pF 20 30 ns NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM TEST LOAD CIRCUIT +3.0V 90% +5V VCC S1 10% 0V C1 tR 5ns tF C2 R1 5ns BY I0 +3.0V 90% INPUTS I11 BW 10% CL R2 DUT 0V 5ns 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses TIMING DEFINITIONS SYMBOL BX GND BZ OUTPUTS NOTE: C1 and C2 are to bypass VCC to GND. TIMING DIAGRAM PARAMETER +3V tPD tOD tOE Propagation delay between input and output. Delay between input change and when output is off (Hi-Z or High). I, B 1.5V 1.5V 0V VOH B 1.5V Delay between input change and when output reflects specified output level. October 22, 1993 1.5V 1.5V VT VOL tPD 29 tOD tOE Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) LOGIC PROGRAMMING PLS173 PROGRAMMING AND SOFTWARE SUPPORT The PLS173 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O Corporation’s ABEL, and Logical Devices Incorporated’s CUPL design software packages. Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for addtional information. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. OUTPUT POLARITY – (B) S PLS173 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. S ACTIVE LEVEL CODE To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. HIGH1 (NON-NVERTING) H B B X X ACTIVE LEVEL CODE LOW (INVERTING) L AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B P, D P, D STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1, 2 O I, B H I, B L DON’T CARE – OR ARRAY – (B) VIRGIN STATE P A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. P S S 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. Pn STATUS CODE Pn STATUS ACTIVE1 A INACTIVE CODE • NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the True and Complement of any input (I, B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 30 October 22, 1993 H L — I, B I, B DON’T CARE VARIABLE NAME 0 INACTIVE AND I, B(I) LOW HIGH L H B(0) (POL) A CONTROL INACTIVE ACTIVE OR 2. Unused I and B bits in the AND array must be programmed Don’t Care (—). 3. Unused product terms can be left blank. NOTES 1. The PLA is shipped with all links intact. Thus a background of entries corresponding to states of virgin links exists in the table. (Shown BLANK for clarity.) PROGRAM TABLE # PHILIPS DEVICE # CUSTOMER NAME REV DATE Philips Semiconductors Programmable Logic Devices T E R M PIN 11 10 Product specification Programmable logic array (22 × 42 × 10) PLS173 PROGRAM TABLE POLARITY I AND B(I) 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 D9 31 D8 D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 1 0 13 11 10 9 8 7 6 5 4 3 2 1 31 9 8 7 6 5 B(0) OR 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array (22 × 42 × 10) PLS173 SNAP RESOURCE SUMMARY DESIGNATIONS P31 P0 D0 D9 DIN173 I0 NIN173 I11 B0 DIN173 NIN173 B9 AND CAND TOUT173 S9 B9 X9 OR S0 B0 X0 EXOR173 October 22, 1993 32