INTEGRATED CIRCUITS DATA SHEET TDA8357J Full bridge vertical deflection output circuit in LVDMOS Preliminary specification File under Integrated Circuits, IC02 1999 Nov 10 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J FEATURES GENERAL DESCRIPTION • Few external components required The TDA8357J is a power circuit for use in 90° and 110° colour deflection systems for 25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC contains a vertical deflection output circuit, operating as a high efficiency class G system. The full bridge output circuit allows DC coupling of the deflection coil in combination with single positive supply voltages. • High efficiency fully DC coupled vertical bridge output circuit • Vertical flyback switch with short rise and fall times • Built-in guard circuit • Thermal protection circuit • Improved EMC performance due to differential inputs. The IC is constructed in a Low Voltage DMOS (LVDMOS) process that combines bipolar, CMOS and DMOS devices. DMOS transistors are used in the output stage because of absence of second breakdown. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP supply voltage 7.5 12 18 V VFB flyback supply voltage 2VP 45 66 V Iq(P)(av) average quiescent supply current during scan − 10 15 mA Iq(FB)(av) average quiescent flyback supply current during scan − − 10 mA Ptot total power dissipation − − 8 W Inputs and outputs Vi(dif)(p-p) differential input voltage (peak-to-peak value) − 1000 1500 mV Io(p-p) output current (peak-to-peak value) − − 2.0 A − − ±1.2 A Flyback switch Io(peak) t ≤ 1.5 ms maximum (peak) output current Thermal data; in accordance with IEC 747-1 Tstg storage temperature −55 − +150 °C Tamb ambient temperature −25 − +75 °C Tj junction temperature − − 150 °C ORDERING INFORMATION TYPE NUMBER TDA8357J 1999 Nov 10 PACKAGE NAME DBS9P DESCRIPTION plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad 2 VERSION SOT523-1 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J BLOCK DIAGRAM GUARD handbook, full pagewidth 8 VP VFB 3 6 GUARD CIRCUIT M5 D2 D3 M2 Vi(p-p) D1 VI(bias) 7 OUTA INA 1 M4 0 Vi(p-p) INB VI(bias) 9 INPUT AND FEEDBACK CIRCUIT FEEDB M1 2 4 0 OUTB M3 TDA8357J 5 MGS803 GND Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION handbook, halfpage INA 1 INB 2 VP 3 OUTB 4 ground GND 5 6 flyback supply voltage VFB 6 7 output A OUTA 7 GUARD 8 guard output GUARD 8 FEEDB 9 feedback input FEEDB 9 INA 1 input A INB 2 input B VP 3 supply voltage OUTB 4 output B GND 5 VFB OUTA TDA8357J MGS804 The exposed die pad is connected to pin GND. Fig.2 Pin configuration. 1999 Nov 10 3 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J FUNCTIONAL DESCRIPTION Guard circuit Vertical output stage A guard circuit with output pin GUARD is provided. The vertical driver circuit has a bridge configuration. The deflection coil is connected between the complimentary driven output amplifiers. The differential input circuit is voltage driven. The input circuit is specially designed for direct connection to driver circuits delivering a differential signal but it is also suitable for single-ended applications. The output currents of the driver device are converted to voltages by the conversion resistors RCV1 and RCV2 (see Fig.3) connected to pins INA and INB. The differential input voltage is compared with the voltage across the measuring resistor RM, providing internal feedback information. The voltage across RM is proportional with the output current. The relationship between the differential input current and the output current is defined by: The guard circuit generates a HIGH-level during the flyback period. The guard circuit is also activated for one of the following conditions: • During thermal protection (Tj ≈ 170 °C) • During an open-loop condition. The guard signal can be used for blanking the picture tube and signalling fault conditions. The vertical synchronization pulses of the guard signal can be used by an On Screen Display (OSD) microcontroller. Damping resistor compensation HF loop stability is achieved by connecting a damping resistor RD1 across the deflection coil. The current values in RD1 during scan and flyback are significantly different. Both the resistor current and the deflection coil current flow into measuring resistor RM, resulting in a too low deflection coil current at the start of the scan. 2 × Ii(dif)(p-p) × RCV = Io(p-p) × RM The output current should measure 0.5 to 2.0 A (p-p) and is determined by the value of RM and RCV. The allowable input voltage range is 100 mV to 1.6 V for each input. The formula given does not include internal bondwire resistances. Depending on the values of RM and the internal bondwire resistance (typical value of 50 mΩ) the actual value of the current in the deflection coil will be about 5% lower than calculated. The difference in the damping resistor current values during scan and flyback have to be externally compensated in order to achieve a short settling time. For that purpose a compensation resistor RCMP in series with a zener diode is connected between pins OUTA and INA (see Fig.4). The zener diode voltage value should be equal to VP. The value of RCMP is calculated by: Flyback supply ( V FB – V loss ( FB ) – V Z ) × R D1 × R CV1 R CMP = ----------------------------------------------------------------------------------------------------------( V FB – V loss ( FB ) – I coil ( peak ) × R coil ) × R M The flyback voltage is determined by the flyback supply voltage VFB. The principle of two supply voltages (class G) allows to use an optimum supply voltage VP for scan and an optimum flyback supply voltage VFB for flyback, thus very high efficiency is achieved. The available flyback output voltage across the coil is almost equal to VFB, due to the absence of a coupling capacitor which is not required in a bridge configuration. The very short rise and fall times of the flyback switch are determined mainly by the slew-rate value of more than 300 V/µs. where: • Vloss(FB) is the voltage loss between pins VFB and OUTA at flyback • Rcoil is the deflection coil resistance • VZ is the voltage of zener diode D5. Protection The output circuit contains protection circuits for: • Too high die temperature • Overvoltage of output A. 1999 Nov 10 4 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage − 18 V VFB flyback supply voltage − 68 V Vn DC voltage − 68 V pin OUTB − VP V pins INA, INB, GUARD and FEEDB −0.5 VP V pin OUTA In note 1 DC current pins OUTA and OUTB during scan (p-p) − 2.0 A pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms − ±1.2 A −20 +20 mA current into any pin; pin voltage is 1.5 × VP; note 2 − +200 mA current out of any pin; pin voltage is −1.5 × VP; note 2 −200 − mA machine model; note 3 −300 +300 V human body model; note 4 −2000 +2000 V pins INA, INB, GUARD and FEEDB Ilu Ves latch-up current electrostatic handling voltage Ptot total power dissipation − 8 W Tstg storage temperature −55 +150 °C Tamb ambient temperature −25 +75 °C Tj junction temperature − 150 °C note 5 Notes 1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage. 2. At Tj(max). 3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor. 4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor. 5. Internally limited by thermal protection at Tj ≈ 170 °C. THERMAL CHARACTERISTICS In accordance with IEC 747-1. SYMBOL PARAMETER Rth(j-c) thermal resistance from junction to case Rth(j-a) thermal resistance from junction to ambient 1999 Nov 10 CONDITIONS in free air 5 MIN. TYP. MAX. UNIT − − 6 K/W − − 65 K/W Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J CHARACTERISTICS VP = 12 V; VFB = 45 V; fvert = 50 Hz; VI(bias) = 880 mV; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VP operating supply voltage 7.5 12 18 V VFB flyback supply voltage note 1 2VP 45 66 V Iq(P)(av) average quiescent supply current during scan − 10 15 mA Iq(P) quiescent supply current no signal; no load − 55 75 mA Iq(FB)(av) average quiescent flyback supply current during scan − − 10 mA − 1000 1500 mV Inputs A and B Vi(dif)(p-p) differential input voltage (peak-to-peak value) note 2 VI(bias) input bias voltage note 2 II(bias) input bias current 100 880 1600 mV − 25 35 µA Io = 0.7 A − − 3.9 V Io = 1.0 A − − 5.5 V Io = −0.7 A − − 2.8 V Io = −1.0 A − − 4.0 V − − 2.0 A adjacent blocks − 1 2 % non adjacent blocks − 1 3 % VI(bias) = 200 mV − − ±15 mV VI(bias) = 1 V Outputs A and B Vloss(1) Vloss(2) voltage loss first scan part voltage loss second scan part Io(p-p) output current (peak-to-peak value) LE linearity error Voffset offset voltage note 3 note 4 Io(p-p) = 2.0 A; notes 5 and 6 across RM; Vi(dif) = 0 V − − ±25 mV ∆Voffset(T) offset voltage variation with temperature across RM; Vi(dif) = 0 V − − 40 µV/K VO DC output voltage Vi(dif) = 0 V − 0.5VP − V Gv(ol) open-loop voltage gain notes 7 and 8 − 60 − dB f−3dB(h) high −3 dB cut-off frequency open-loop − 1 − kHz Gv voltage gain note 9 − 1 − ∆Gv(T) voltage gain variation with the temperature − − 10−4 K−1 PSRR power supply rejection ratio 80 90 − dB 1999 Nov 10 note 10 6 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS SYMBOL PARAMETER CONDITIONS TDA8357J MIN. TYP. MAX. UNIT Flyback switch Io(peak) maximum (peak) output current t ≤ 1.5 ms Vloss(FB) voltage loss at flyback note 11 − − ±1.2 A Io = 0.7 A − 7.5 8.5 V Io = 1.0 A − 8 9 V Guard circuit IO(grd) = 100 µA 5 6 7 V VO(grd)(max) allowable guard voltage maximum leakage current IL(max) = 10 µA − − 18 V IO(grd) VO(grd) = 0 V; not active − − 10 µA VO(grd) = 4.5 V; active 1 − 2.5 mA VO(grd) guard output voltage output current Notes 1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA and VFB at the first part of the flyback. 2. Allowable input range: VI(bias) + Vi(dif) < 1600 mV and VI(bias) − Vi(dif) > 100 mV for each input. 3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value. 4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value. 5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’ measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across RM, starting at k = 2 and ending at k = 21, where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin, Vmax and Vavg are the minimum, maximum and average voltages respectively. The linearity errors are defined as: Vk – Vk + 1 a) LE = ------------------------- (adjacent blocks) V avg V max – V min b) LE = ------------------------------ (non adjacent blocks) V avg 6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage dependent S-distortion in the input stage. 7. V OUTA – V OUTB G v ( ol ) = ------------------------------------------V FEEDB – V OUTB 8. Pin FEEDB not connected. 9. V FEEDB – V OUTB G v = ------------------------------------------V INA – V INB 10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM. 11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA. 1999 Nov 10 7 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J APPLICATION INFORMATION VP handbook, full pagewidth RGRD 4.7 kΩ VFB GUARD VP VFB 8 3 6 GUARD CIRCUIT Vi(p-p) C1 100 nF M5 C2 100 nF D2 D3 VI(bias) M2 0 D1 I I(bias) 7 OUTA INA 1 RCV1 2.2 kΩ (1%) I i(dif) M4 9 INPUT AND FEEDBACK CIRCUIT RS 2.7 kΩ I I(bias) CM 10 nF M1 INB 2 4 RCV2 2.2 kΩ (1%) M3 Vi(p-p) TDA8357J VI(bias) 5 0 GND Fig.3 Test diagram. 1999 Nov 10 FEEDB RL 5.2 Ω 8 MGS806 OUTB RM 0.8 Ω This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VFB 8 3 6 GUARD CIRCUIT Vi(p-p) 10 Ω C3 100 nF M5 VI(bias) C1 47 µF (100 V) D5 12 V D2 C4 100 nF Vfb = 29 V C2 220 µF (25 V) D4(2) D3 RCMP 270 kΩ M2 0 D1 7 OUTA INA 1 C6 2.2 nF RCV1 2.2 kΩ (1%) 9 DEFLECTION CONTROLLER M4 9 INPUT AND FEEDBACK CIRCUIT RS 2.7 kΩ 4 RCV2 2.2 kΩ (1%) deflection coil 8.82 mH 7.9 Ω (W66ESF) RM 1.5 Ω M1 INB 2 C7 2.2 nF FEEDB RD1 330 Ω (1) CD 47 nF RD2(1) 22 Ω Philips Semiconductors GUARD VP VP = 11 V Full bridge vertical deflection output circuit in LVDMOS k, full pagewidth 1999 Nov 10 RFB RGRD 12 kΩ OUTB M3 TDA8357J Vi(p-p) VI(bias) 5 GND 0 MGS807 Preliminary specification Fig.4 Application diagram. TDA8357J fvert = 50 Hz; tFB = 640 µs; II(bias) = 400 µA; Ii(dif)(peak) = 494 µA; Io(p-p) = 1.45 A. (1) Optional, depending on the deflection coil impedance. (2) Optional extended flash over protection; BYD33D or equivalent. Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J The flyback supply voltage calculated this way is about 5% to 10% higher than required. Supply voltage calculation For calculating the minimum required supply voltage, several specific application parameter values have to be known. These parameters are the required maximum (peak) deflection coil current Icoil(peak), the coil parameters Rcoil and Lcoil, and the measuring resistance of RM. The required maximum (peak) deflection coil current should also include the overscan. Calculation of the power dissipation of the vertical output stage The IC total power dissipation is given by the formula: Ptot = Psup − PL The power to be supplied is given by the formula: The deflection coil resistance has to be multiplied with 1.2 in order to take account of hot conditions. I coil ( peak ) P sup = V P × ----------------------- + V P × 0.015 [A] + 0.3 [W] 2 Chapter “Characteristics” supplies values for the voltage losses of the vertical output stage. For the first part of the scan the voltage loss is given by Vloss(1). For the second part of the scan the voltage loss is given by Vloss(2). In this formula 0.3 [W] represents the average value of the losses in the flyback supply. The average external load power dissipation in the deflection coil and the measuring resistor is given by the formula: The voltage drop across the deflection coil during scan is determined by the coil impedance. For the first part of the scan the inductive contribution and the ohmic contribution to the total coil voltage drop are of opposite sign, while for the second part of the scan the inductive part and the ohmic part have the same sign. 2 ( I coil ( peak ) ) P L = -------------------------------- × ( R coil + R M ) 3 For the vertical frequency the maximum frequency occurring must be applied to the calculations. Example Table 1 The required power supply voltage VP for the first part of the scan is given by: SYMBOL Icoil(peak) V P ( 1 ) = I coil ( peak ) × ( R coil + R M ) – L coil × 2I coil ( peak ) × f vert ( max ) + V loss ( 1 ) Icoil(p-p) Lcoil Rcoil RM fvert tFB The required power supply voltage VP for the second part of the scan is given by: V P ( 2 ) = I coil ( peak ) × ( R coil + R M ) + L coil × 2I coil ( peak ) × f vert ( max ) + V loss ( 2 ) The minimum required supply voltage VP shall be the highest of the two values VP(1) and VP(2). Spread in supply voltage and component values also has to be taken into account. Table 2 R coil + R M = I coil ( p –p ) × -------------------------– t FB ⁄ x 1–e Psup PL Ptot where: L coil x = -------------------------R coil + R M 10 UNIT 0.725 1.45 8.82 7.9 1.5 A A mH Ω Ω 50 Hz 640 µs SYMBOL If the flyback time is known, the required flyback supply voltage can be calculated by the simplified formula: 1999 Nov 10 VALUE Calculated values VP RM + Rcoil (hot) tvert x VFB Flyback supply voltage calculation V FB Application values VALUE UNIT 11 11 0.02 0.000802 V Ω s 29 4.45 1.93 2.52 V W W W Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J Heatsink calculation The required heatsink thermal resistance is given by: The value of the heatsink can be calculated in a standard way with a method based on average temperatures. The required thermal resistance of the heatsink is determined by the maximum die temperature of 150 °C. In general we recommend to design for an average die temperature not exceeding 130 °C. T j – T amb R th ( h – a ) = ----------------------- – ( R th ( j – c ) + R th ( c – h ) ) P tot When we use the values given we find: 110 – 40 R th ( h – a ) = ---------------------- – ( 5 + 2 ) = 16 K/W 3.0 EXAMPLE The heatsink temperature will be: Measured or given values: Ptot = 3 W; Tamb = 40 °C; Tj = 110 °C; Rth(j-c) = 5 K/W; Rth(c-h) = 2 K/W. 1999 Nov 10 Th = Tamb + (Rth(h-a) × Ptot) = 40 + (3 × 16) = 90 °C 11 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J INTERNAL PIN CONFIGURATION PIN 1 SYMBOL EQUIVALENT CIRCUIT INA 1 300 Ω MBL100 2 INB 2 300 Ω MBL102 3 VP 4 OUTB 5 GND 6 VFB 7 OUTA 6 3 7 4 MGS805 1999 Nov 10 12 5 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS PIN 8 SYMBOL TDA8357J EQUIVALENT CIRCUIT GUARD 300 Ω 8 MBL103 9 FEEDB 300 Ω 9 MBL101 1999 Nov 10 13 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J PACKAGE OUTLINE DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad ,, ,, non-concave x SOT523-1 q1 Eh Dh D D1 view B: mounting base side P A2 k q2 B E q L2 L3 L1 L 1 9 e1 Z e Q w M bp 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT A2(2) bp mm c D(1) D1(2) Dh E(1) Eh 2.7 0.80 0.58 13.2 2.3 0.65 0.48 12.8 10 mm v M c e2 m e e1 e2 L L1 L2 L3 m 6.2 14.7 3.0 12.4 11.4 6.7 3.5 3.5 2.54 1.27 5.08 5.8 14.3 2.0 11.0 10.0 5.5 4.5 3.7 2.8 k P Q q q1 q2 3.4 1.15 17.5 4.85 3.8 3.1 0.85 16.3 3.6 v 0.8 w x 0.3 0.02 Z(1) 1.65 1.10 Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Plastic surface within circle area D1 may protrude 0.04 mm maximum. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 98-11-12 SOT523-1 1999 Nov 10 EUROPEAN PROJECTION 14 Philips Semiconductors Preliminary specification Full bridge vertical deflection output circuit in LVDMOS TDA8357J The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction to soldering through-hole mount packages The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL WAVE suitable(1) suitable Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 10 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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