INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4002B gates Dual 4-input NOR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4002B gates Dual 4-input NOR gate DESCRIPTION The HEF4002B provides the positive dual 4-input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4002BP(N): 14-lead DIL; plastic HEF4002BD(F): 14-lead DIL; ceramic (cerdip) (SOT27-1) (SOT73) HEF4002BT(D): 14-lead SO; plastic (SOT108-1) Fig.1 Functional diagram. ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4002B gates Dual 4-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On 5 LOW to HIGH package (P) 60 120 ns 33 ns + (0,55 ns/pF) CL 50 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 VDD V dissipation per TYPICAL EXTRAPOLATION FORMULA MAX. 25 tPHL; tPLH tTHL tTLH 15 Dynamic power TYP. 15 10 Output transition times HIGH to LOW SYMBOL TYPICAL FORMULA FOR P (µW) 5 1050 fi + ∑ (foCL) × VDD2 where 10 4300 fi + ∑ (foCL) × VDD fi = input freq. (MHz) 15 11 700 fi + ∑ (foCL) × 2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3