PHILIPS TDA8020HL

INTEGRATED CIRCUITS
DATA SHEET
TDA8020HL
Dual smart card interface
Product specification
Supersedes data of 2001 May 29
File under Integrated Circuits, IC02
2001 Aug 15
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
FEATURES
• Two independent 6 contacts smart card interfaces
• Supply voltage to the cards; VCC = 5 or 3 V ±5%; ICC up
to 65 mA
• Integrated DC/DC converter (doubler, tripler or follower)
for allowing power supply from 2.5 to 6.5 V
• Independant supply voltage for interface signals (from
1.5 to 6.5 V)
APPLICATIONS
• Set top boxes
• Control and status via the I2C-bus
• Banking terminals
• Four possible devices in parallel due to two I2C-bus
address pins
• Internet terminals.
• Electrical specifications according to ISO 7816 or
EMV norms
GENERAL DESCRIPTION
• Automatic activation and deactivation sequences by
means of integrated sequencers
The TDA8020HL is a one-chip dual smart card interface.
Controlled by the I2C-bus, it guarantees conformity to
ISO 7816 or EMV norms with very few external
components.
• Automatic clock count and reset toggling during warm or
cold reset
• Interrupt request output to the controller
• 6 kV ESD protection on cards contacts
• Automatic emergency deactivation in the event of
supply drop-out, overload, overheating or card take-off
• Current limitation on pins CLK, RST, I/O and VCC
• Integrated voltage supervisor for power-on reset and
drop-out detection
• Power-down mode with several wake-up events.
ORDERING INFORMATION
TYPE
NUMBER
TDA8020HL
2001 Aug 15
PACKAGE
NAME
LQFP32
DESCRIPTION
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
2
VERSION
SOT358-1
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD
supply voltage on pins VDD and
VDDA
2.5
−
6.5
V
VDDI
supply voltage for interface
signals
1.5
−
VDD
V
IDD
supply current (IDD and IDDA)
VDD = 3.3 V; inactive mode
−
−
150
µA
VDD = 3.3 V; Power-down mode;
2 cards activated; VCC1 = VCC2 = 5 V;
ICC1 = ICC2 = 100 µA;
CLK1 and CLK2 stopped
−
−
2
mA
VDD = 3.3 V; active mode;
VCC1 = VCC2 = 5 V;
ICC1 + ICC2 = 80 mA;
CLK1 = CLK2 = 5 MHz
−
−
400
mA
VDD = 3.3 V; active mode;
VCC1 = VCC2 = 3 V;
ICC1 = ICC2 = 10 mA;
CLK1 = CLK2 = 5 MHz
−
−
80
mA
5 V card
4.75
−
5.25
V
3 V card
VCC1, VCC2
supply voltage for card 1 and 2 note 1
2.80
−
3.20
V
ICC1, ICC2
supply current for card 1 and 2
0
−
55
mA
Vth1
threshold voltage for the
supervisor on VDD
2.1
−
2.4
V
Vhys1
hysteresis on Vth1
50
−
100
mV
Tamb
ambient temperature
−25
−
+85
°C
Note
1. Both cards are not allowed to operate at maximum current at the same time at minimum supply voltage.
2001 Aug 15
3
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
BLOCK DIAGRAM
VDD
handbook, full pagewidth
SAP
14
20
SAM
19
SBP
15
SBM
17
16
CDEL
30
SUPPLY SUPERVISOR
VOLTAGE REFERENCE
DC/DC
CONVERTER
13
VDDA
VUP
TDA8020HL
3
INTERNAL
OSCILLATOR
CLOCK
CIRCUITRY
5
4
CARD1
DRIVERS
SAD0
SAD1
SCL
SDA
IRQ
2
23
32
24
21
22
SEQUENCER1
I 2C-BUS
AND
REGISTERS
1
9
10
26
CARD2
DRIVERS
27
28
LEVEL
SHIFTERS
CGND1
I/O1
PRES1
8
CLK2
RST2
VCC2
CGND2
I/O2
SEQUENCER2
7
PRES2
31
18
12
FCE834
AGND
GND
Fig.1 Block diagram.
2001 Aug 15
VCC1
6
I/O2uC
VDDI
11
29
CLKIN1
I/O1uC
RST1
25
CLOCK
CIRCUITRY
CLKIN2
CLK1
4
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
PINNING
SYMBOL
PIN
DESCRIPTION
PRES1
1
card 1 presence contact input (active HIGH)
CGND1
2
ground connection output to card 1 (C5 contact)
CLK1
3
clock output to card 1 (C3 contact)
VCC1
4
supply voltage output to card 1 (C1 contact); decouple to pin CGND1 with 2 × 100 nF
capacitors with ESR < 100 mΩ
RST1
5
reset output to card 1 (C2 contact)
I/O2
6
I/O contact to card 2 (C7 contact); internal 15 kΩ pull-up resistance to pin VCC2
PRES2
7
card 2 presence contact input (active HIGH)
CGND2
8
ground connection output to card 2 (C5 contact)
CLK2
9
clock output to card 2 (C3 contact)
VCC2
10
supply voltage output to card 2 (C1 contact); decouple to pin CGND2 with 2 × 100 nF
capacitors with ESR < 100 mΩ
RST2
11
reset output to card 2 (C2 contact)
GND
12
ground connection
VUP
13
output of DC/DC converter; a 220 nF capacitor with ESR < 100 mΩ must be connected
to pin AGND
SAP
14
capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
SBP
15
capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
VDDA
16
analog supply voltage for the DC/DC converter
SBM
17
capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SBP and SBM
AGND
18
analog ground connection for the DC/DC converter
SAM
19
capacitors connection for the DC/DC converter; a 220 nF capacitor with
ESR < 100 mΩ must be connected between pins SAP and SAM
VDD
20
power supply voltage
SCL
21
serial clock input of the I2C-bus (open drain)
SDA
22
serial data input/output of the I2C-bus (open drain)
SAD0
23
I2C-bus address selection input 0
SAD1
24
I2C-bus address selection input 1
IRQ
25
interrupt request output to host (open drain; active LOW)
CLKIN1
26
external clock input for card 1
I/O1uC
27
I/O connection to host for card 1; internal 22 kΩ pull-up resistor to VDDI
I/O2uC
28
I/O connection to host for card 2; internal 22 kΩ pull-up resistor to VDDI
CLKIN2
29
external clock input for card 2
CDEL
30
delay capacitor connection for the voltage supervisor (1 ms per 2 nF)
VDDI
31
interface signals reference supply voltage
I/O1
32
I/O contact to card 1 (C7 contact); internal 15 kΩ pull-up resistor to VCC1
2001 Aug 15
5
Philips Semiconductors
Product specification
PRES1
1
24 SAD1
CGND1
2
23 SAD0
CLK1
3
22 SDA
VCC1
4
RST1
5
20 VDD
I/O2
6
19 SAM
PRES2
7
18 AGND
CGND2
8
17 SBM
21 SCL
6
VDDA 16
SBP 15
SAP 14
VUP 13
GND 12
RST2 11
VCC2 10
CLK2
9
TDA8020HL
Fig.2 Pin configuration.
2001 Aug 15
25 IRQ
26 CLKIN1
27 I/O1uC
28 I/O2uC
29 CLKIN2
32 I/O1
handbook, full pagewidth
30 CDEL
TDA8020HL
31 VDDI
Dual smart card interface
FCE833
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
A specific reference supply voltage, VDDI, is used for the
interface signals CLKIN1, CLKIN2, I/O1uC, I/O2uC,
SAD0, SAD1, SCL, SDA and IRQ, which can be lower
than VDD (minimum 1.5 V), thus allowing direct control with
a low voltage supplied device.
FUNCTIONAL DESCRIPTION
Throughout this specification, it is assumed that the reader
is familiar with ISO 7816 norm terminology.
Supply
Pins SCL, SDA and IRQ are open-drain outputs, and may
be externally pulled up to a voltage higher than VDD.
The TDA8020HL operates with a supply voltage from
2.5 to 6.5 V. An integrated voltage supervisor ensures that
no spike appears on cards contacts during power-on or off.
The supervisor also initializes the device, and forces an
automatic emergency deactivation of the contacts in the
event of a supply drop-out.
I2C-bus
A 400 kHz I2C-bus slave interface is used for configuring
the device and reading the status. The bus has
2 addresses, one for each card. 4 devices may be used in
parallel due to the address selection pins SAD0 and SAD1
(see Table 1).
As long as the supply voltage is below the threshold
voltage Vth1, the capacitor CDEL remains uncharged. When
the supply voltage reaches Vth1 and Vhys1, then CDEL is
charged with a small current source of approximately 2 µA.
When the voltage on CDEL reaches Vth2, then the
supervisor is no longer active. As long as the supervisor is
active (pin IRQ is LOW), bit SUPL in the status register is
set. When pin IRQ goes HIGH the supervisor becomes
inactive (see Fig.3).
Table 1
Proposed addresses
PIN SAD1
PIN SAD0
CARD 1
CARD 2
LOW
LOW
40H
48H
Separate supply pins are used for the DC/DC converter,
allowing specific decoupling for counteracting the noise
the switching transistors may induce on the supply.
LOW
HIGH
42H
4AH
HIGH
LOW
44H
4CH
HIGH
HIGH
46H
4EH
handbook, full pagewidth
VDD
Vth1 + Vhys1
Vth1
Vth2
VCDEL
IRQ
tw
tw
status read
after event
BUS NOT RESPONDING
BUS OK
BUS NOT
RESPONDING
BUS OK
BUS NOT
RESPONDING
FCE835
Fig.3 Supply supervisor.
2001 Aug 15
7
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
WRITING COMMANDS
START, ADDRESS, WRITE, CONTROL byte, STOP.
Table 2
CONTROL bits (all bits cleared after power-on)
NAME
BIT
DESCRIPTION
START/STOP
0
when set, initiates an activation and a cold reset procedure; when reset, initiates a
deactivation sequence
WARM
1
when set, initiates a warm reset procedure; automatically reset by hardware when the card
starts answering or when the card is declared mute
3 and 5 V
2
when set, VCC = 3 V; when reset, VCC = 5 V
PDOWN
3
when set, the configuration defined by bit CLKPD is applied on pin CLK, and the circuit
enters the Power-down mode; when reset, the circuit goes back to normal (active) mode
CLKPD
4
when set, CLK is stopped HIGH during Power-down mode; when reset, CLK is stopped LOW
in Power-down mode
CLKSEL1
5
bits 5 and 6 determine the clock to the card in normal mode according to Table 3
CLKSEL2
6
I/OEN
7
when set, I/O is transferred on I/OuC; when reset, I/O to I/OuC is high-impedance
When deactivating the card, by resetting the START bit,
only bit 0 must be changed.
All frequency changes are synchronous, thus ensuring
that no pulse is shorter than 45% of the smallest period.
For cards power reduction modes, CLKIN may be stopped
after switching to STOP LOW or STOP HIGH. CLKIN
should be restarted before leaving this mode.
The clock to the cards in active mode is selected with
bits CLKSEL1 and CLKSEL2; see Table 3.
Table 3
Selecting the card clock.
BIT CLKSEL2
BIT CLKSEL1
CLOCK
OUTPUT
0
0
CLKIN/8
0
1
CLKIN/4
1
0
CLKIN/2
1
1
CLKIN
2001 Aug 15
A correct duty factor can not be guaranteed in the CLKIN
configuration, as it depends on the duty factor of the
CLKIN signal.
8
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
READING STATUS
START, ADDRESS, READ, STATUS byte, STOP.
Table 4
STATUS bits (all bits cleared after power-on, except SUPL and PRES)
NAME
BIT
DESCRIPTION
PRES
0
set when the card is present; reset when the card is not present
PRESL
1
set when the card has been inserted or extracted; reset when the status has been read
I/O
2
set when I/O is HIGH and reset if I/O is LOW
SUPL
3
set when the supervisor has signalled a fault; reset when the status has been read
PROT
4
set when an overload or an overheating has occurred during a session; reset when the
status has been read
MUTE
5
set during ATR when the selected card has not answered during the ISO 7816 time slots
EARLY
6
set during ATR when the selected card has answered too early
ACTIVE
7
set if the card is active; reset if the card is inactive
When one of the bits PRESL, MUTE, EARLY and PROT is set, then pin IRQ goes LOW until the status byte has been
read. After power-on, bit SUPL is set until the status byte has been read, and pin IRQ is LOW until the supervisor
becomes inactive.
DC/DC converter
If VDD > 3 V, for 5 V cards, then both cards can draw up to
55 mA at the same time.
VCC1 is the supply voltage for card 1 contacts, VCC2 for
card 2 contacts. Card 1 and card 2 may be independently
powered-down, powered at 5 V or powered at 3 V. A
capacitor type step-up converter is used for generating
these voltages. This step-up converter acts either as a
doubler, tripler or follower.
If VDD > 3.3 V, for 3 V cards, then both cards can draw up
to 50 mA at the same time.
The DC/DC converter is powered with specific pins (VDDA
and AGND) to enable separate decoupling.
The output voltage, VUP, is internally fed to the VCC
generators. VCC1, VCC2 and CGND1, CGND2 are used as
a reference for all other cards contacts.
If VCC is the maximum value of VCC1 and VCC2, then there
are 4 possible situations:
• VDD = 3 V and VCC = 3 V: in this case, the DC/DC
converter acts as a doubler with a regulation of
approximately 4.0 V
Sequencers and clock counter
Two sequencers are used to ensure activation and
deactivation sequences according to ISO 7816 and
EMV norms, even in the event of an emergency (card
removal during transaction, supply drop-out and hardware
problem).
• VDD = 3 V and VCC = 5 V: in this case, the DC/DC
converter acts as a tripler with a regulation of
approximately 5.5 V
• VDD = 5 V and VCC = 3 V: in this case, the DC/DC
converter acts as a follower: VDD is applied on VUP
The sequencers are clocked by the internal oscillator.
• VDD = 5 V and VCC = 5 V: in this case, the DC/DC
converter acts as a doubler with a regulation of
approximately 5.5 V.
The activation of a card is initiated by setting the card
select bit and the start bit within the control register. This is
only possible if the card is present and if the voltage
supervisor is not active.
The switch between the modes is automatically executed
when VDD is approximately 3.4 V.
During activation the DC/DC converter is initiated (except
if another card is already powered up or if VDD = 5 V and
VCC = 3 V). VCC then goes high to the selected voltage
(3 or 5 V), the I/O lines are then enabled and the clock is
started with RST LOW.
Each card may independently draw a current up to 65 mA,
also during activation, with a supply voltage from 2.5 V up
to 6.5 V provided the sum of ICC1 and ICC2 does not
exceed 80 mA.
2001 Aug 15
9
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
If a start bit is detected on the I/O during the first 200 CLK
pulses, then it is omitted. If a start bit is detected between
200 and 352 CLK pulses, then bit EARLY is set in the
status register. If the card starts answering before
41950 CLK pulses, then RST remains LOW level. If not,
after 41950 CLK pulses, RST is toggled HIGH. If, again, a
start bit is detected within 352 CLK pulses, bit EARLY is
set in the status register. If the card does not answer
before 41950 new CLK pulses, then bit MUTE is set in the
status register. If the card answers within the correct
window, then the CLK count is stopped and the system
controller may send commands to the card.
Activation sequence
Deactivation is initiated either by the system controller
(reset bit START), or automatically in the event of a
hardware problem or supply drop-out. With a supply
drop-out both cards are deactivated at the same time.
• VCC starts rising from 0 to 5 or 3 V with a controlled rise
time of 0.14 V/µs typical (t2)
During deactivation, RST goes LOW, the clock is stopped
and the I/O lines go LOW. VCC then goes low with a
controlled slope and the DC/DC converter is stopped if no
card is active.
• CLK is sent to the card and RST is enabled (t4 = tact).
When the cards are inactive, VCC, CLK, RST and I/O are
LOW, with low impedance with respect to CGND. The
DC/DC converter is stopped.
When everything is satisfactory (voltage supply, card
present and no hardware problems), the system controller
may initiate an activation sequence of a present card
(see Fig.4):
• The DC/DC converter is started (t1). If one card was
already active, then the DC/DC converter was already
on, and nothing more occurs at this step
• I/O rises to VCC (t3); internal 10 kΩ pull-up resistors to
VCC
If the card does not answer within the first 41950 CLK
cycles, then RST is raised HIGH (t5).
The sequencer is clocked by fint/64 which leads to a time
interval T of 25 µs typical. Thus t1 = 0 to T/64;
t2 = t1 + 3T/2; t3 = t1 + 7T/2 and t4 = t1 + 4T.
Outside a session, cards contacts are forced low
impedance to CGND.
handbook, full pagewidth
START/STOP
VUP
VCC
I/O
CLK
RST
t0 t1
t2
t3
t4
t5
ATR
FCE837
t4 = tact.
Fig.4 Activation sequence.
2001 Aug 15
10
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
Deactivation sequence
t11 = t10 + T/64; t12 = t11 + T/2; t13 = t11 + T;
t14 = t11 + 3T/2; t15 = t11 + 7T/2.
When the session is completed, the microcontroller resets
bit START/STOP to logic 0 (t10). The circuit then executes
an automatic deactivation sequence (see Fig.5):
The deactivation time tde is the time that VCC needs to drop
below 0.4 V from START/STOP to logic 0 (t10).
• Card reset (RST falls LOW) (t11)
• CLK is stopped (t12)
• I/O falls to 0 V (t13)
• VCC falls to 0 V with typical 0.14 V/µs slew rate (t14)
• The DC/DC converter is stopped (if both cards are
inactive) and CLK, RST, VCC and I/O become low
impedance to CGND (t15).
handbook, full pagewidth
START/STOP
RST
CLK
I/O
VCC
VUP
t de
t10 t11
t12
FCE836
t13
t14
Fig.5 Deactivation sequence.
2001 Aug 15
11
t15
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
Clock inputs and data inputs/outputs to the system
controller
Protections
The current on pin CLK is limited to ±70 mA.
The current on pin RST is limited to ±20 mA; if the current
reaches this value with RST LOW, then an emergency
deactivation sequence is performed, IRQ is pulled LOW
and bit PROT is set in the status register.
CLKIN1 is the input clock for card 1, CLKIN2 for card 2.
They may be driven separately from the system controller,
or be tied together externally and driven with the same
signal.
The current on pins I/O is limited to +15 and −15 mA.
An RC filter is needed on these lines in order to limit the
influence of possible fast transitions.
The current on VCC is limited to 90 mA; if ICC reaches this
value, then an emergency deactivation sequence is
performed, IRQ is pulled LOW and bit PROT is set in the
status register.
I/O1uC is the data signal to or from card 1, I/O2uC to or
from card 2. They can be driven separately from the
system controller, in which case both bits I/OEN may be
set to logic 1. They can also be driven by the same signal,
in which event they have to be tied together externally, but
each bit I/OEN has to be set or reset according to the
addressed card.
In the event of overcurrent on VCC, card take-off during a
session, overheating, or overcurrent on RST, then the
TDA8020HL performs an automatic emergency
deactivation sequence on the corresponding card, resets
bit START/STOP and pulls pin IRQ LOW.
In the event of overheating or supply drop-out, the
TDA8020HL performs an automatic emergency
deactivation sequence on both cards, resets both bits
START/STOP and pulls pin IRQ LOW.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage on pins VDD and VDDA
−0.5
+6.5
V
VDDI
supply voltage for interface signals
−0.5
+6.5
V
Vn
input voltage
on pins SAP, SAM, SBP, SBM and VUP
−0.5
+7.5
V
on all other pins
−0.5
VDD + 0.5 V
from or to pins SAP, SAM, SBP, SBM
and VUP
−200
+200
mA
from or to all other pins
−5
+5
mA
In
DC current
Ptot
total power dissipation
−
460
mW
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−
125
°C
Ves
electrostatic discharge voltage
on pins I/O1, VCC1, RST1, CLK1,
CGND1, PRES1, I/O2, VCC2, RST2,
CLK2, CGND2 and PRES2
−6
+6
kV
on all other pins
−2
+2
kV
2001 Aug 15
Tamb = −20 to +85 °C
12
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
80
K/W
in free air
CHARACTERISTICS
VDD = 3.3 V; VDDI = 1.5 V; fCLKIN1 = fCLKIN2 = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Temperature
ambient temperature
−25
−
+85
°C
VDD
supply voltage on pins VDD
and VDDA
2.5
−
6.5
V
IDD
supply current (IDD and IDDA) inactive mode
−
−
150
µA
Power-down mode; 2 cards
activated; VCC1 = VCC2 = 5 V;
ICC1 = ICC2 = 100 µA; CLK1 and
CLK2 stopped
−
−
2.5
mA
active mode; VCC1 = VCC2 = 5 V;
ICC1 + ICC2 = 80 mA;
CLK1 = CLK2 = 5 MHz
−
−
400
mA
active mode; VCC1 = VCC2 = 3 V;
ICC1 = ICC2 = 10 mA;
CLK1 = CLK2 = 5 MHz
−
−
80
mA
Tamb
Supply
VDDI
supply voltage for interface
signals
1.5
−
VDD
V
IDDI
supply current for interface
signals
−
−
120
µA
Vth1
threshold voltage on VDD
2.1
−
2.4
V
falling
Vhys1
hysteresis on Vth1
50
−
100
mV
Vth2
threshold voltage on
pin CDEL
−
1.38
−
V
VCDEL
voltage on pin CDEL
−
−
VDD + 0.3
V
ICDEL
output current at pin CDEL
tW
width of the internal ALARM
pulse
pin grounded (charge)
−
−2
−
µA
VCDEL = VDD (discharge)
−
5
−
mA
CDEL = 22 nF
−
10
−
ms
2
2.5
3
MHz
at least one 5 V card
−
5.5
−
V
both cards 3 V
−
4
−
V
−
3.4
−
V
DC/DC converter
fint
internal oscillator frequency
VUP
voltage on pin VUP
Vdt
detection voltage for doubler,
tripler and follower selection
2001 Aug 15
13
Philips Semiconductors
Product specification
Dual smart card interface
SYMBOL
TDA8020HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Card supply voltages (pins VCC1 and VCC2); note 1
output voltage in inactive
mode
no load
0
−
0.1
V
Iinactive = 1 mA
0
−
0.3
V
Iinactive
current from VCC when
inactive
pin grounded
−
−
−1
mA
VCC(ripple)
output voltage including
ripple
active mode; ICC < 65 mA;
5 V card; ICC1 + ICC2 < 80 mA;
2.5 V < VDD < 6.5 V
4.75
5
5.25
V
active mode; ICC < 65 mA;
3 V card; ICC1 + ICC2 < 80 mA;
2.5 V < VDD < 6.5 V
2.8
3
3.2
V
active mode; current pulses of
40 nAs with I < 200 mA and
t < 400 ns; f < 20 MHz; 5 V card
4.6
−
5.4
V
active mode; current pulses of
24 nAs with I < 200 mA and
t < 400 ns; f < 20 MHz; 3 V card
2.76
−
3.24
V
active mode; VDD > 3 V;
ICC1 < 55 mA; ICC2 < 55 mA;
5 V cards
4.6
−
5.4
V
active mode; VDD > 3.3 V;
ICC < 50 mA; ICC2 < 50 mA;
3 V cards
2.76
−
3.24
V
from 0 to 5 V (5 V card); the other −
card at full load; VDD > 3 V
−
−55
mA
from 0 to 3 V (3 V card); the other −
card at full load; VDD > 3.3 V
−
−50
mA
Vo(inactive)
VCC(load)
ICC
output voltage when both
slots fully loaded
output current
VCC shorted to GND
−
−
−100
mA
Vripple(p-p)
ripple voltage (peak-to-peak
value)
from 20 kHz to 200 MHz
−
−
350
mV
SR
slew rate
up or down (maximum
capacitance is 300 nF)
0.08
0.14
0.20
V/µs
Reset output to the cards (pins RST1 and RST2)
Vo(inactive)
output voltage in inactive
mode
no load
0
−
0.1
V
Iinactive = 1 mA
0
−
0.3
V
Iinactive
current from pin RST when
inactive
pin grounded
0
−
−1
mA
VOL
LOW-level output voltage
IOL = 200 µA
0
−
0.3
V
VOH
HIGH-level output voltage
IOH < −200 µA
VCC − 0.5
−
VCC
V
tr
rise time
CL = 30 pF
−
−
0.1
µs
tf
fall time
CL = 30 pF
−
−
0.1
µs
2001 Aug 15
14
Philips Semiconductors
Product specification
Dual smart card interface
SYMBOL
TDA8020HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock output to the cards (pins CLK1 and CLK2)
output voltage in inactive
mode
no load
0
−
0.1
V
Iinactive = 1 mA
0
−
0.3
V
Iinactive
current from pin CLK when
inactive
pin grounded
0
−
−1
mA
Vo(inactive)
VOL
LOW-level output voltage
IOL = 200 µA
0
−
0.3
V
VOH
HIGH-level output voltage
IOH < −200 µA
VCC − 0.5
−
VCC
V
tr
rise time
CL = 30 pF
−
−
8
ns
tf
fall time
CL = 30 pF
−
−
8
ns
fclk
clock frequency
1 MHz Idle configuration
1
−
1.5
MHz
operational
0
−
10
MHz
δ
duty factor
CL = 30 pF
45
−
55
%
SR
slew rate (rise and fall)
CL = 30 pF
0.2
−
−
V/ns
Data lines (pins I/O1 and I/O2); note 2
output voltage in inactive
mode
no load
0
−
0.1
V
Iinactive = 1 mA
−
−
0.3
V
Iinactive
current from pin I/O when
inactive
pin grounded
−
−
−1
mA
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.3
V
VOH
HIGH-level output voltage
no DC load
0.9VCC
−
VCC + 0.1
V
IOH < −20 µA
0.8VCC
−
VCC + 0.1
V
IOH < −40 µA
Vo(inactive)
0.75VCC
−
VCC + 0.1
V
Iedge
current from pins I/O1
VOH = 0.9VCC; CL = 80 pF
and I/O2 when active pull-up
−1
−
−
mA
td(edge)
delay between falling edge
on pins I/O1, I/O2, I/O1uC,
I/O2uC and width of active
pull-up pulse
−
500
650
ns
VIL
LOW-level input voltage
−0.3
−
+0.8
V
VIH
HIGH-level input voltage
1.5
−
VCC
V
IIL
LOW-level input current on
pin I/O
VIL = 0
−
−
600
µA
ILIH
HIGH-level input leakage
current on pin I/O
VIH = VCC
−
−
10
µA
ti(r), ti(f)
input transition times
from VIL(max) to VIH(min)
−
−
1.5
µs
to(r), to(f)
output transition times
CL < 80 pF; no DC load;
10% to 90% from 0 to
VCC1 and VCC2
−
−
0.1
µs
Ci
input capacitance on
pins I/O1 and I/O2
−
−
10
pF
Rpu(int)
internal pull-up resistance
between pin I/O and VCC
12
15
18
kΩ
2001 Aug 15
15
Philips Semiconductors
Product specification
Dual smart card interface
SYMBOL
fmax
TDA8020HL
PARAMETER
CONDITIONS
maximum frequency on
pins I/O1 and I/O2
MIN.
TYP.
MAX.
UNIT
−
−
500
kHz
Data lines (pins I/O1uC and I/O2uC); note 3
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.4
V
VOH
HIGH-level output voltage
no DC load
0.9VDDI
−
VDDI + 0.2
V
IOH < −10 µA
0.75VDDI
−
VDDI + 0.2
V
VIL
LOW-level input voltage
−0.3
−
0.25VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
−
VDDI + 0.3
V
IIL
LOW-level input current
VIL = 0
−
−
600
µA
ILIH
HIGH-level input leakage
current
VIH = VDDI
−
−
10
µA
ti(r), ti(f)
input transition times
from VIL(max) to VIH(min)
−
−
1
µs
to(r), to(f)
output transition times
CL < 30 pF; 10% to 90% from
0 to VDDI
−
−
0.1
µs
Rpu(int)
internal pull-up resistance
between I/O1uC, I/O2uC and VDDI 15
22
30
kΩ
Timing
tact
activation sequence duration
−
−
135
µs
tde
deactivation sequence
duration
−
−
110
µs
Protections and limitations
ICC(sd)
shutdown and limitation
current at VCC1 and VCC2
−
−90
−
mA
II/O(lim)
limitation current on
pins I/O1 and I/O2
−15
−
+15
mA
ICLK(lim)
limitation current on
pins CLK1 and CLK2
−70
−
+70
mA
IRST(sd)
shutdown and limitation
current on pins RST1
and RST2
−20
−
+20
mA
Tj(sd)
shutdown die temperature
−
150
−
°C
−
−
0.3VDD
V
Card presence inputs (pins PRES1 and PRES2)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
−
−
V
ILIL
LOW-level input leakage
current
VI = 0
−
−
±20
µA
ILIH
HIGH-level input leakage
current
VI = VDD
−
−
±20
µA
2001 Aug 15
16
Philips Semiconductors
Product specification
Dual smart card interface
SYMBOL
TDA8020HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock inputs (pins CLKIN1 and CLKIN2)
fext
external frequency applied
on CLKIN1 and CLKIN2
0
−
25
MHz
VIL
LOW-level input voltage
0
−
0.25VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
−
VDDI + 0.3
V
ti(r), ti(f)
input transition times
−
−
100
ns
Logic inputs (pins SAD0 and SAD1)
VIL
LOW-level input voltage
−0.3
−
0.25VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
−
VDDI + 0.3
V
ILIL
LOW-level input leakage
current
−
−
±20
µA
ILIH
HIGH-level input leakage
current
−
−
±20
µA
Ci
input capacitance
−
−
10
pF
−
−
0.3
V
−
−
10
µA
Interrupt line (pin IRQ; open-drain; active LOW output)
VOL
LOW-level output voltage
ILH
HIGH-level leakage current
Io = 2 mA
Serial data input/output (pin SDA; open-drain)
VIL
LOW-level input voltage
−0.3
−
0.25VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
−
VDDI + 0.3
V
µA
ILH
HIGH-level leakage current
−
−
1
IIL
LOW-level input current
depends on the pull-up resistance −
−
−
VOL
LOW-level output voltage
IOL = 3 mA
−
−
0.3
V
Serial clock input (pin SCL; open-drain)
VIL
LOW-level input voltage
−0.3
−
0.25VDDI
V
VIH
HIGH-level input voltage
0.7VDDI
−
VDDI + 0.3
V
ILH
HIGH-level leakage current
−
−
1
µA
IIL
LOW-level input current
depends on the pull-up resistance −
−
−
Notes
1. Two ceramic multilayer capacitors of minimum 100 nF with low ESR should be used in order to meet these
specifications.
2. Pin I/O1 has an internal 15 kΩ pull-up resistor to VCC1 and pin I/O2 has an internal 15 kΩ pull-up resistor to VCC2.
3. Pins I/O1uC and I/O2uC have an internal 22 kΩ pull-up resistor to VDDI.
2001 Aug 15
17
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
22 nF
100
nF
18
I/O2
PRES2
0 kΩ
CGND2
100 kΩ
CLKIN1
I/O1uC
I/O2uC
CLKIN2
CDEL
IRQ
25
24
2
23
3
SAD1
SAD0
4
TDA8020HL
20
6
19
7
VDD
SAM
SBM
17
CLK2
10
11
12
13
14
15
16
220
nF
220 nF
100 nF
100 kΩ
+3.3 V
+3.3 V
33 µF
(16 V)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
EA
ALE
PSEN
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
10 µF
(16 V)
14.745 MHz
33 pF
FCE838
+3.3 V
Product specification
TDA8020HL
Fig.6 Application diagram.
P1_0
1
P1_1
2
P1_2
3
P1_3
4
P1_4
5
P1_5
6
P1_6
7
P1_7
8
RST
9
P3_0
10
P3_1
11
P3_2
12
P3_3
13
P3_4
14
P3_5
15
P3_6
16
P3_7
17
XTAL2
18
XTAL1
19
VSS
20
33 pF
100 nF
100 nF
K1
K2
220 nF
AGND
18
8
10 µF
SCL
21
5
+1.5 V
SDA
22
9
100
nF
10 pF
1
CARD_READ_LM01
C8
C7
C6
C5
C1I
C2I
C3I
C4I
26
1.5 to
6.5 kΩ
1 kΩ
VDDA
RST1
27
SBP
100 nF
28
SAP
VCC1
29
VUP
CARD 1
30
GND
CLK1
31
RST2
CGND1
32
VDDI
I/O1
PRES1
K1
K2
C4
C3
C2
C1
C5I
C6I
C7I
C8I
220 Ω
100 nF
MICROCONTROLLER
100 kΩ
C8
C7
C6
C5
C1I
C2I
C3I
C4I
VCC2
C4
C3
C2
C1
C5I
C6I
C7I
C8I
Philips Semiconductors
+1.5 V
Dual smart card interface
CARD_READ_LM01
CARD 2
+1.5 to +6.5 V
10 µF
(16 V)
APPLICATION INFORMATION
andbook, full pagewidth
2001 Aug 15
+1.5 V
+3.3 V
0 kΩ
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
24
A
17
25
16
ZE
e
E HE
A A2 A
1
(A 3)
wM
θ
bp
Lp
L
pin 1 index
32
9
detail X
8
1
e
ZD
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.4
0.3
0.18
0.12
7.1
6.9
7.1
6.9
0.8
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.25
0.1
Z D (1) Z E (1)
0.9
0.5
0.9
0.5
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT358 -1
136E03
MS-026
2001 Aug 15
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
19
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2001 Aug 15
20
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, HBGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DATA SHEET STATUS
DATA SHEET STATUS(1)
PRODUCT
STATUS(2)
DEFINITIONS
Objective data
Development
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Aug 15
21
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2001 Aug 15
22
Philips Semiconductors
Product specification
Dual smart card interface
TDA8020HL
NOTES
2001 Aug 15
23
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected]
© Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp24
Date of release: 2001
Aug 15
Document order number:
9397 750 08605