INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4517B LSI Dual 64-bit static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4517B LSI Dual 64-bit static shift register When PE/EO is LOW the outputs are enabled and the device is in the 64-bit serial mode. DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock, regardless of the state of PE/EO. When PE/EO is HIGH the outputs are disabled (high impedance OFF-state), the 64-bit shift register is divided into four 16-bit shift registers with D, O16, O32 and O48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4517B LSI Dual 64-bit static shift register Fig.2 Pinning diagram. HEF4517BP(N): 16-lead DIL; plastic (SOT38-1) HEF4517BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4517BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING CPA, CPB clock inputs PE/EOA, PE/EOB parallel input-enable/output-enable inputs DA, DB data inputs O16A, O32A, O48A 3-state outputs/inputs O16B, O32B, O48B 3-state outputs/inputs O64A, O64B 3-state outputs January 1995 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Dual 64-bit static shift register January 1995 4 Product specification HEF4517B LSI Fig.3 Logic diagram (one shift register). This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INPUTS/OUTPUTS MODE CP D O16 PE/EO O32 O48 O64 data entered into 1st bit L content of 16th bit displayed content of 32nd bit displayed content of 48th bit displayed content of 64th bit displayed One 64-bit shift register. The content of the shift register is shifted over one stage data entered into 1st bit H data at O16 entered into 17th bit data at O32 entered into 33rd bit data at O48 entered into 49th bit remains in ‘Z’ state Four 16-bit shift register. The content of the shift registers is shifted over one stage. X L no change no change no change no change no change X H Z no change Notes Z Z Z Philips Semiconductors INPUTS Dual 64-bit static shift register January 1995 FUNCTION TABLE 5 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance state = positive-going transition = negative-going transition Product specification HEF4517B LSI Philips Semiconductors Product specification HEF4517B LSI Dual 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V TYPICAL FORMULA FOR P (µW) 5 7 000 fi + ∑ (foCL) × VDD2 dissipation per 10 package (P) 15 28 000 fi + ∑ (foCL) × VDD2 70 000 fi + ∑ (foCL) × VDD2 Dynamic power where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CP → On HIGH to LOW LOW to HIGH 5 220 440 ns 193 ns + (0,55 ns/pF) CL 85 170 ns 74 ns + (0,23 ns/pF) CL 15 60 120 ns 52 ns + (0,16 ns/pF) CL 5 190 380 ns 163 ns + (0,55 ns/pF) CL 10 tPHL 75 150 ns 64 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 tPLH 15 Output transition times HIGH to LOW LOW to HIGH 5 10 10 tTHL tTLH 15 January 1995 6 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL Philips Semiconductors Product specification HEF4517B LSI Dual 64-bit static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Minimum clock pulse width; LOW SYMBOL MIN. TYP. 5 10 tWCPL 15 Set-up times On, D → CP Hold time On, D → CP 5 MAX. 95 190 ns 40 80 ns 30 60 ns 30 10 ns 25 5 ns 15 20 5 ns 5 45 15 ns 30 10 ns 25 10 ns 10 10 tsu thold 15 3-state propagation delays Output disable times PE/EO → On HIGH LOW 5 40 80 ns 30 60 ns 15 25 50 ns 5 50 100 ns 30 60 ns 15 25 50 ns 5 45 90 ns 10 10 tPHZ tPLZ Output enable times PE/EO → On HIGH LOW 10 tPZH 25 50 ns 15 20 40 ns 5 60 120 ns 30 60 ns 25 50 ns 10 tPZL 15 Maximum clock pulse frequency 5 10 15 January 1995 fmax 2 5 MHz 6 12 MHz 8 16 MHz 7 see also waveforms Fig.4. Philips Semiconductors Product specification HEF4517B LSI Dual 64-bit static shift register Fig.4 Waveforms showing minimum clock pulse width, set-up and hold times for On (as data input) and D to CP. January 1995 8