ADF4193-TN-001_Loop_Filter_Design.pdf

ADF4193 PLL Loop Filter Design
Using ADI SimPLL
ADF4193-TN-001
Technical Note
LOOP FILTER DESIGN STEPS
GENERAL DESCRIPTION
This Technical Note shows how ADI SimPLL can be used to
design the loop filter for a PLL using the ADF4193.
This is illustrated using a worked example of a GSM/DCS-1800
TX synthesizer. The SimPLL file used in this example may be
downloaded from the ADF4193 Product Page on the web.
Following the recommendations in the Applications section of
the ADF4193 datasheet, a 13MHz PFD frequency with a 60kHz
final loop bandwidth is chosen for the GSM TX synthesizer.
15
SD Vdd
8,10,13
20 24
DVdd
Vp1 Vp2
CPo +
5
SW1
SWGND
Supply
29
R1A1
820
28
R1A2
6.20k
F out
11
SW2
27
Ref in
18
Reference
104MHz
17
23
Rset
2.40k
C1A
120pF
Integrated
Differential
Amplifier
LE
Data
CPo -
26
R3
160
SW3 3
31
Ain+
2
R1B2
6.20k
C2B
1.20nF
Aout
R2
1.80k
Ain-
L1
2.20mH
C3
270pF
CMR
1
R1B1
820
Gnd
19
Adjust the value of R2 from the default 1k to 1.8k so
that value of L1 is approx 2.2mH. The 2.2mH
inductor is recommended as the value of R3 becomes
too small with the next available inductor value of
1.5mH and is thus dominated by the SW3 Ron.
Select Tools-> Build This results in the loop filter
component values of Figure 1.
32
Vp3
25
ADF4193
V+
2.
30
RFin
/RFin
Use SimPLL to design the filter for desired loop BW
(60kHz in this example) with a 45° phase margin.
3.
7
AVdd
C2A
1.20nF
6
1.
C1B
120pF
Ct
30.0pF
VCO
38.0MHz/V
100n
Clock
R set
MUXOUT
16
SDGnd AGnd DGnd
14
4,22 9,12,21
Lock Detect
Out
Figure 1. Initial Loop filter Design
Phase Noise at 1.84GHz
In this example the input reference noise is set at -130dBc/Hz
by selecting Reference-> Phase Noise -> Point/Floor.
VCO noise is also added by selecting VCO -> Phase Noise ->
Point/Floor. The phase noise at 100kHz is set to -105dBc/Hz,
which results in a phase noise of -145dBc/Hz two decades up at
1MHz offset. This results in the SSB Phase Noise shown in
Figure 2. Also the VCO input capacitance is set to 30pF.
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 2. Phase Noise Profile in Initial Design
Rev.0
04-19-2005
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ADF4193-TN-001
Technical Note
The fast lock timers can be updated in ADI SimPLL by selecting
Chip -> Speedup Mode -> SW R1 8xBW. Following the
recommendations in the ADF4193 datasheet for a GSM TX
synthesizer, the ICP timeout is set to 28 (~8.6us with a 13MHz
PFD frequency) and the SW timeout is set to 35 (~10.8us).
With these timer values the charge pump current is reduced
from 64 × 104 uA to 1 × 104 uA, in 6 binary steps after ~8.6us.
ADI SimPLL shows this in the Phase Detector Output plot.
Phase Detector Output
The differential amplifier and loop filter switches provided on
the ADF4193 provide an additional degree of freedom in the
loop filter design that can be taken advantage of for increased
suppression of out-of-band spurs and noise from the PLL.
Since the optimum 45° phase margin for fast settling is only
needed in wide BW mode, extra spur and noise attenuation can
be achieved in narrow BW mode by increasing C3. E.g. from
270pF to 470pF. The will change the wide BW phase margin
slightly so R3 should be reduced to restore it to 45°. E.g. from
180 to 62 ohms. The phase margin in wide BW mode can be
observed by selecting Chip->Mode-> FL always and placing the
marker where the wide BW open loop gain is at 0dB, as shown
in Figure 6.
Loop Gain at 1.84GHz
0
5
10
15
20
25
30
Time (us)
100
Gain (dB)
Figure 3. Phase Detector Output plot from ADI SimPLL
The frequency and phase settling plots from ADI SimPLL with
these timer values are as follows:
Frequency
1.92
Frequency (GHz)
Amplitude
0
80
-20
60
-40
-60
40
-80
20
-100
0
-120
-20
-140
-40
-160
-60
1.90
1k
10k
100k
440kHz 0.3602dB -135.84 deg
1.88
-180
1M
10M
Frequency (Hz)
1.86
Figure 6. Loop Gain and Phase in Wide BW Mode
1.84
Phase Margin = 180° - 135.8° = 44.2°
1.82
The improved attenuation of out-of-band noise from the PLL
and spurs at offsets >100kHz can be seen in the blue trace of
Figure 7. The phase noise eventually becomes dominated by
VCO noise at offset frequencies >400kHz, however the
improvement in spur attenuation extends beyond this, up to the
self resonant frequency of the 2.2mH inductor (~2MHz). The
VCO noise contribution can be easily turned off in the
simulator by selecting Tools -> Individual Noise Control.
1.80
0
5
10
15
20
25
30
Time (us)
Figure 4. Frequency Settling Transient for a 75MHz Jump across the DSC1800 TX Band
Output Phase Error
20
15
Phase Noise at 1.84GHz
-90
10
Phase Noise (dBc/Hz)
Phase Error (deg)
Phase
5
0
-5
-10
-15
-20
0
5
10
15
20
25
30
Time (us)
-100
-110
-120
-130
-140
-150
-160
1k
Figure 5. Phase Settling Transient for a 75MHz Jump across the DCS-1800 TX
Band
Rev. 0 | Page 2 of 3
10k
100k
Figure 7. SSB Phase Noise Plots
1M
10M
Frequency (Hz)
Phase (deg)
PD Out (mA)
7
6
5
4
3
2
1
0
IMPROVED SPUR SUPPRESSION
Technical Note
ADF4193-TN-001
The improvement in far out attenuation is achieved with no
significant degradation to the lock time performance (see below
plots). This is because the phase margin in wide BW mode is
still at the optimum value of 45 degrees. The narrow BW
phase margin can be reduced down to 30° without any
noticeable impact on settling time. Going lower than this may
give rise to a slight ripple in the settled phase when the BW is
reduced.
Frequency
Frequency (GHz)
1.64
1.63
1.62
1.61
1.60
1.59
1.58
1.57
1.56
1.55
1.54
1.53
The final loop filter values for 60kHz/26MHz PFD are shown in
Figure 11. Figures 8 to 10 show the new frequency and phase
settling transients in blue overlaid on the original transients in
red.
0
5
10
15
20
0
25
30
Time (us)
8,10,13
20 24
DVdd
Vp1 Vp2
CPo +
5
SW1
SWGND
Supply
7
AVdd
29
R1A1
820
28
R1A2
6.20k
ADF4193
V+
F out
11
SW2
27
Ref in
18
Reference
104MHz
17
23
Rset
2.40k
LE
Data
CPo -
MUXOUT
20
C1A
120pF
Integrated
Differential
Amplifier
SW3 3
31
26
Ain+
2
25
R1B2
6.20k
C2B
1.20nF
R3
62.0
Aout
Ain-
R2
1.80k
L1
2.20mH
CMR
1
C1B
120pF
100n
Clock
R set
15
32
Vp3
R1B1
820
Gnd
19
10
30
RFin
/RFin
5
Figure 10. Frequency Error Plots
C2A
1.20nF
6
25
30
Time (us)
100M
10M
1M
100k
10k
1k
100
10
1
100m
Figure 8. Phase Settling Transients
15
SD Vdd
20
|Freq Error|
Abs Frequency Error (Hz)
Phase Error (deg)
Output Phase Error
5
15
Figure 9. Frequency Settling Transients
25
20
15
10
5
0
-5
-10
-15
-20
-25
0
10
16
SDGnd AGnd DGnd
14
4,22 9,12,21
Lock Detect
Out
Figure 11. Loop Filter Components for a DCS1800 TX Synthesizer
Rev. 0 | Page 3 of 3
C3
470pF
Ct
30.0pF
VCO
38.0MHz/V
25
30
Time (us)
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