Freescale Semiconductor Advance Information Document Number: MC33907-MC33908D2 Rev. 4.0, 2/2015 Power System Basis Chip with High Speed CAN and LIN Transceivers 33907 33908 The 33907/33908 SMARTMOS devices area multi-output, power supply, integrated circuit, including HSCAN and/or LIN transceivers, dedicated to the automotive market. Multiple switching and linear voltage regulators, including low-power mode (32 A) are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over wide input voltages (down to 2.7 V) and wide output current ranges (up to 1.5 A). The 33907/33908 include enhanced safety features, with multiple fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in enhanced high-speed CAN interface fulfills the ISO11898-2 and -5 standards. The LIN interface fulfills LIN protocol specifications 1.3, 2.0, 2.1, 2.2, and SAEJ2602-2 Features • Battery voltage sensing & MUX output pin • Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck • Switching mode power supply (SMPS) dedicated to MCU core supply, from 1.2 V to 3.3 V delivering up to 1.5 A • Multiple wake-up sources in low-power mode: CAN, LIN, and/or IOs • Six configurable I/Os • Linear voltage regulator dedicated to auxiliary functions, or to a sensor supply (VCCA tracker or independent), 5.0 V or 3.3 V • Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V POWER SYSTEM BASIS CHIP AE SUFFIX (PB-FREE) 98ASA00173D 48-PIN LQFP-EP Applications • Electrical power steering • Engine management • Battery management • Active suspension • Gear box • Transmission • Electrical vehicle (EV), hybrid electrical vehicle (HEV), and inverter • Advanced driver assistance systems +Battery (KL30) VDD 33907/33908 BOOTS_CORE SW_CORE VPRE GATE_LS SW_PRE2 BOOTS_PRE SW_PRE1 VSUP2 VSUP1 VSUP3 VSENSE COMP_CORE VCCA_E VCCA_B VAUX_E VCCA VAUX_B VDDIO VAUX VAUX SELECT VCCA AD ref. voltage VCORE or VCCA MOSI MISO SCLK NCS MUX_OUT CAN-5V Ignition Key (KL15) MCU VCORE_SNS FB_CORE IO_0 INTB IO_1 SPI ADC Input NMI VDDIO IO_2 RSTB IO_3 Reset VDDIO IO_4 IO_5 FS0B VPRE CANH CAN BUS DEBUG CANL DEBUG mode VSUP3 LIN BUS TXDL LIN GNDA GND_COM VDD DGND TXD RXD RXDL LIN CAN Figure 1. 33907/33908 Simplified Application Diagram - Buck Boost Configuration * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2014-2015. All rights reserved. FCCU +Battery (KL30) VDD 33907/33908 BOOTS_CORE SW_CORE VPRE GSTE_LS BOOTS_RPE SW_PRE2 Sw_PRE1 VSUP2 VSUP1 VSUP3 VSENSE VPRE VPRE COMP_CORE VCCA_E VAUX_E VCCA_B VAUX_B VCCA VDDIO VAUX SELECT VCCA AD ref. voltage VCORE or VCCA MOSI MISO SCLK NCS MUX_OUT CAN-5V Ignition Key (KL15) MCU VCORE_SNS FB_CORE IO_0 INTB IO_1 SPI ADC Input NMI VDDIO IO_2 RSTB IO_3 Reset VDDIO IO_4 IO_5 FS0B VPRE CANH CAN BUS DEBUG CANL DEBUG mode VSUP3 LIN BUS VDD TXDL LIN GNDA GND_COM DGND TXD RXD RXDL LIN CAN FCCU Figure 2. Simplified Application Diagram - Buck Configuration, VAUX not used, VCCA = 100 mA 33907/33908 2 Analog Integrated Circuit Device Data Freescale Semiconductor 1 Orderable Parts Table 1. Orderable Part Variations Part Number Temperature (TA) Package CAN MC33907NAE MC33908NAE MC33907LAE -40 to 125 °C 48-pin LQFP exposed pad MC33908LAE 1 LIN Vcore 0 0.8 A 0 1.5 A 1 0.8 A 1 1.5 A Notes (1) Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 3 2 Internal Block Diagram COMP_CORE BOOTS_CORE FB_CORE VCORE_SNS SW_CORE DGND VPRE GATE_LS BOOTS_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 VPRE VSUP3 TSD TSD VPRE SMPS VCORE SMPS TSD VAUX_E VAUX_B VAUX VPRE VPRE TSD VAUX Linear Regulator VPRE VCAN TSD Internal Linear Regulator CAN-5V VCCA_E VCCA_B VCCA VCCA Linear Regulator VSUP3 VPRE VSENSE VPRE Analog Reference #1 Charge Pump VREF (2.5 V) GNDA MUX Interface IO_0 SELECT Die Temp MUX_OUT IO_1 Select IO_0 IO_1 IO_2 6 I/Os Interface IO_3 V2p5 Logic Main OSC Main Power Management State Machine IO_4 IO_5 CAN-5V VPRE VAUX Voltage Regulator SUPERVISOR (Over & undervoltage) VSUP1&2 CAN diag VSENSE Debug INTB MOSI MISO SCLK NCS SPI Main VDDIO VCCA FB_CORE DEBUG MISO FS V2p5Logic FS 5 Analog Reference #2 FS VPRE SPI FS FAIL SAFE Machine VDDIO RSTB FS0B OSC FS VSUP3 VSENSE CAN-5V CANH VDDIO Debug Select HSCAN Interface CANL VSENSE RXD TXD GND_COM LIN Interface LIN RXDL TXDL Fail Safe Logic & supply Figure 3. 33907L/33908L with CAN and LIN Simplified Internal Block Diagram 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 4 COMP_CORE BOOTS_CORE FB_CORE VCORE_SNS SW_CORE DGND VPRE GATE_LS BOOTS_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 VPRE VSUP3 TSD TSD VPRE SMPS VCORE SMPS TSD VAUX_E VAUX_B VAUX VPRE VPRE TSD VAUX Linear Regulator VPRE VCAN TSD Internal Linear Regulator CAN-5V VCCA_E VCCA_B VCCA VCCA Linear Regulator VSUP3 VSENSE VPRE VPRE Analog Reference #1 Charge Pump VREF (2.5 V) GNDA MUX Interface IO_0 SELECT Die Temp MUX_OUT IO_1 Select IO_0 IO_1 IO_2 I/Os Interface IO_3 6 V2p5 Logic Main OSC Main Power Management State Machine IO_4 IO_5 CAN-5V VPRE VAUX Voltage Regulator SUPERVISOR (Over & undervoltage) VSUP1&2 CAN diag VSENSE Debug INTB MOSI MISO SCLK NCS SPI Main VDDIO VCCA FB_CORE DEBUG MISO FS V2p5Logic FS 5 Analog Reference #2 FS VPRE SPI FS FAIL SAFE Machine VDDIO RSTB FS0B OSC FS VSUP3 VSENSE CAN-5V CANH VDDIO Debug Select HSCAN Interface CANL VSENSE RXD TXD GND_COM Fail Safe Logic & supply Figure 4. 33907N/33908N with CAN Only Simplified Internal Block Diagram 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 5 3 VPRE VAUX VAUX_B VAUX_E VCCA_E VCCA_B VCCA GATE_LS DGND BOOT_PRE SW_PRE2 Pinout Diagram for 33907/33908 SW_PRE1 3.1 Pin connections Transparent top view VSUP1 BOOT_CORE VSUP2 SW_CORE VSENSE VCORE_SNS VSUP3 COMP_CORE FB_CORE LIN GND_COM SELECT CAN_5V VDDIO RSTB RXDL TXDL RXD TXD IO_3 IO_2 MISO MUX_OUT MOSI IO_0 AGND SCLK IO_5 DEBUG NCS IO_4 IO_1 INTB CANL FS0B CANH VPRE VAUX VAUX_B VAUX_E VCCA_E VCCA_B VCCA GATE_LS DGND BOOT_PRE SW_PRE2 SW_PRE1 Figure 5. 33907L/33908L Pinout with CAN and LIN Transparent top view VSUP1 BOOT_CORE VSUP2 SW_CORE VSENSE VCORE_SNS VSUP3 COMP_CORE NC FB_CORE GND_COM SELECT CAN_5V VDDIO RSTB NC NC RXD TXD IO_3 IO_2 MISO MUX_OUT MOSI IO_0 AGND SCLK IO_5 DEBUG NCS IO_4 IO_1 INTB CANL FS0B CANH Figure 6. 33907N/33908N Pinout with CAN Only 33907/33908 6 Analog Integrated Circuit Device Data Freescale Semiconductor 3.2 Pin Definitions A functional description of each pin can be found in the functional pin description section beginning on page 26. Table 2. 33907/33908 Pin Definition 33907L/ 33908L Pin Number 33907N/ 33908N Pin Number Pin Name Type 1 1 VSUP1 A_IN Power supply of the device. An external reverse battery protection diode in series is mandatory 2 2 VSUP2 A_IN Second power supply. Protected by the external reverse battery protection diode used for VSUP1. VSUP1 and VSUP2 must be connected together externally. 3 3 VSENSE A_IN Sensing of the battery voltage. Must be connected prior to the reverse battery protection diode. 4 4 VSUP3 A_IN Third power supply dedicated to the device supply. Protected by the external reverse battery protection diode used for VSUP1. Must be connected between the reverse protection diode and the input PI filter. 5 NC LIN A_IN/OUT LIN single-wire bus transmitter and receiver. NC: pin must be left open for 33907N/33908N version 6 6 GND_COM GND 7 7 CAN_5V A_OUT 8 8 CANH A_IN/OUT HSCAN output High 9 9 CANL A_IN/OUT HSCAN output Low 10 11 10 11 IO_4:5 Definition Dedicated ground for CAN Output voltage for the embedded CAN interface D_IN A_OUT Can be used as digital input (load dump proof) with wake-up capability or as an output gate driver Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes. Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition Output gate driver: Can drive a logic level low-side NMOS transistor. Controlled by the SPI. 12 13 12 13 IO_0:1 A_IN D_IN Can be used as analog or digital input (load dump proof) with wake-up capability (selectable) Analog input: Pin status can be read through the MUX output pin Digital input: Pin status can be read through the SPI. Can be used to monitor error signals from another IC for safety purposes Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition Rk: For safety purposes, IO_1 can also be used to monitor the middle point of a redundant resistor bridge connected on Vcore (in parallel to the one used to set the Vcore voltage). 14 14 FS0B D_OUT Output of the safety block (active low). The pin is asserted low at start-up and when a fault condition is detected. Open drain structure. 15 15 DEBUG D_IN 16 16 AGND 17 17 MUX_OUT Debug mode entry input GROUND Analog ground connection A_OUT Multiplexed output to be connected to an MCU ADC input. Selection of the analog parameter is available at MUX-OUT through the SPI. 18 19 18 19 IO_2:3 D_IN Digital input pin with wake-up capability (logic level compatible) Digital INPUT: Pin status can be read through the SPI. Can be used to monitor error signals from MCU for safety purposes. Wake-up capability: Can be selectable to wake-up on a rising or falling edge, or on a transition. 20 20 TXD D_IN Transceiver input from the MCU which controls the state of the HSCAN bus. Internal pull-up to VDDIO. Internal pull-up to VDDIO. 21 21 RXD D_OUT 22 NC TXDL D_IN Receiver output which reports the state of the HSCAN bus to the MCU Transceiver input from the MCU which controls the state of the LIN bus. Internal pull-up to VDDIO. NC: pin must be left open for 33907N/33908N version 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Table 2. 33907/33908 Pin Definition 33907L/ 33908L Pin Number 33907N/ 33908N Pin Number Pin Name Type Definition 23 NC RXDL D_OUT Receiver output which reports the state of the LIN bus to the MCU. NC: pin must be left open for 33907N/33908N version 24 24 RSTB D_OUT This output is asserted low when the safety block reports a failure. The main function is to reset the MCU. Reset input voltage is also monitored in order to detect external reset and fault condition. Open drain structure. 25 25 MISO D_OUT SPI bus. Master Input Slave Output 26 26 MOSI D_IN SPI bus. Master Output Slave Input 27 27 SCLK D_IN SPI Bus. Serial clock 28 28 NCS D_IN No Chip Select (Active low) 29 29 INTB D_OUT 30 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os. 31 31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages 32 32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier. 33 33 COMP_CORE A_IN Compensation network. Output of the error amplifier. 34 34 VCORE_SNS A_IN VCORE output voltage sense 35 35 SW_CORE A_IN VCORE switching point 36 36 37 37 VPRE A_OUT VPRE output voltage 38 38 VAUX A_OUT VAUX output voltage. External PNP ballast transistor. Collector connection 39 39 VAUX_B A_OUT VAUX voltage regulator. External PNP ballast transistor. Base connection 40 40 VAUX_E A_OUT VAUX voltage regulator. External PNP ballast transistor. Emitter connection 41 41 VCCA_E A_OUT VCCA voltage regulator. External PNP ballast transistor. Emitter connection 42 42 VCCA_B A_OUT VCCA voltage regulator. External PNP ballast transistor. Base connection 43 43 VCCA A_OUT VCCA output voltage. External PNP ballast transistor. Collector connection 44 44 GATE_LS A_OUT Low-side MOSFET gate drive for “Non-inverting Buck-boost” configuration 45 45 DGND 46 46 BOOT_PRE 47 47 SW_PRE2 A_IN Second pre-regulator switching point 48 48 SW_PRE1 A_IN First pre-regulator switching point This output pin generates a low pulse when an Interrupt condition occurs. Pulse duration is configurable. Internal pull-up to VDDIO. BOOT_CORE A_IN/OUT Bootstrap capacitor for VCORE internal NMOS gate drive GROUND Digital ground connection A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive 33907/33908 8 Analog Integrated Circuit Device Data Freescale Semiconductor 4 General Product Characteristics 4.1 Maximum Ratings Table 3. Maximum Ratings All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Ratings Value Unit Notes (2) ELECTRICAL RATINGS VSUP1/2/3 DC Voltage at Power Supply Pins -1.0 to 40 V VSENSE DC Voltage at Battery Sense Pin -14 to 40 V VSW1,2 DC Voltage at SW_PRE1 and SW_PRE2 Pins -1.0 to 40 V DC Voltage at VPRE Pin -0.3 to 8 V DC Voltage at Gate_LS pin -0.3 to 8 V VBOOT_PRE DC Voltage at BOOT_PRE pin -1.0 to 50 V VSW_CORE DC Voltage at SW_CORE pin -1.0 to 8.0 V VCORE_SNS DC Voltage at VCORE_SNS pin 0.0 to 8.0 V VBOOT_CORE DC Voltage at BOOT_CORE pin 0.0 to 15 V DC Voltage at FB_CORE pin -0.3 to 2.5 V DC Voltage at COMP_CORE pin -0.3 to 2.5 V DC Voltage at VAUX_E, VAUX_B pin -0.3 to 40 V DC Voltage at VAUX pin -2.0 to 40 V DC Voltage at VCCA_B, VCCA_E pin -0.3 to 8.0 V VCCA DC Voltage at VCCA pin -0.3 to 8.0 V VDDIO DC Voltage at VDDIO -0.3 to 8.0 V VFS0 DC Voltage at FS0B (with ext R mandatory) -0.3 to 40 V DC Voltage at DEBUG -0.3 to 40 V DC Voltage at IO_0:1; 4:5 (with ext R = 5.1 k in series mandatory) -0.3 to 40 V -0.3 to VDDIO+0.3 V DC Voltage at SELECT -0.3 to 8.0 V VBUS_CAN DC Voltage on CANL, CANH -27 to 40 V VBUS_LIN DC Voltage on LIN -18 to 40V V VCAN_5V DC Voltage on CAN_5 V -0.3 to 8.0 V IOs Maximum Current Capability(IO_0, IO_1, IO_4, IO_5) -5.0 to 5.0 mA VPRE VGATE_LS VFB_CORE VCOMP_CORE VAUX_E,B VAUX VCCA_B,E VDEBUG VIO_0,1,4,5 VDIG VSELECT I_IO0, 1, 4, 5 DC Voltage at INTB, RSTB, MISO, MOSI, NCS, SCLK, MUX_OUT, RXD, TXD, RXDL, TXDL, IO_2, IO_3 Notes 2. All Vsups (VSUP1/2/3) shall be connected to the same supply (Figure 58) 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 9 Table 3. Maximum Ratings (continued) All voltages are with respect to ground, unless otherwise specified. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol VESD-HBM1 VESD-HBM2 VESD-HBM3 VESD-HBM4 VESD-CDM1 VESD-CDM2 VESD-GUN1 VESD-GUN2 VESD-GUN3 VESD-GUN4 VESD-GUN5 VESD-GUN6 VESD-GUN7 VESD-GUN8 VESD-GUN9 VESD-GUN10 VESD-GUN11 VESD-GUN12 Ratings ESD Voltage Human Body Model (JESD22/A114) - 100 pF, 1.5 k • All pins • VSUP1,VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5,FS0B, DEBUG • CANH, CANL • LIN Charge Device Model (JESD22/C101): • All Pins • Corner Pins System level ESD (Gun Test) • VSUP1, VSUP2, VSUP3, VSENSE, VAUX, IO_0:1, IO_4:5, FS0B 330 / 150 pF Unpowered According to IEC61000-4-2: 330 / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 k / 150 pF Unpowered According to ISO10605.2008 2.0 k / 330 pF Powered According to ISO10605.2008 • CANH, CANL 330 / 150 pF Unpowered According to IEC61000-4-2: 330 / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 k / 150 pF Unpowered According to ISO10605.2008 2.0 k / 330 pF Powered According to ISO10605.2008 • LIN 330 / 150 pF Unpowered According to IEC61000-4-2: 330 / 150 pF Unpowered According to OEM LIN, CAN, FLexray Conformance 2.0 k / 150 pF Unpowered According to ISO10605.2008 2.0 k / 330 pF Powered According to ISO10605.2008 Value Unit ±2.0 ±4.0 ±6.0 ±8.0 kV kV kV kV ±500 ±750 V V ±8.0 ±8.0 ±8.0 ±8.0 kV kV kV kV ±15.0 ±12.0 ±15.0 ±15.0 kV kV kV kV ±15.0 ±15.0 ±12.0 ±15.0 kV kV kV kV Notes (3) THERMAL RATINGS TA Ambient Temperature -40 to 125 °C TJ Junction Temperature -40 to 150 °C TSTG Storage Temperature -55 to 150 °C 30 °C/W (4) Thermal Resistance Junction to Case Top 24.2 °C/W (5) Thermal Resistance Junction to Case Bottom 0.9 °C/W (6) THERMAL RESISTANCE RJA RJCTOP RJCBOTTOM Notes 3. 4. 5. 6. Thermal Resistance Junction to Ambient Compared to AGND. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). Thermal resistance between the die and the solder par on the bottom of the packaged based on simulation without any interface resistance. 33907/33908 10 Analog Integrated Circuit Device Data Freescale Semiconductor 4.2 Static Electrical Characteristics Table 4. Operating Range TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit 2.0 – 13.0 mA Power Supply Current for VSUP3 in Normal Mode (VSUP > VSUP_UV_7) – 3.5 5.0 mA ISUP_LPOFF1 Power Supply Current in LPOFF (VSUP = 14 V at TA = 25 °C) – 32 – µA ISUP_LPOFF2 Power Supply Current in LPOFF (VSUP = 18 V at TA = 80 °C) – 42 60 µA Power Supply Undervoltage Warning – 8.5 – V Notes POWER SUPPLY ISUP123 ISUP3 VSNS_UV Power Supply Current in Normal Mode (VSUP > VSUP_UV_7) VSNS_UV_HYST Power Supply Undervoltage Warning Hysteresis 0.1 – – V VSUP_UV_7 Power Supply Undervoltage Lockout (power-up) 7.0 – 8.0 V VSUP_UV_5 Power Supply Undervoltage Lockout (power-up) – – 5.6 V VSUP_UV_L Power Supply Undervoltage Lockout (falling - Boost config.) – – 2.7 V VSUP_UV_L_B Power Supply Undervoltage Lockout (falling - Buck config.) – – 4.6 V (7) Power Supply Undervoltage Lockout Hysteresis – 0.1 – V (8) 6.25 VPRE_UV_4 – VSUP - 6.75 – P3 RDSON_PR E * IPRE 6.0 – 7.0 2.0 0.5 2.0 1.0 0.3 – 2.0 – – – – – – – – 0.05 2.0 1.0 0.3 – – – – – – – – VSUP_UV_HYST VPRE VOLTAGE PRE-REGULATOR VPRE VPRE Output Voltage • Buck mode (VSUP > VSUP_UV_7) • Buck mode (VSUP_UV_7 VSUP 4.6 V) • Boost mode (VSUP 2.7 V) IPRE VPRE Maximum Output Current Capability • Buck or Boost with VSUP > VSUP_UV_7 • Buck with VSUP_UV_7 VSUP 4.6 V • Boost with VSUP_UV_7 VSUP 6.0 V • Boost with 6.0 V VSUP 4.0 V • Boost with 4.0 V VSUP 2.7 V IPRE_LPOFF VPRE Maximum Output Current Capability in LPOFF at low VSUP voltage • Buck with VSUP_UV_7 VSUP 4.6 V • Boost with VSUP_UV_7 VSUP 6.0 V • Boost with 6.0 V VSUP 4.0 V • Boost with 4.0 V VSUP 2.7 V V A (8) A (8) IPRE_LIM VPRE Output Current Limitation with VSUP 28 V 3.5 – – A IPRE_OC VPRE Overcurrent Detection Threshold (in buck mode only) with VSUP 28 V 5.0 – – A VPRE_UV VPRE Undervoltage Detection Threshold (Falling) 5.5 – 6.0 V Notes 7. VSUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE * IPRE 8. Guaranteed by design 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 11 Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes VPRE Undervoltage Hysteresis 0.05 – 0.15 V (9) VPRE Shut-off Threshold (Falling - buck and buck/boost) 4.2 – 4.5 V VPRE Shut-off Hysteresis 0.05 – 0.15 V VPRE Pass Transistor On Resistance with VSUP 28 V – – 200 m VPRE Line Regulation – 20 – mV (9) LORVPRE_BUCK VPRE Load Regulation for COUT = 57 µF • IPRE from 50 mA to 2.0 A - Buck mode – 100 – mV (9) LORVPRE_BOOST VPRE Load Regulation for COUT = 57 µF • IPRE from 50 mA to 2.0 A - Boost mode – 500 – mV (9) VPRE_LL_H VPRE_LL_L VPRE Pulse Skipping Thresholds – – 200 180 – – mV TWARN_PRE VPRE Thermal Warning Threshold – 125 – °C VPRE VOLTAGE PRE-REGULATOR (CONTINUED) VPRE_UV_HYST VPRE_UV_4P3 VPRE_UV_4P3_ HYST RDSON_PRE LIR_VPRE TSD_PRE VPRE Thermal Shutdown Threshold 160 – – °C TSD_PRE_HYST VPRE Thermal Shutdown Hysteresis – 10 – °C VSUP_IPFF IPFF Input Voltage Detection 18 – 24 V VSUP_IPFF_HYST IPFF Input Voltage Hysteresis 0.2 – – V IPFF High-side Peak Current Detection with VSUP 28 V 1.7 – – A VPRE-1 – VPRE V – – 0.5 V 0.784 0.8 0.816 V – – – – – – – – 0.8 1.5 0.8 1.5 1 1.8 1 1.8 – – – – 2 3.5 2 3.5 – – 200 IPRE_IPFF_PK VG_LS_OH LS Gate Driver High Output Voltage (IOUT = 50 mA) VG_LS_OL LS Gate driver Low Level (IOUT = 50 mA) (9) (9) VCORE VOLTAGE REGULATOR VCORE_FB ICORE ICORE_LIM RDSON_CORE VCORE Feedback Input Voltage VCORE Output Current Capability in Normal Mode • 33907N • 33908N • 33907L • 33908L VCORE Output Current Limitation • 33907N • 33908N • 33907L • 33908L VCORE Pass Transistor On Resistance A A m Notes 9. Guaranteed by design 33907/33908 12 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes VCORE VOLTAGE REGULATOR (CONTINUED) LORVCORE_1.2 VCORE Transient Load regulation - 1.2 V range -60 – 60 mV (10), (11) LORVCORE_3.3 VCORE Transient Load regulation - 3.3 V range -100 – 100 mV (10) (11) VCORE_LL_H VCORE_LL_L VCORE Pulse Skipping Thresholds – – 180 160 – – mV TWARN_CORE VCORE Thermal Warning Threshold – 125 – °C , TSD_CORE VCORE Thermal Shutdown Threshold 160 – – °C TSD_CORE_HYST VCORE Thermal Shutdown Hysteresis – 10 – °C (10) 4.95 4.9 4.85 3.2505 3.234 3.201 5.0 5.0 5.0 3.3 3.3 3.3 5.05 5.1 5.15 3.3495 3.366 3.399 V (12) VCCA VOLTAGE REGULATOR VCCA VCCA Output Voltage • 5.0 V config. with Internal ballast at 100 mA • 5.0 V config with external ballast at 200 mA • 5.0 V config with external ballast at 300 mA • 3.3 V config with Internal ballast at 100 mA • 3.3 V config with external ballast at 200 mA • 3.3 V config with external ballast at 300 mA ICCA_IN VCCA Output Current (int. MOSFET) – – 100 mA ICCA_OUT VCCA Output Current (external PNP) – – 300 mA ICCA_LIM_INT VCCA Output Current Limitation (int. MOSFET) 100 – 675 mA ICCA_LIM_OUT VCCA Output Current Limitation (external PNP) 300 – 675 mA ICCA_LIM_FB VCCA Output Current Limitation Foldback 80 – 200 mA VCCA_LIM_FB VCCA Output Voltage Foldback Threshold 0.5 – 1.1 V VCCA_LIM_HYST VCCA Output Voltage Foldback Hysteresis 0.03 – 0.3 V VCCA Base Current Capability – 20 – – 30 – mA VCCA Thermal Warning Threshold (int. MOSFET only) – 125 – °C 160 – – °C VCCA Thermal Shutdown Hysteresis – 10 – °C (13) VCCA Transient Load Regulation • ICCA = 10 mA to 100 mA (internal MOSFET) • ICCA = 10 mA to 300 mA (external ballast) – – 1.0 % (13) ICCA_BASE_SC ICCA_BASE_SK TWARN_CCA TSDCCA TSDCCA_HYST LORTVCCA VCCA Thermal Shutdown Threshold (int. MOSFET only) Notes 10. Guaranteed by design. 11. COUT = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt 2.0 A/µs 12. 13. External PNP gain within 150 to 450 Guaranteed by design. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 13 Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes VAUX VOLTAGE REGULATOR VAUX_5 VAUX Output Voltage (5.0 V configuration) 4.85 5.0 5.15 V VAUX_33 VAUX Output Voltage (3.3 V configuration) 3.2 3.3 3.4 V VAUX_TRK VAUX Tracking Error (VAUX_5 and VAUX_33) -15 – +15 mV IAUX_OUT VAUX Output Current – – 300 mA IAUX_LIM VAUX Output Current Limitation 300 – 700 mA IAUX_LIM_FB VAUX Output Current Limitation Foldback 100 – 530 mA VAUX_LIM_FB VAUX Output Voltage Foldback Threshold 0.5 – 1.1 V VAUX_LIM_HYST VAUX Output Voltage Foldback Hysteresis 0.03 – 0.3 V VAUX Base Current Capability – 7.0 – – -7.0 – mA TSDAUX VAUX Thermal Shutdown Threshold 160 – – °C TSDAUX_HYST VAUX Thermal Shutdown Hysteresis – 10 – °C (14) VAUX Static Load Regulation (IAUX_OUT = 10 mA to 300 mA) – 15 – mV (14) VAUX Transient Load Regulation • IAUX_OUT = 10 mA to 300 mA – – 1.0 % (14) 4.8 5.0 5.2 V – – 100 mA IAUX_BASE_SC IAUX_BASE_SK LORVAUX LORTVAUX CAN_5V VOLTAGE REGULATOR VCAN VCAN Output Voltage VSUP > 6.0 V in Buck mode VSUP > VSUP_UV_L in Boost mode ICAN_OUT VCAN Output Current ICAN_LIM VCAN Output Current Limitation 100 – 250 mA TSDCAN VCAN Thermal Shutdown Threshold 160 – – °C TSDCAN_HYST VCAN Thermal Shutdown Hysteresis – 10 – °C VCAN Undervoltage Detection Threshold 4.25 – 4.8 V VCAN Undervoltage Hysteresis 0.07 – 0.22 V VCAN Overvoltage Detection Threshold 5.2 – 5.55 V VCAN Overvoltage Hysteresis 0.07 – 0.22 V – 100 – mV VCAN_UV VCAN_UV_HYST VCAN_OV VCAN_OV_HYST LORVCAN VCAN Load Regulation (from 0 to 50 mA) (14) (14) Notes 14. Guaranteed by design. 33907/33908 14 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit 7.2 – 8.0 V – 0.1 – V Notes FAIL-SAFE MACHINE VOLTAGE SUPERVISOR VPRE_OV VPRE Overvoltage Detection Threshold VPRE_OV_HYST VPRE Overvoltage Hysteresis VCORE_FB_UV VCORE FB Undervoltage Detection Threshold 0.67 – 0.773 V VCORE FB Undervoltage Detection Threshold - Degraded mode 0.45 – 0.58 V 10 – 27 mV 0.84 – 0.905 V VCORE FB Overvoltage Hysteresis 10 – 30 mV VCORE_FB Drift versus IO_1 50 100 150 mV VCORE Internal Pull-down Current (active when VCOR E is enabled) 5.0 12 25 mA VCCA_UV_5 VCCA Undervoltage Detection Threshold (5.0 V config) 4.5 – 4.75 V VCCA_UV_5D VCCA Undervoltage Detection Threshold (Degraded 5.0 V) 3.0 – 3.2 V VCCA_UV_33 VCCA Undervoltage Detection Threshold (3.3 V config) 3.0 – 3.2 V – 0.07 – V VCORE_FB_UV_D VCORE_FB_UV_ HYST VCORE_FB_OV VCORE_FB_OV_HYS T VCORE_FB_DRIFT IPD_CORE VCCA_UV_HYST VCORE FB Undervoltage Hysteresis VCORE FB Overvoltage Detection Threshold VCCA Undervoltage Hysteresis VCCA_OV_5 VCCA Overvoltage Detection Threshold (5.0 V config) 5.25 – 5.5 V VCCA_OV_33 VCCA Overvoltage Detection Threshold (3.3 V config) 3.4 – 3.6 V VCCA Overvoltage Hysteresis – 0.15 – V VCCA Internal Pull-down Resistor (active when VCCA is disabled) 50 – 160 VAUX_UV_5 VAUX Undervoltage Detection Threshold (5.0 V config) 4.5 – 4.75 V VAUX_UV_5D VAUX Undervoltage Detection Threshold (Degraded 5.0 V) 3.0 – 3.2 V VAUX_UV_33 VAUX Undervoltage Detection Threshold (3.3 V config) 3.0 – 3.2 V – 0.07 – V VCCA_OV_HYST RPD_CCA VAUX_UV_HYST VAUX Undervoltage Hysteresis VAUX_OV_5 VAUX Overvoltage Detection Threshold (5.0 V config) 5.25 – 5.5 V VAUX_OV_33 VAUX Overvoltage Detection Threshold (3.3 V config) 3.4 – 3.6 V VAUX Overvoltage Hysteresis – 0.07 – V VAUX Internal Pull-down Resistor (active when VAUX is disabled) 50 – 170 VAUX_OV_HYST RPD_AUX (15) (15) (15) (15) (15) (15) (15) Notes 15. Guaranteed by design. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes VRSTB_OL Reset Low Output Level (I_RSTB = 2.0 mA and 2.0 V < VSUP < 40 V) – – 0.5 V (16) IRSTB_LIM Reset Output Current Limitation 12 – 25 mA VRSTB_IL External Reset Detection Threshold (falling) 1.0 – – V VRSTB_IH External Reset Detection Threshold (rising) – – 2.0 V 0.2 – – V FAIL-SAFE OUTPUTS VRSTB_IN_HYST External Reset Input Hysteresis VFS0B_OL FS0B Low Output Level (I_FS0b = 2.0 mA) – – 0.5 V IFS0B_LK FS0B Input Current Leakage (VFS0B = 28 V) – – 1.0 µA IFS0B_LIM FS0B Output Current Limitation 6.0 – 12 mA ANALOG INPUT - MULTI-PURPOSE IOS VIO_ANA_WD Measurable Input Voltage (wide range) 3.0 – 19 V VIO_ANA_TG Measurable Input Voltage (tight range) 3.0 – 9.0 V – – 100 µA Digital High Input voltage level (IO_0:1, IO_4:5) • Min Limit = 2.7 V at VSUP = 40 V 2.6 – – V Digital High Input voltage level (IO_2, IO_3) 2.0 – – V Digital Low Input voltage Level (IO_0:1; IO_4:5) – – 2.1 V VIO_HYST Input Voltage Hysteresis (IO_0:1, IO_4:5) 50 120 500 mV VIO23_IL Digital Low Input voltage Level (IO_2, IO_3) – – 0.9 V Input Voltage Hysteresis (IO_2, IO_3) 200 450 700 mV Input Current for IO_0:1 -5.0 – 100 µA Input Current for IO_1 when used for FB_Core monitoring -1.0 – 1.0 µA Input Current for IO_2:5 -5.0 – 5.0 µA Input Current for IO_0:5 in LPOFF -1.0 – 1.0 µA IIO_IN_ANA Input Current DIGITAL INPUT VIO_IH VIO23_IH VIO_IL VIO23_HYST IIO_IN_0:1 IIO_IN_1 IIO_IN_2:5 IIO_IN_LPOFF (17) (17) OUTPUT GATE DRIVER VIO_OH High Output Level at IIO_OUT = -2.5 mA VPRE - 1.5 – VPRE V VIO_OL Low Output Level at IIO_OUT = +2.5 mA 0.0 – 1.0 V Output Current Capability 2.5 – – – – -2.5 mA VIO_OUT_SK VIO_OUT_SC Notes 16. For VSUP < 2.0 V, all supplies are already off and external pull-up on RSTB (e.g VCORE or VCCA) pulls the line down. 17. Guaranteed by design. 33907/33908 16 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes -5.0 – 5.0 % (18) ANALOG MULTIPLEXER VAMUX_ACC Voltage Sense Accuracy (VSNS, IO_0, IO_1) using 5.1 kresistor VAMUX_WD_5 Divider Ratio (wide input voltage range) at VDDIO = 5.0 V – 5.0 – VAMUX_WD_3P3 Divider Ratio (wide input voltage range) at VDDIO = 3.3 V – 7.0 – VAMUX_TG_5 Divider Ratio (tight input voltage range) at VDDIO = 5.0 V – 2.0 – VAMUX_TG_3P3 Divider Ratio (tight input voltage range) at VDDIO = 3.3 V – 3.0 – VAMUX_REF1 Internal Voltage Reference with 6.0 V < VSUP < 19 V 2.475 2.5 2.525 V VAMUX_REF2 Internal Voltage Reference with VSUP 6.0 V or VSUP 19 V 2.468 2.5 2.532 V – 9.9 – mV/°C 2.08 2.15 2.22 V VAMUX_TP_CO VAMUX_TP Internal Temperature sensor coefficient Temperature Sensor MUX_OUT output voltage (at TJ=165°C) (19) INTERRUPT VINTB_OL Low Output Level (IINT = 2.5 mA) – – 0.5 V RPU_INT Internal Pull-up Resistor (connected to VDDIO) – 10 – K IINT_LK Input Leakage Current – – 1 µA CAN TRANSCEIVER CAN LOGIC INPUT PIN (TXD) VTXD_IH TXD High Input Threshold 0.7 x VDDIO – – V VTXD_IL TXD Low Input Threshold – – 0.3 x VDDIO V TXDPULL-UP TXD Main Device Pull-up 20 33 50 K -1.0 – 1.0 µA TXDLK TXD Input Leakage Current, VTXD = VDDIO CAN LOGIC OUTPUT PIN (RXD) VRXD_OL1 Low Level Output Voltage (IRXD = 250 µA) – – 0.4 V VRXD_OL2 Low Level Output Voltage (IRXD = 1.5 mA) – – 0.9 V VOUTHIGH High Level Output Voltage (IRXD = -250 µA, VDDIO = 3.0 V to 5.5 V) VDDIO 0.4V – – V Notes 18. If a higher resistor value than recommended is used, the accuracy degrades. 19. Guaranteed by design 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 17 Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Differential Input Comparator Common Mode Range -12 – 12 V Differential Input Voltage Threshold in Sleep Mode 0.5 – 0.9 V VIN_HYST Differential Input Hysteresis (in TX, RX mode) 50 – – mV RIN_CHCL CANH, CANL Input Resistance 5.0 – 50 k RIN_DIFF CAN Differential Input Resistance 10 – 100 k Input Resistance Matching -3.0 – 3.0 % VCANH CANH Output Voltage (45 < RBUS < 65 ) • TX dominant state • TX recessive state 2.75 2.0 – 2.5 4.5 3.0 V VCANL CANL Output Voltage (45 < RBUS < 65 ) • TX dominant state • TX recessive state 0.5 2.0 – 2.5 2.25 3.0 V CAN dominant voltage symmetry (VCANL + VCANH) 4.5 5 5.5 V 1.5 -50 2.0 0.0 3.0 50 V mV Notes CAN OUTPUT PINS (CANH, CANL) VDIFF_COM_MODE VIN_DIFF_SLEEP RIN_MATCH VCAN_SYM VOH-VOL Differential Output Voltage • TX dominant state (45 < RBUS < 65 ) • TX recessive state ICANL-SK CANL Sink Current Under Short-circuit Condition (VCANL 12 V, CANL driver ON, TXD low) 40 – 100 mA ICANH-SC CANH Source Current Under Short-circuit Condition (VCANH = -2.0 V, CANH driver ON, TXD low) -100 – -40 mA RINSLEEP CANH, CANL Input Resistance Device Supplied and in CAN Sleep Mode 5.0 – 50 k VCANLP CANL, CANH Output Voltage in Sleep Modes. No termination load. -0.1 0.0 0.1 V ICAN CANH, CANL Input Current, Device Unsupplied, (VCANH, VCANL =5.0V) • VSUP and VCAN connected to GND • VSUP and VCAN connected to GND via 47k resistor -10 -10 – – 10 10 µA µA TOT Overtemperature Detection 160 – – °C THYST Overtemperature Hysteresis – – 20 °C (20) DIGITAL INTERFACE MISOH High Output Level on MISO (IMISO = 1.5 mA) VDDIO - 0.4 – – V MISOL Low Output Level on MISO (IMISO = 2.0 mA) – – 0.4 V IMISO Tri-state Leakage Current (VDDIO = 5.0 V) -5.0 – 5.0 µA VDDIO Supply Voltage for MISO Output Buffer 3.0 – 5.5 V IVDDIO Current consumption on VDDIO – 1.0 3.0 mA SPILK SCLK, NCS, MOSI Input Current -1.0 – 1.0 µA SCLK, NCS, MOSI High Input Threshold 2.0 – – V NCS, MOSI Internal Pull-up (pull-up to VDDIO) 200 400 800 K – – 0.8 V VSPI_IH RSPI VSPI_IL SCLK, NCS, MOSI Low Input Threshold 33907/33908 18 Analog Integrated Circuit Device Data Freescale Semiconductor Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes DEBUG VDEBUG_IL Low Input Voltage Threshold 2.1 2.35 2.6 V VDEBUG_IH High Input Voltage Threshold 4.35 4.6 4.97 V IDEBUG_LK Input Leakage Current -10 – 10 µA LIN TRANSCEIVER (WHEN 7.0 V < VSUP1,2,3 < 18 V, UNLESS OTHERWISE SPECIFIED) (33907L/33908L) LIN LOGIC INPUT PIN (TXDL) VTXDL_IH TXDL High Input Threshold 2.0 – – V VTXDL_IL TXDL Low Input Threshold – – 0.8 V TXDL Internal Pull-up (to VDDIO) 20 33 50 k -1.0 – 1.0 µA TXDLPULL-UP TXDLLK TXD Input Leakage Current, VTXDL = VDDIO LIN LOGIC INPUT PIN (RXDL) VRXDL_OL1 Low Level Output Voltage (IRXDL = 250 µA) – – 0.4 V VRXDL_OL2 Low Level Output Voltage (IRXDL = 1.5 mA) – – 0.9 V High Level Output Voltage (IRXDL = -250 µA, VDDIO = 3.0 V to 5.5 V) VDDIO-0.4V – – V IBUS_PAS_DOM Input Leakage Current at the Receiver. Dominant State (Driver OFF, VBAT = 12 V, VBUS = 0 V) -1.0 – – mA IBUS_PAS_REC Input Leakage Current at the Receiver. Recessive State (Driver OFF, 8.0 V < VBAT < 18 V, 8.0 V < VBUS < 18 V, VBUS VBAT) – – 20 µA VDRIVER_DOM Driver Dominant Voltage – – 0.251 VSUP V VBUS_DOM Receiver Dominant State – – 0.4 VSUP V VBUS_REC Receiver Recessive State 0.6 VSUP – – V VBUS_WU LIN Wake-up Detection Threshold (7.0 V< VSUP < 18 V) 0.4 VSUP – 0.6 VSUP V – – 7.0 V Series Diode Voltage Drop (DSER_MASTER and DSER_INT in pull-up path) 0.4 0.7 1.0 V IBUS_LIM Current Limitation for Driver Dominant State (VBUS = 18 V) 40 – 200 mA RSLAVE LIN Pull-up Resistor 20 – 60 k VSHIFT_GND Ground Shift (VSHIFT_GND = VGND_ECU - VGND_BATTERY) 0.0 – 11.5%VBAT V VSHIFT_BAT Battery Voltage Shift (VSHIFT_BAT = VBATTERY - VSHIFT_GND- VBAT) 0.0 – 11.5%VBAT V VRXDL_OUT_HIGH LIN OUTPUT PIN VLIN_UV VSER_DIODE VSUP Undervoltage Threshold (21) (22) (23) Notes 20. Guaranteed by design and characterization. 21. VBAT is the voltage at the input of the control unit. 22. 23. Current flowing inside the pin. A transceiver must be capable to sink at least 40 mA. VBAT: voltage across the battery connectors of the vehicle. VGND_ECU: voltage on the local ECU ground connector with respect to battery ground of the vehicle (VGND_BATTERY). 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Table 4. Operating Range (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes 0.0 – 8.0% VBAT V (24) 0.475 VSUP – 0.525 VSUP V (25) – – 0.175 VSUP V LIN OUTPUT PIN (CONTINUED) VSHIFT_DIF Difference Between Battery Shift and Ground Shift (VSHIFT_DIF = VSHIFT_BAT - VSHIFT_GND) VBUS_CNT VBUS_CNT = (VTH_REC + VTH_DOM)/2 VHYST VHYST = VTH_REC - VTH_DOM IBUS_NO_GND Ground Disconnection. GND = VSUP, 0 V < VBUS < 18 V, VBAT = 12 V. Loss of Local GND does not affect communication in the remaining network -1.0 – 1.0 mA IBUS_NO_BAT VBAT disconnection. VSUP = GND, 0 V < VBUS < 18 V. Node sustains the current that can flow under this condition. BUS remains operational. – – 100 µA LIN Thermal Shutdown – 180 – °C LINTSD LINTSD_HYST CLIN LIN Thermal Shutdown Hysteresis LIN internal capacitor 20 – – (26) (27) °C 10 pF (27) Notes 24. This constraint refers to duty cycle D1 and D2 only. 25. VTH_DOM: receiver threshold of the recessive to dominant LIN bus edge. VTH_REC receiver threshold of the dominant to recessive LIN bus edge. 26. VSUP is the voltage at the input of the device (different from Vbat when a reverse current protection diode is implemented. 27. Guaranteed by design. 33907/33908 20 Analog Integrated Circuit Device Data Freescale Semiconductor 4.3 Dynamic Electrical Characteristics Table 5. Dynamic Electrical Characteristics TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes DIGITAL INTERFACE TIMING fSPI SPI Operation Frequency (50% DC) 0.5 – 8.0 MHz tMISO_TRANS MISO Transition Speed, 20 - 80% • VDDIO = 5.0 V, CLOAD = 50 pF • VDDIO = 5.0 V, CLOAD = 150 pF 5.0 5.0 – – 30 50 ns tCLH Minimum Time SCLK = HIGH 62 – – ns tCLL Minimum Time SCLK = LOW 62 – – ns tPCLD Propagation Delay (SCLK to data at 10% of MISO rising edge) – – 30 ns tCSDV NCS = LOW to Data at MISO Active – – 75 ns tSCLCH SCLK Low Before NCS Low (setup time SCLK to NCS change H/L) 75 – – ns tHCLCL SCLK Change L/H after NCS = low 75 – – ns tSCLD SDI Input Setup Time (SCLK change H/L after MOSI data valid) 40 – – ns tHCLD SDI Input Hold Time (MOSI data hold after SCLK change H/L) 40 – – ns tSCLCL SCLK Low Before NCS High 100 – – ns tHCLCH SCLK High After NCS High 100 – – ns tPCHD NCS L/H to MISO at High-impedance – – 75 ns NCS Min. High Time 500 – – ns NCS Filter Time 10 – 40 ns tSCLCL tHCLCH tONNCS tNCS_MIN NCS tONNCS tSCLCH tHCLCL tCLH tCLL SCLK MISO tPCHD z tPCLD tCSDV Tri-state Not used LSB MSB tHCLD tSCLD MOSI LSB MSB Figure 7. SPI Timing Diagram 500 ns min NCS 3.5 µs min AnyFail Fail-safe Any Safe registeracces access register Any main Any Main register register access acces AnyFail Fail-safe Any Safe register acces access register Figure 8. Register Access Restriction 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes CAN DYNAMIC CHARACTERISTICS tDOUT TXD Dominant State Timeout 0.8 – 5.0 ms tDOM Bus Dominant Clamping Detection 0.8 – 5.0 ms tLOOP Propagation Loop Delay TXD to RXD • RLOAD = 120 , C between CANH and CANL = 100 pF, C at RxD < 15 pF – – 255 ns t1PWU Single Pulse Wake-up Time 0.5 – 5.0 µs t3PWU Multiple Pulse Wake-up Time 0.5 – 1.0 µs t3PTO1 Multiple Pulse Wake-up Timeout (120 µs bit selection) 110 120 – µs t3PTO2 Multiple Pulse Wake-up Timeout (360 µs bit selection) 350 360 – µs – – 100 µs tCAN_READY Delay to Enable CAN by SPI Command (NCS rising edge) to CAN to Transmit (device in normal mode and CAN interface in TX/RX mode) (28) FAIL-SAFE STATE MACHINE OSCFSSM Oscillator 405 – 495 kHz CLKFS_MIN Fail-safe Oscillator Monitoring 150 – – kHz tIC_ERR IO_0:5 Filter Time 4.0 – 20 µs tACK_FS Acknowledgement Counter (used for IC error handling IO_1 and IO_5) 7.0 – 9.7 ms t_DFS_RECOVERY IO_0 Filter Time to Recover from Deep Reset and Fail State 0.8 – 1.3 ms tIO1_DRIFT_MON IO_1 filter time 1.0 – 2.0 ms FAIL-SAFE OUTPUT tRSTB_FB RSTB Feedback Filter Time 8.0 – 15 µs tFSOB_FB FS0B Feedback Filter Time 8.0 – 15 µs tRSTB_BLK RSTB Feedback Blanking Time 180 – 320 µs tFSOB_BLK FS0B Feedback Blanking Time 180 – 320 µs tRSTB_POR Reset Delay Time (after a Power On Reset or from LPOFF) 12 15.9 23.6 ms tRSTB_LG Reset Duration (long pulse) 8.0 – 10 ms tRSTB_ST Reset duration (short pulse) 1.0 – 1.3 ms tRSTB_IN External Reset Delay time 8.0 – 15 µs tDIAG_SC Fail-safe Output Diagnostic Counter (FS0B) 550 – 800 µs 44 – – µF (29) VSUP VOLTAGE SUPPLY CSUP Minimum capacitor on Vsup Notes 28. For proper CAN operation, TXD must be set to high level before CAN enable by SPI, and must remain high for at least TCAN_READY. 29. This timing is not guaranteed in case of fault during startup phase (after Power On Reset of from LPOFF) 33907/33908 22 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit 418 440 462 kHz – – 30 ns VPRE Soft Start Duration (COUT 100 µF) 500 – 700 µs VPRE Current Limitation Blanking Time 200 – 600 ns tIPRE_OC VPRE Overcurrent Filtering Time 30 – 120 ns tPRE_UV VPRE Undervoltage Filtering Time 20 – 40 µs Vpre Shut-off Filtering Time 3.0 – 6.0 µs VPRE Load Regulation Variation – – 25 A/ms tPRE_WARN VPRE Thermal Warning Filtering Time 30 – 40 µs tPRE_TSD VPRE Thermal Detection Filtering Time 1.3 – – µs tVSUP_IPFF IPFF Input Voltage Filtering Time 1.0 – 5.0 µs tIPRE_IPFF IPFF High-side Peak Current Filter Time 100 – 300 ns – – 50 ns 1.0 – 3.0 µs 20 – 40 ns Notes VPRE VOLTAGE PRE-REGULATOR fSW_PRE VPRE Switching Frequency tSW_PRE VSW_PRE On and Off Switching Time tPRE_SOFT tPRE_BLK_LIM tPRE_UV_4p3 dIPRE/DT tLS_RISE/FALL LS Gate Voltage Switching Time (IOUT = 300 mA) (30) (30) (30) VSENSE VOLTAGE REGULATOR tVSNS_UV VSNS Undervoltage Filtering Time VCORE VOLTAGE REGULATOR tCORE_BLK_LIM VCORE Current Limitation Blanking Time fSW_CORE VCORE Switching Frequency 2.28 2.4 2.52 MHz tSW_CORE VSW_CORE On and Off Switching Time 6.0 – 12 ns VCORE_SOFT VCORE Soft Start (COUT = 100 µF max) – – 10 V/ms tCORE_WARN VCORE Thermal Warning Filtering Time 30 – 40 µs tCORE_TSD VCORE Thermal Detection Filtering Time 0.5 – – µs VCCA Output Current Limitation Filter Time 1.0 – 3.0 µs VCCA Output Current Limitation Duration 10 50 – – – – ms VCCA Thermal Warning Filtering Time 30 – 40 µs tCCA_TSD VCCA Thermal Detection Filter Time (int. MOSFET) 1.5 – – µs dILOAD/dt VCCA Load Transient – 2.0 – A/ms VCCA Soft Start (5.0 V and 3.3 V) – – 50 V/ms VCCA VOLTAGE REGULATOR tCCA_LIM tCCA_LIM_OFF1 tCCA_LIM_OFF2 tCCA_WARN VCCA_SOFT (30) Notes 30. Guaranteed by characterization. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit VAUX Output Current Limitation Filter Time 1.0 – 3.0 µs VAUX Output Current Limitation Duration 10 50 – – – – ms tAUX_TSD VAUX Thermal Detection Filter Time 1.5 – – µs dIAUX/dt VAUX Load Transient – 2.0 – A/ms VAUX Soft Start (5.0 V and 3.3 V) – – 50 V/ms Notes VAUX VOLTAGE REGULATOR tAUX_LIM tAUX_LIM_OFF1 tAUX_LIM_OFF2 VAUX_SOFT (31) CAN_5V VOLTAGE REGULATOR tCAN_LIM Output Current Limitation Filter Time 2.0 – 4.0 µs tCAN_TSD VCAN Thermal Detection Filter Time 1.0 – – µs tCAN_UV VCAN Undervoltage Filtering Time 4.0 – 7.0 µs tCAN_OV VCAN Overvoltage Filtering Time 100 – 200 µs dICAN/dt VCAN Load Transient – 100 – A/ms VPRE Overvoltage Filtering Time 128 – 234 µs tCORE_UV VCORE FB Undervoltage Filtering Time 4.0 – 10 µs tCORE_OV VCORE FB Overvoltage Filtering Time 128 – 234 µs tCCA_UV VCCA Undervoltage Filtering Time 4.0 – 10 µs tCCA_OV VCCA Overvoltage Filtering Time 128 – 234 µs tAUX_UV VAUX Undervoltage Filtering Time 4.0 – 10 µs tAUX_OV VAUX Overvoltage Filtering Time 128 – 234 µs 0.0 – 100 kHz SPI Selection to Data Ready to be Sampled on Mux_out • VDDIO = 5.0 V, CMUX_OUT = 1.0 nF – – 10 tINTB_LG INTB Pulse Duration (long) 90 100 – µs tINTB_ST INTB Pulse Duration (short) 20 25 – µs 60 70 80 µs (31) FAIL-SAFE MACHINE VOLTAGE SUPERVISOR tPRE_OV DIGITAL INPUT - MULTI-PURPOSE IOS FIO_IN Digital Input Frequency Range ANALOG MULTIPLEXER tMUX_READY µs INTERRUPT FUNCTIONAL SATE MACHINE tWU_GEN General Wake-up Signal Deglitch Time (for any wu signal on IOs) Notes 31. Guaranteed by characterization. 33907/33908 24 Analog Integrated Circuit Device Data Freescale Semiconductor Table 5. Dynamic Electrical Characteristics (continued) TCASE = -40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UV_L to 40 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 40 V, thermal dissipation must be considered (Figure 25). Symbol Parameter Min Typ Max Unit Notes LIN DYNAMIC CHARACTERISTICS (WHEN 7.0 V < VSUP1, 2, 3 < 18 V, UNLESS OTHERWISE SPECIFIED) (33907L/33908L) tRX_PD Receiver Propagation Delay (TRX_PD = MAX (tREC_PDR, tREC_PDF)) – – 6.0 µs -2.0 – 2.0 µs tRX_SYM Symmetry of Receiver Propagation Delay (TRX_SYM = tREC_PDF tREC_PDR) tBUS_WU BUS Wake-up Filter Time – – 250 µs tXD_DOM TXD_L Permanent Dominant State Delay – 5.0 – ms LIN Short-circuit to GND Deglitcher – 15 – ms Fast Baud Rate – – 100 KB/s D1 Duty Cycle D1 THREC(max) = 0.744 x VSUP, THDOM(max) = 0.581 x VSUP VSUP 7.0 V to 18 V, tBIT = 50 µs D1 = tBUS-rec(min)/(2tBIT) 0.396 – – % (32) D2 Duty Cycle D2 THREC(min) = 0.422 x VSUP, THDOM(min) = 0.284 x VSUP VSUP 7.6 V to 18 V, tBIT = 50 µs D2 = tBUS-rec(max)/(2tBIT) – – 0.581 % (32) D3 Duty Cycle D3 THREC(max) = 0.778 x VSUP, THDOM(max) = 0.616 x VSUP VSUP 7.0 V to 18 V, tBIT = 96 µs D3 = tBUS-rec(min)/(2tBIT) 0.417 – – % (32) D4 Duty Cycle D4 THREC(min) = 0.389 x VSUP, THDOM(min) = 0.251 x VSUP VSUP 7.6 V to 18 V, tBIT = 96 µs D4 = tBUS-rec(max)/(2tBIT) – – 0.59 % (32) tLIN_SHORT_GND BDFAST Notes 32. LIN Driver, Bus load conditions (CBUS,RBUS): 1.0 nF;1.0 k / 6.8 nF;660 / 10 nF;500 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 25 5 5.1 Functional Pin Description Introduction The 33907/33908 is the third generation of the System Basis Chip, combining: • High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN interface, external ICs such as sensors, and accurate reference voltage for A to D converters. • Built-in enhanced high-speed CAN interface (ISO11898-2 and -5), and LIN interface (LIN up to Rev. 2.2/ SAEJ2602-2), with local and bus failure diagnostic, protection, and Fail-safe operation mode. • Low-power mode, with ultra low-current consumption. • Various wake-up capabilities. • Enhanced safety features with multiple fail-safe outputs and scheme to support ASIL D applications. 5.2 Power Supplies (VSUP1, VSUP2, VSUP3) VSUP1 and VSUP2 are the inputs pins for internal supply dedicated to SMPS regulators. VSUP3 is the input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO7637 pulses. VSUP1,2, and 3 shall be connected to the same supply (Figure 58). 5.3 VSENSE Input (VSENSE) This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure the VSENSE voltage via the MUX-OUT pin. VSENSE pin is robust against ISO7637 pulses. 5.4 Pre-regulator (VPRE) A highly flexible SMPS pre-regulator is implemented in the 33907/33908. It can be configured as a “non-inverting buck-boost converter” (Figure 27) or “standard buck converter” (Figure 26), depending on the external configuration (connection of pin GATE_LS). The configuration is detected automatically during start-up sequence. The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side switching MOSFET is also integrated to make the current control easier. The pre-regulator delivers a typical output voltage of 6.5 V, which is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default. 5.5 VCORE Output (from 1.2 V to 3.3 V range) The VCORE block is an SMPS regulator. The voltage regulator is a step down DC-DC converter operating in voltage control mode. The output voltage is configurable from 1.2 V to 3.3 V range thanks to an external resistor divider connected between VCORE and the feedback pin (FB_CORE) (as example in Figure 1, Figure 2, and Figure 58). The stability of the converter is done externally, by using the COMP_CORE pin. Current limitation, overvoltage, and undervoltage detectors are provided. VCORE can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCORE by SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCORE overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled by default. 33907/33908 26 Analog Integrated Circuit Device Data Freescale Semiconductor 5.6 VCCA Output, 5.0 V or 3.3 V Selectable The VCCA voltage regulator is used to provide an accurate voltage output (5.0 V, 3.3 V) selectable through an external resistor connected to the SELECT pin. The VCCA output voltage regulator can be configured using an internal transistor delivering very good accuracy (1.0% for 5.0 V configuration and 1.5% for 3.3 V configuration), with a limited current capability (100 mA) for an analog to digital converter, or with an external PNP transistor, giving higher current capability (up to 300 mA) with lower output voltage accuracy (3.0% for 300 mA) when using a local ECU supply. Current limitation, overvoltage, and undervoltage detectors are provided. VCCA can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VCCA by SPI when VCCA is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VCCA overcurrent (with the use of external PNP only) and overvoltage information disables VCCA. Diagnostics are reported in the dedicated register and generate an Interrupt. VCCA is enabled by default. 5.7 VAUX Output, 5.0 V or 3.3 V Selectable The VAUX pin provides an auxiliary output voltage (5.0 V, 3.3 V) selectable through an external resistor connected to SELECT pin. It uses an external PNP ballast transistor for flexibility and power dissipation constraints. The VAUX output voltage regulator can be used as “auxiliary supply” (local ECU supply) or “sensor supply” (external ECU supply) with the possibility to be configured as a tracking regulator following VCCA. Current limitation, overvoltage, and undervoltage detectors are provided. VAUX can be turned ON or OFF via a SPI command, however it is not recommended to turn OFF VAUX by SPI when VAUX is configured safety critical (both overvoltage and undervoltage have an impact on RSTB and FS0B). VAUX overcurrent and overvoltage information disables VAUX, reported in the dedicated register, and generates an Interrupt. VAUX is enabled by default. 5.8 SELECT Input (VCCA, VAUX Voltage Configuration) VCCA and VAUX output voltage configurations are set by connecting an external resistor between SELECT pin and Ground. According to the value of this resistor, the voltage of VCCA and VAUX are configured after each Power On Reset, and after a wake-up event when device is in LPOFF. Information latches until the next hardware configuration read. Regulator voltage values can be read on the dedicated register via the SPI. Table 6. VCCA/VAUX Voltage Selection (Figure 59) VCCA(V) VAUX(V) R Select Recommended value 3.3 3.3 <7.0 K 5.1 K5.0% 5.0 5.0 10.8 << 13.2 K 12 K5.0% 3.3 5.0 21.6 << 26.2 K 24 K5.0% 5.0 3.3 45.9 << 56.1 K 51 K5.0% When VAUX is not used, the output VCCA voltage configuration is set using an external resistor connected between the SELECT and the VPRE pin. Table 7. VCCA Voltage Selection (VAUX not used, Figure 60, Figure 61) VCCA(V) 3.3 5.0 R Select Recommended Value <7.0 K 5.1 K5.0% 21.6 << 26.2 K 24 K5.0% 10.8 << 13.2 K 12 K5.0% 45.9 << 56.1 K 51 K5.0% 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 27 5.9 CAN_5V Voltage Regulator The CAN_5V voltage regulator is a linear regulator dedicated to the internal HSCAN interface. An external capacitor is required. Current limitation, overvoltage, and undervoltage detectors are provided. If the internal CAN transceiver is not used, the CAN_5V regulator can supply an external load (CAN_5V Voltage Regulator). CAN_5V is enabled by default. 5.10 INTERRUPT (INTB) The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set through the SPI during INIT phase. INTB has an internal pull-up resistor connected to VDDIO. 5.11 CANH, CANL, TXD, RXD These are the pins of the high speed CAN physical interface. The CAN transceivers provides the physical interface between the CAN protocol controller of an MCU and the physical dual wires CAN bus. The CAN interface is connected to the MCU via the RXD and TXD pins. 5.11.1 TXD TXD is the device input pin to control the CAN bus level. TXD is a digital input with an internal pull-up resistor connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin. In Normal mode, when TXD is high or floating, the CANH and CANL drivers are OFF, setting the bus in a recessive state. When TXD is low, the CANH and CANL drivers are activated and the bus is set to a dominant state. TXD has a built-in timing protection that disables the bus when TXD is dominant for more than TDOUT. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND. 5.11.2 RXD RXD is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin is in high-impedance state. 5.11.3 CANH and CANL These are the CAN bus pins. CANL is a low side driver to GND, and CANH is a high side driver to CAN_5V. In Normal mode and TXD high, the CANH and CANL drivers are OFF, and the voltage at CANH and CANL is approximately 2.5 V, provided by the internal bus biasing circuitry. When TXD is low, CANL is pulled to GND and CANH to CAN_5V, creating a differential voltage on the CAN bus. In LPOFF mode, the CANH and CANL drivers are OFF, and these pins are pulled down to GND via the device RIN_CHCL resistors. CANH and CANL have integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical transients. These pins have current limitation and thermal protection. 5.12 LIN, TXDL, RXDL These pins apply to 33907L and 33908L versions. These are the pins of the LIN physical interface. The LIN transceivers provides the physical interface between the MCU and the physical single wire LIN bus. The LIN interface is connected to the MCU via the RXDL and TXDL pins. 5.12.1 TXDL The TXDL input pin is the MCU interface to control the state of the LIN output. TXDL is a digital input with an internal pull-up resistor connected to VDDIO. In the application, this pin is connected to the microcontroller transmit pin. 33907/33908 28 Analog Integrated Circuit Device Data Freescale Semiconductor In Normal mode, when TXDL is high or floating, the LIN output transistor is OFF, setting the bus in recessive state. When TXDL is low, the LIN output transistor is ON and the bus is set to a dominant state. TXDL has a built-in timing protection that disables the bus when TXDL is dominant for more than TXD_DOM. In LPOFF mode, VDDIO is OFF, pulling down this pin to GND. 5.12.2 RXDL RXDL is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. In Normal mode, RXD is a push-pull structure. When the bus is in a recessive state, RXD is high. When the bus is dominant, RXD is low. In LPOFF mode, this pin is in high-impedance state. 5.12.3 LIN This is the LIN bus pin. The LIN driver is a low-side MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is integrated so no external pull-up components are required for the application in a slave node. An additional pullup resistor of 1.0 k must be added when the device is used in the master node. In Normal mode and TXDL high, the LIN transistor is OFF, and the voltage at LIN is approximately VSUP3, provided by the pull up resistor with a serial diode structure. When TXD is low, LIN is pulled to GND The device has two selectable baud rates: 20 kBits/s for Normal Baud rate and 10 kBits/s for slow baud rate. An additional fast baud rate (100 kBits/s) is implemented. It can be used to flash the MCU or in the garage for diagnostic. The LIN Consortium specification does not specify electrical parameters for this baud rate. The communication only must be guaranteed. In LPOFF mode, the LIN transistor is OFF, and this pin is pulled up to VSUP3. LIN has integrated ESD protection and extremely high robustness versus external disturbance, such as EMC and electrical transients. 5.13 Multiplexer Output MUX_OUT The MUX_OUT pin (Figure 9) delivers analog voltage to the MCU ADC input. The voltage to be delivered to MUX_OUT is selected via the SPI, from one of the following parameters: • VSENSE • VIO_0 • VIO_1 • Internal 2.5 V reference • Die temperature sensor T(°C) = (VAMUX - VAMUX_TP) / VAMUX_TP_CO + 165 Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V) 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 29 VSENSE R 1 SPI selection Mux_out R 2 R 3 R 5 R 4 3.3 V 3.3 V Ratio#1 Ratio#2 5.0 V Ratio#2 5.0 V Ratio#1 SPI selection Internal 2.5 V reference IO_0 Same as above SPI selection Die temperature sensor IO_1 Same as above Figure 9. Simplified Analog Multiplexer Block Diagram 5.14 I/O pins (I/O_0:I/O_5) The 33907/33908 includes six multi-purpose I/Os (I/O_0 to I/O_5). I/O_0, I/O_1, I/O_4, and I/O_5 are load dump proof and robust against ISO7637 pulses. An external serial resistor must be connected to those pins to limit the current during ISO pulses. I/O_2 and I/O_3 are not load dump proof. Table 8. I/Os Configuration I/0 Number Analog Input Digital Input Wake-up Capability Output Gate Driver IO_0 X X X IO_1 X X X IO_2 X X IO_3 X X IO_4 X X X IO_5 X X X • IO_0:1 are selectable as follows: Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_0 AND IO_1 are used if configured as safety inputs, see Figure 11). • IO_1 is also selectable as follow: Safety purpose: FB_Core using a second resistor bridge (R3/R4 duplicated) connected to IO_1, to detect external resistor drift and trigger when FB_Core - IO_1 > 150 mV max. • IO_2:3 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (logic level) on the rising or falling edge or based on the previous state. Safety purpose: Digital input (logic level) to monitor MCU error signals (both IO_2 AND IO_3 are used if configured as safety inputs). Only bi-stable protocol is available. 33907/33908 30 Analog Integrated Circuit Device Data Freescale Semiconductor When IO_2:3 are used as safety inputs to monitor FCCU error outputs from the Freescale MCU, the monitoring is active only when the Fail-safe sate machine is in “normal WD running” state (Figure 14) and all the phases except the “Normal Phase” are considered as an Error. Reset Phase Error Phase Normal Phase Config Phase FCCU_eout[0] FCCU_eout[1] Figure 10. IO_2:3 MCU Error Monitoring: Bi-stable Protocol • IO_4:5 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on previous state. Output gate driver (from VPRE) for low-side logic level MOSFET. Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs, see Figure 11). Error signal (IO_4 input) 33907_8 Internal IO_4 signal latched Acknowledgment counter Reset counter Restart Acknowledgment counter Acknowledgement signal from MCU (IO_5 input) Filter time RSTB FS0B The error is acknowledged by the MCU then, internal IO_4 signal is released The error is NOT acknowledged by the MCU So, FS0B is activated at the end of the counter Figure 11. External Error Signal Handling 5.15 SAFE Output Pins (FS0B, RSTB) FS0B is asserted low when a fault event occurs (See Faults Triggering FS0B Activation on page 45). The objective of this pin is to drive an electrical safe circuitry independent from MCU to deactivate the whole system and set the ECU in a protected and known state. After each power on reset or after each wake-up event (LPOFF) the FS0B pin is asserted low. Then the MCU can decide to release the FS0B pin, when the application is ready to start. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3. • If the pull-up is connected to VDDIO, the value recommended is 5.0kthere will be no current in LPOFF since VDDIO is OFF in LPOFF mode. • If the pull-up is connected to VSUP3, the value must be above 10 k, there will be a current in the pull-up resistor to consider at application level in LPOFF mode. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 31 The RSTB pin must be connected to MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default configuration, the RST delay time has three possible values depending on the mode and product configuration: • The longest one is used automatically following a Power On Reset or when resulting from LPOFF mode (Low Power Off). • The two reset durations are then available in the INIT_FSSM1 register, which are 1.0 ms and 10 ms. The configured duration is finally used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM1 register is available (writing) in the INIT FS phase. 5.16 DEBUG Input (Entering In Debug Mode) The DEBUG pin allows the product to enter Debug mode. To activate the Debug mode, voltage applied to the DEBUG pin must be within the VDEBUG_IL and VDEBUG_IH range at start-up. If the voltage applied to DEBUG pin is out of these limits, before VCORE ramp-up, the device settles into Normal mode. When the Debug mode is activated, the FS0B output is asserted low at start-up. As soon as the FS0B is released to “high” via SPI (Good WD answer and FS_OUT writing) this pin is never activated whatever the fault is reported. In Debug mode, any errors from watchdog are ignored (No reset and No fail-safe), even if the whole functionality of the watchdog is kept ON (Seed, LFSR, Wd_refresh counter, WD error counter). This allows an easy debug of the hardware and software routines (i.e. SPI commands). When the Debug mode is activated, the CAN transceiver is set to Normal operation mode. This allows communication with the MCU, in case SPI communication is not available (case of MCU not programmed). To exit Debug mode, the pin must be tied to Ground through an external pull-down resistor or to VPRE through an external pull-up resistor and a Power On Reset occurs. 33907/33908 32 Analog Integrated Circuit Device Data Freescale Semiconductor 6 6.1 Functional Device Operation Mode and State Description of Main State Machine The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state diagram (Figure 13). Two state machines are working in parallel. The Main state machine is in charge of the power management (VPRE, VCORE, VCCA, VAUX,...) and the fail-safe state machine is in charge of all the safety aspect (WD, RSTB, FS0B,...). 6.1.1 Buck or Buck Boost Configuration An external low side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter. The connection of the external MOSFET is detected automatically during the start-up phase (after a Power On Reset or From LPOFF). • If the external low-side MOSFET is NOT connected (GATE_LS pin connected to PGND), the product is configured as a standard buck converter. • If the external low-side MOSFET is connected (GATE_LS pin connected to external MOSFET gate), the product is configured as a non-inverting buck-boost converter. The automatic detection is done by pushing 300 A current on Gate_LS pin and monitoring the corresponding voltage generated. If a voltage >120 mV is detected before the 120 s timeout, the non-inverting buck-boost configuration is locked. Otherwise, the standard buck configuration is locked. The boost driver has a current capability of 300 mA. 6.1.2 VPRE ON Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched ON and a softstart with a specified duration tPRE_SOFT is started to control the VPRE output capacitor charge. 6.1.3 Select Pin Configuration This phase is detecting the required voltage level on VAUX and VCCA, according to resistor value connected between the SELECT pin and ground. If the SELECT pin is connected to VPRE via the resistor, it disables the VAUX regulator at start-up. 6.1.4 VCORE/VAUX/VCCA ON In this stage, the three regulators VCORE, VAUX, VCCA are switched ON at the same time with a specified soft start duration. The CAN_5V is also started at that time. 6.1.5 INIT Main This mode is automatically entered after the device is “Powered ON”. When RSTB is released, initialization phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (refer to Table 15 and Table 16). Other registers can be written in this mode, and also in Normal mode. Once the INIT registers configurations are complete, a last register called “INIT INT” must be configured to switch to Normal mode. Writing data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to Normal mode in the Main state machine. 6.1.6 NORMAL In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT INT register. While in Normal mode, the device can be set to Low Power mode (LPOFF) using secured SPI command. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 33 6.1.7 Low Power Mode OFF The Main State Machine has 3 LPOFF modes with different conditions to enter and exit each LPOFF mode as described here after. After wake up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched OFF. The register configuration, the Vpre behavior and the ISO pulse requirement are valid for the 3 LPOFF modes. 6.1.7.1 LPOFF - Sleep Entering in Low Power mode LPOFF - SLEEP is only available if the product is in Normal mode by sending a secured SPI command. In this mode, all the regulators are turned OFF and the MCU connected to the VCORE regulator is unsupplied. Before entering in LPOFF Power mode OFF-sleep, the Reset Error Counter must go back to value “0” (“N” consecutive good watchdog refresh decreases the reset error counter to 0). “N” = RSTb_err_2:0 x (WD_refresh_2:0 + 1). Once the 33907/33908 is in LPOFF - SLEEP, the device monitors external events to wake-up and leave the Low Power mode. The wake-up events can occur and depending of the device configuration from: • CAN • LIN • I/O inputs When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (BUCK or BUCKBOOST), the wake-up source is reported to the dedicated SPI register, and the Fail-safe state machine is also restarted. 6.1.7.2 LPOFF - VPRE_UV LPOFF- VPRE_UV is entered when the device is in the INIT or Normal mode, and if the VPRE voltage level is passing the VPRE_UV_L_4P3 threshold (typ 4.3 V). After 1.0 ms the device attempts to recover by switching ON the VPRE again. 6.1.7.3 LPOFF - DEEP FS LPOFF - DEEP FS is entered when the device is in Deep Fail-safe and if the Key is OFF (IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is usually connected to key ON key OFF signal. 6.1.7.4 Register Configuration in LPOFF In LPOFF, the register settings of the Main State Machine are kept because the internal 2.5 V main digital regulator is available for wakeup operation. However, the register settings of the Fail-safe state machine are erased because the 2.5 V fail safe digital regulator is not available in LPOFF. As a consequence, after a wake-up event, the configuration of the Fail-safe registers must be done again during initialization phase (256 ms open window). 6.1.7.5 VPRE Behavior in LPOFF When device is in LPOFF Sleep mode, and if the VSUP < VSUP_UV_7, VPRE is switched on to maintain internal biasing and wake-up capabilities on IOs, CAN or LIN. • If VPRE is configured as a non-inverting buck-boost converter, VPRE is switched ON in SMPS mode with boost functionality. • If VPRE is configured as a standard buck converter, VPRE is switched ON in Linear mode following VSUP. 6.1.7.6 ISO Pulse in LPOFF If the application has to sustain ISO pulses on VBAT in LPOFF mode, the connection of a an external zener diode and a serial resistor to the ground is mandatory (see Figure 12). During repetitive ISO pulses on Vbat, the capacitors connected on VSUP line are more and more charged and cannot be discharged thanks to the extremely low-current needed to maintain wake-up capabilities on IOs, CAN, and LIN. As a consequence, if a leakage path is not created artificially with those discrete components the voltage on VSUP line can exceed the absolute maximum rating supported by this pin. 33907/33908 34 Analog Integrated Circuit Device Data Freescale Semiconductor VBAT VSUP2 VSUP1 33907_08 33907/33908 VSUP3 VSENSE Figure 12. Components Involved Under ISO Pulse in LPOFF 6.2 Mode and State Description of Fail-safe State Machine 6.2.1 LBIST Included in the fail-safe machine, the Logic Built-in Self Test (LBIST) verifies the correct functionality of the FSSM at start-up. The fail-safe state machine is fully checked and if an issue is reported, the RSTB stays low and after 8 s, the device enters in DEEP Fail-safe. LBIST is run at start-up and after each wake-up event when the device is in LPOFF mode. 6.2.2 Select Pin Configuration This phase detects the required voltage level to apply on VAUX and VCCA, according to the resistor value connected between the SELECT pin and ground, (VAUX used) or between the SELECT pin and VPRE (VAUX not used). This mode is the equivalent mode seen in the main state machine. Difference is in the fail-safe machine, this detection is used to internally set the UV/OV threshold on VCCA and VAUX for the voltage supervision. 6.2.3 ABIST Included in the fail-safe machine, the Analog Built-in Self Test (ABIST) verifies the correct functionality of the analog part of the device, like the overvoltage and undervoltage detections of the voltage supervisor and the RTSTB and FS0B fail-safe outputs feedback (Table 9). The ABIST is run at start-up and after each wake-up event when device is in LPOFF mode. Table 9. Regulators and Fail-safe Pins Checked During ABIST 6.2.4 Parameters Overvoltage Undervoltage VPRE X VCORE X X VCCA X X VAUX X X OK/NOK IO_1 FB_Core Delta X RSTB X FS0B X Release RSTB In this state, the device releases the RSTB pin. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 35 6.2.5 INIT FS This mode is automatically entered after the device is “powered on” and only if Built-in Self Tests (Logic and Analog) have been passed successfully. This INIT FS mode starts as soon as RSTB is released (means no “Activate RST” faults are present and no external reset is requested). Faults leading to an “Activate RST” are described in Reset Error Counter. In this mode, the device can be configured via the SPI within a maximum time of 256 ms, including first watchdog refresh. Some registers can only be configured in this mode and is locked when leaving INIT FS mode (refer to Table 15 and Table 16). It is recommended, to configure first the device before sending the first WD refresh. As soon as the first good watchdog refresh is sent by the MCU, the device leaves this mode and goes into Normal WD mode. 6.2.6 Normal WD is Running In this mode, the device waits for a periodic watchdog refresh coming from the MCU, within a specific configured window timing. Configuration of the watchdog window period can be set during INIT FS phase or in this mode. This mode is exited if there are consecutive bad watchdog refreshes if there is an external reset request, or if a fault occurs leading to a RSTB activation. 6.2.7 RST Delay When the reset pin is asserted low by the device, a delay runs, to release the RSTB, if there are no faults present. The reset low duration time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible for writing only in the INIT FS phase. 6.3 Deep Fail Safe state The Fail-safe state machine monitors the RSTB pin of the device and count the number of reset(s) happening in case of fault detection (see Reset Error Counter). As soon as either the Reset Error Counter reach its final value or the RESET pin remains asserted low for more than 8.0 s, the device moves to Deep Fail-safe state, identified by the “Wait Deep Fail-safe” state in the functional state diagram (Figure 13). When the device is in Deep Fail-safe state, all the regulators are OFF. To exit this state, a Key OFF / Key ON action is needed. IO_0 is usually connected to key signal. Key OFF (IO_0 low) will move the device to LPOFF-Deep FS, and Key ON (IO_0 high) will wake-up the device. The final value of the Reset Error Counter can be configured to 2 or 6 in the register INIT FSSM 2. During power up phase, the 8.0 s timer starts when the Fail-safe state machine enters in the “Select pin config detection” state and stop when the RSTB pin is released. During “INIT FS” state, the 8.0 s timer can be disabled in the register INIT SUPERVISOR 2. During “Normal WD running” state, the 8.0 s timer is activated at each RSTB pin assertion. 33907/33908 36 Analog Integrated Circuit Device Data Freescale Semiconductor 6.4 Functional State Diagram Wait Fail SAFE VSUP > VSUP_UV_5 PowerDown No POR Fail Safe POR Fail Safe & Fail Safe Reg. ON & VSUP > VSUP_UV_5 VSUP < VSUP_UV_L From Anywhere From Anywhere PowerDown POR Fail Safe VSUP < VSUP_UV_5 Buck or Buck Boost configuration detection - RSTb is asserted low LBIST LBIST Done & VPRE>VPRE_UV 120µs elapsed VSUP < VSUP_UV_5 Vpre OFF VPRE ON Vpre ON VPRE<VPRE_UV VPRE>VPRE_UV SELECT pin config. detection 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV VPRE<VPRE_UV SELECT pin config. detection Wait Deep Fail Safe - RSTb is asserted low - RSTb is asserted low ABIST 1ms elapsed RST delay=8s or RST error counter = 6 Vcore/Vaux/ Vcca ON No IO_0 ABIST Pass No activate RST & - RSTb delay running RST delay expired - RSTb is asserted low RST Delay - Unlock SPI init registers - SPI config Activate RST VPRE_UV_L4P3 INIT MAIN External RST Release RSTb - RSTb is released No external RST & No activate RST External RST INIT done (init int reg. writing) - SPI init registers locked NORMAL MODE Activate RST or WD Not OK VPRE_UV_L4P3 WD OK SPI command LPOFF DEEP FS LPOFF SLEEP External RST LPOFF - - VCAN/VCORE/VAUX/VCCA OFF Activate RST VPRE_UV - Fail Safe OFF CAN/IOs event Wake up - VCAN/VCORE OFF - VAUX/VCCA OFF - OSC Main ON - FailSafe ON MAIN STATE MACHINE NORMAL WD is RUNNING - Start WD close/open window 1ms Rise IO_0 POR Fail Safe & Fail Safe Reg. ON - Unlock SPI init registers - Start 256ms open window - RSTb is released INIT FS Activate RST : any UV, any OV, WD, IO_23 error, deep fail safe, reset by spi, IO_1 FB_core delta, FS0b short to VDD, SPI DED FAIL SAFE STATE MACHINE Figure 13. Simplified State Diagram 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 37 6.5 Fail-safe Machine To fulfill safety critical applications, the 33907/33908 integrates a dedicated fail-safe machine (FSM). The FSM is composed of three main sub-blocks: the Voltage Supervisor (VS), the Fail-safe state machine (FSSM), and the Fail-safe output driver (FSO).The FSM is electrically independent from the rest of the circuitry, to avoid common cause failure. For this reason, the FSM has its own voltage regulators (analog and digital), dedicated bandgap, and its own oscillator. Three power supply pins (VSUP 1, 2, & 3) are used to overtake a pin lift issue. The internal voltage regulators are directly connected on VSUP (one bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. All the voltages generated in the device are monitored by the voltage supervisor (under & overvoltage) owing to a dedicated internal voltage reference (different from the one used for the voltage regulators). The result is reported to the MCU through the SPI and delivered to the Fail-safe state machine (FSSM) for action, in case of a fault. All the safety relevant signals feed the FSSM, which handles the error handling and controls the fail-safe outputs. There are two fail-safe outputs: RSTB (asserted low to reset the MCU), and FS0B (asserted low to control any fail-safe circuitry). The Failsafe machine is in charge of bringing and maintaining the application in a Fail-safe state. Four sub Fail-safe states are implemented to handle the different kinds of failures, and to give a chance for the system to come back to a normal state. 6.5.1 Fail-safe Machine State Diagram No POR Fail-safe From Anywhere PowerDown POR Fail-safe LBIST - RSTb is asserted low LBIST Done & VPRE>VPRE_UV SELECT pin config. detection VPRE<VPRE_UV - RSTb is asserted low 1ms elapsed & VCORE > VCORE_UV & VCCA > VCCA_UV & VAUX > VAUX_UV ABIST RSTb delay = 8s IO_0 - RSTb is asserted low ABIST Pass - RSTb delay running - RSTb is asserted low RST delay=8s OR Rst_error_count=6 - VCAN/VCORE OFF - VAUX/VCCA OFF - Fail Safe OFF Deep Fail Safe - FS0b = Low - RSTb = Low Assert RSTb No activate RST & RST delay expired Activate RST FS0b low & No activate RST & RST delay expired External RST - RSTb is released No external RST & No activate RST External RSTb = 8s External RST Activate RST 2 > RST_error_count < 6 Release RSTb Activate RST or WD Not OK INIT FS - Unlock SPI init registers - Start 256ms open window - RSTb is released WD OK RST delay=8s - FS0b is asserted low FS0B Low Ext. IC error (IO0:1 and/or IO4:5) Ext. IC error (IO0:1 and/or IO4:5) External RST RST_err_count = 0 & FS_OUT ok NORMAL WD is RUNNING - Start WD close/open window Release FSOb -FS0b is released No FS0b Figure 14. Detailed Fail-safe State Diagram 33907/33908 38 Analog Integrated Circuit Device Data Freescale Semiconductor 6.5.2 Watchdog Operation A windowed watchdog is implemented in the 33907/33908 and is based on “question/answer” principle (Challenger). The watchdog must be continuously triggered by the MCU in the open watchdog window, otherwise an error is generated. The error handling and watchdog operations are managed by the Fail-safe state machine. For debugging purpose, this functionality can be inhibited by setting the right voltage on the DEBUG pin at start-up. The watchdog window duration is selectable through the SPI during the INIT FS phase or in Normal mode. The following values are available: 1.0 ms, 2.0 ms, 3.0 ms, 4.0 ms, 6.0 ms, 8.0 ms, 12 ms, 16.0 ms, 24 ms, 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, and 1024 ms. The watchdog can also be inhibited through the SPI register to allow “reprogramming” (ie.at vehicle level through CAN). An 8-bit pseudo-random word is generated, due to a Linear Feedback Shift Register implemented in the 33907/33908. The MCU can send the seed of the LFSR or use the LFSR generated by the 33907/33908 during the INIT phase and performs a pre-defined calculation. The result is sent through the SPI during the “open” watchdog window and verified by the 33907/33908. When the result is right, a new LFSR is generated and the watchdog window is restarted. When the result is wrong, the WD error counter is incremented, the watchdog window is restarted, an INTB is generated, and the LFSR value is not changed. Any access to the WD register during the “closed” watchdog window is considered a wrong WD refresh. 6.5.2.1 Normal Operation (First Watchdog Refresh) At power up, when the RSTB is released as high (after around 16 ms), the INIT phase starts for a maximum duration of 256 ms and this is considered as a fully open watchdog window. During this initialization phase the MCU sends the seed for the LFSR, or uses the default LFSR value generated by the 33907/33908 (0xB2), available in the WD_LFSR register (Table 75). Using this LFSR, the MCU performs a simple calculation based on this formula. As an example, the result of this calculation based on LFSR default value (0xB2) is 0x4D. LFSR_OUT[7:0] x + - 4 6 4 NOT / WD_answer[7:0] 4 Figure 15. Watchdog Answer Calculation The MCU sends the results in the WD answer register (Table 77). When the watchdog is properly refreshed during the open window, the 256 ms open window is stopped and the initialization phase is finished. A new LFSR is generated and available in the WD LFSR register, Table 74. If the watchdog refresh is wrong or if the watchdog is not refreshed during this 256 ms open window (INIT FS phase), the device asserts the reset low and the RSTB error counter is incremented by “1”. After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed windows are defined either by the configuration made during initialization phase in the watchdog window register (Table 73), or by the default value already present in this register (3.0 ms). 6.5.2.2 Normal Watchdog Refresh The watchdog must be refreshed during every open window of the window period configured in the register Table 73. Any WD refresh restarts the window. This ensures the synchronization between MCU and 33907/33908. The duration of the “window” is selectable through the SPI with no access restriction, means the window duration can be changed in the INIT phase or Normal mode. Doing the change in normal operation allow the system integrator to configure the watchdog window duration on the fly: • The new WD window duration (except after disable) will be taken into account when a write in the WD_answer register occurs (good or bad WD answer) or when the previous WD window is finished without any writing (WD timeout) • The new WD window duration after disable will be taken into account when SPI command is validated The duty cycle of the window is set to 50% and is not modifiable. Window Period CLOSED OPEN Refresh Slot CLOSED OPEN Refresh Slot Figure 16. Windowed Watchdog 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 39 6.5.2.3 Watchdog in Debug Mode When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does not affect the device operation by asserting a reset or fail-safe pins. For the user, operation appears without the watchdog. If needed and to debug the watchdog itself, the user can operate as in Normal mode and check LFSR values, the watchdog refresh counter, the watchdog error counter, and reset counter. This allows the user to debug their software and ensure a good watchdog strategy in the application. 6.5.2.4 Wrong Watchdog Refresh Handling Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. According to consecutive numbers of wrong watchdog refreshes, the device can decide to assert the RSTB only, or to go in deep Fail-safe mode where only a Power On Reset or a transition on IO_O helps the system to recover. 6.5.2.5 Watchdog error counter The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a watchdog failure occurs, the device increments this counter by 2. The WD error counter is decremented by 1 each time the watchdog is properly refreshed. This principle ensures that a cyclic “OK/NOK” behavior converges to a failure detection. To allow flexibility in the application, the maximum value of this counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. Watchdog Error Counter WD_CNT_error = 6 WD refresh NOK 0 WD refresh NOK 1 WD refresh NOK 2 Watchdog Error Counter WD_CNT_error = 4 WD refresh NOK 0 WD refresh NOK 1 WD refresh NOK 2 WD refresh OK WD refresh NOK 0 WD refresh OK WD refresh OK 1 WD refresh OK WD refresh OK WD refresh NOK Watchdog Error Counter WD_CNT_error = 2 2 WD refresh OK 3 3 WD refresh NOK WD refresh OK WD refresh NOK 4 4 WD refresh OK 5 WD refresh NOK 6 Figure 17. Watchdog Error Counter Configuration (INIT_WD register, Bits WD_CNT_error_1:0) 33907/33908 40 Analog Integrated Circuit Device Data Freescale Semiconductor 6.5.2.6 Watchdog Refresh Counter The watchdog refresh counter is used to decrement the RST error counter. Each time the watchdog is properly refreshed, the watchdog refresh counter is incremented by “1”. Each time the watchdog refresh counter reaches “6” and if next WD refresh is also good, the RST error counter is decremented by “1” (case with WD_CNT_refresh_1:0 configured at 6). Whatever the position is in the watchdog refresh counter, each time there is a wrong refresh watchdog, the watchdog refresh counter is reset to “0”. To allow flexibility in the application, the maximum value of this watchdog refresh counter is configurable in the INIT_WD register, but only when device is in INIT FS mode. Watchdog Refresh Counter WD_CNT_refresh = 6 Watchdog Refresh Counter WD_CNT_refresh = 4 WD Refresh NOK 2 WD Refresh OK 3 WD Refresh OK 4 WD Refresh OK 5 WD Refresh OK 6 WD Refresh OK WD Refresh NOK / WD_OFF WD Refresh OK WD Refresh NOK / WD_OFF WD Refresh OK WD Refresh NOK / WD_OFF 0 WD Refresh OK 1 WD Refresh NOK / WD_OFF 2 3 4 WD Refresh NOK 0 0 WD Refresh OK 1 Watchdog Refresh Counter WD_CNT_refresh = 1 WD Refresh NOK WD Refresh NOK 0 WD Refresh OK WD Refresh OK Watchdog Refresh Counter WD_CNT_refresh = 2 WD Refresh NOK / WD_OFF WD Refresh OK 1 WD Refresh OK 2 WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF 1 WD Refresh OK / WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF WD Refresh NOK / WD_OFF WD Refresh OK / WD Refresh NOK / WD_OFF Figure 18. Watchdog Refresh Counter Configuration (INIT_WD register, WD_CNT_refresh_1:0) Table 10. Watchdog Error Table WINDOW SPI CLOSED OPEN BAD Key WD_NOK WD_NOK GOOD Key WD_NOK WD_OK None (time out) No_issue WD_NOK Any access to the watchdog register during the “closed” watchdog window is considered as a wrong watchdog refresh. Watchdog timeout, meaning no WD refresh during closed or open windows, is considered as a wrong WD refresh. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 41 6.5.3 Reset Error Counter The reset error counter manages the reset events and counts the number of resets occurring in the application. This counter is incremented not only for the reset linked to consecutive wrong refresh watchdogs, but also for other sources of reset (undervoltage, overvoltage, external reset). The RST error counter is incremented by 1, each time a reset is generated. The reset error counter has two output values (intermediate and final). The intermediate output value is used to handle the transition from reset (RSTB is asserted low) to reset and fail where RSTB and FS0B are activated. The final value is used to handle the transition from reset and fail to deep reset and fail (Deep Fail-safe mode), where regulators are off, RSTB and FS0B are activated, and a power on reset or a transition on IO_0 is needed to recover. The intermediate value of the reset error counter is configurable to “1” or “3” using the RSTB_err_FS bit in the INIT FSSM2 register (Table 71). If RSTB_err_FS is set to “0”, it means the device activates FS0B when the reset error counter reaches level “3”. If RSTB_err_FS is set to “1”, it means the device activates FS0B when the reset error counter reaches level “1”. This configuration must be done during INIT FS phase. The final value of the reset error counter is based on the intermediate configuration. • RSTB_err_FS = 0 / Intermediate = 3; Final = 6 (Figure 19). When reset error counter reaches 6, the device goes into deep reset and fails. • RSTB_err_FS = 1 / Intermediate = 1; Final = 2 (Figure 20). When reset error counter reaches 2, the device goes into deep reset and fails. In any condition, if the RSTB is asserted LOW for a duration longer than eight seconds, the device goes into deep reset and fails. Conditions that leads to an increment of the RSTB error counter, and according to the product configuration are: • Watchdog error counter = 6 • Watchdog refresh NOK during INIT phase or Watchdog timeout • IO_23 error detection (FCCU) • Undervoltage • Overvoltage • IO_1 FB_Core Delta • FS0B shorted to VDD • SPI DED • Reset request by the SPI • External reset Conditions leading to a transition go to FS, according to the product configuration are: • IO_01/IO_23/IO_45 error detection • Undervoltage • Overvoltage • IO_1 FB_Core Delta • Analog BIST fail • SPI DED • RSTB shorted to high 33907/33908 42 Analog Integrated Circuit Device Data Freescale Semiconductor Reset Error Counter (Cfg SPI RSTb_err_FS=0; WD_CNT_refresh=6) 7 consecutive WD Refresh OK POR or from LPOFF mode gotoFS INCR 7 consecutive WD Refresh OK INCR 7 consecutive WD Refresh OK INCR 7 consecutive WD Refresh OK 1 INCR = WD error counter = WD_CNT_error[1:0] | WD refresh NOK during INIT | IO23_ERR |UV/OV | IO_1 FB_Core delta | FS0b_shorttovdd | SPI DED | Reset by SPI | External reset gotoFS = IO01/23/45_ERR | UV/OV| IO_1 FB_Core delta | ABIST_fail | SPI DED | RSTb_short2hi (7 = WD_CNT_refresh + 1) 0 gotoFS 2 3 Active FS0 INCR 7 consecutive WD Refresh OK 4 Active FS0 INCR 7 consecutive WD Refresh OK 5 Active FS0 INCR Active FS0 Turn OFF regulators 6 RSTb asserted for 8 seconds Figure 19. RSTB Error Counter (RSTB_err_FS = 0) Reset Error Counter (Cfg SPI RSTb_err_FS=1; WD_CNT_refresh=6) INCR = WD error counter = WD_CNT_error[1:0] | WD refresh NOK during INIT | IO23_ERR |UV/OV | IO_1 FB_Core delta | FS0b_shorttovdd | SPI DED | Reset by SPI | External reset 7 consecutive WD Refresh OK POR or from LPOFF mode INCR/gotoFS Active FS0 gotoFS = IO01/23/45_ERR | UV/OV | IO_1 FB_Core delta | ABIST_fail | SPI DED | RSTb_short2hi (7 = WD_CNT_refresh + 1) 0 7 consecutive WD Refresh OK 1 INCR Active FS0 Turn OFF regulators 2 RSTb asserted for 8 seconds Figure 20. RSTB Error Counter(RSTb_err_FS = 1) 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 43 6.5.3.1 RST Error Counter at Start-up or Resuming from LPOFF Mode At start-up or when resuming from LPOFF mode the reset error counter starts at level 1 and FS0B is asserted low. To remove activation of FS0B, the RST error counter must go back to value “0” (seven consecutive good watchdog refresh decreases the reset error counter down to 0) and a right command is sent to FS_OUT register (Figure 23). 1st WD refresh OK after INIT phase. Start of the WD window New fully OPEN window of 256 ms WD window OK WD error counter NOK 0 NOK 3 4 2 NOK OK Reset error counter OK NOK 6 4 5 1 RSTb delay time RSTB WD Refresh counter 0 1 0 0 0 1 1 0 Figure 21. Example of WD Operation Generating a Reset (WD_error_cnt = 6) New fully OPEN window of 256 ms WD window OK NOK WD error counter 4 Reset error counter 1 RSTb WD Refresh counter OK OK OK OK OK OK OK 0 6 2 1 RSTb delay time 0 1 2 3 4 5 6 0 1 Figure 22. Example of WD Operation Leading a Decrement of the Reset Error Counter (WD_resfresh_cnt = 6) 33907/33908 44 Analog Integrated Circuit Device Data Freescale Semiconductor # WD refresh counter max value +1 consecutive WD answers OK FS_OUT write OK Reset error counter RST_ERR_CNT 1 # WD refresh counter max value +1 consecutive WD answers OK 0 1 RSTb FS0b WD error counter =6 WD error counter =6 WD error counter =6 2 FS_OUT write OK 3 2 1 0 Reset delay Output stage ON OFF ON OFF Figure 23. Reset Error Counter and FS0B Deactivation Sequence (RSTB_err_FS = 0 & WD_CNT_error1:0 = 6) 6.5.4 Fail-safe Output (FS0B) Deactivation When the fail-safe output FS0B is asserted low by the device due to a fault, some conditions must be validated before allowing the FS0B pin to be deactivated by the device. These conditions are: • Fault is removed • Reset error counter must be at “0” • FS_OUT register must be filled with the right value. 6.5.4.1 Faults Triggering FS0B Activation The activation of the FS0B is clearly dependent on the product configuration, but the following items can be settled: • IO_01/IO_23/IO_45 error detection • Undervoltage • Overvoltage • IO_1 FB_Core Delta • Analog BIST fail (not configurable) • SPI DED (not configurable) • RSTB shorted to high (not configurable) • RSTB error counter level 6.5.5 SPI DED Some SPI registers affect some safety critical aspects of the fail-safe functions, and thus are required to be protected against SEU (Single Event Upset). Only fail-safe registers are concerned. During INIT FS mode, access to fail-safe registers for product configuration is open. Then once the INIT FS phase is over, the Hamming circuitry is activated to protect registers content. At this stage, if there is 1 single bit flip, the detection is made due to hamming code, and the error is corrected automatically (fully transparent for the user), and a flag is sent. If there are two errors (DED - Dual Error Detection), the detection is made due to hamming code but detected errors cannot be corrected. Flag is sent, RSTB and FS0B are activated. 6.5.6 FS_OUT Register When fault is removed and reset error counter changes back to level “0”, a right word must be filled in the FS_OUT register. The value is dependant on the current WD_LFSR. LSB and MSB must be swapped and negative operation per bit must be applied. WD_LFSR_7:0= b7 b6 b5 b4 b3 b2 b1 b0 FS_OUT_7:0 = b0 b1 b2 b3 b4 b5 b6 b7 Figure 24. FS_OUT Register Based on LFSR Value 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 45 6.6 Input Voltage Range Due to the flexibility of the pre-regulator, the device can cover a wide battery input voltage range. However, a more standard voltage range can still be covered using only the Buck configuration. VSUP Buck-Boost Buck only No operation Risk of damage No operation Risk of damage 40 V Extended voltage range Extended voltage range Potential Vpre thermal limitation Potential Vpre thermal limitation 28 V Extended voltage range Extended voltage range Amux limitation Amux limitation 19 V Normal voltage range Normal voltage range VSUP_UV_7 Extended voltage range 6.0 V Extended voltage range Vpre output current limitation 4.6 V VPRE output current limitation 2.7 V No operation No operation Figure 25. Input Voltage Range • VSUP > 28 V: Potential VPRE thermal limitation RDS(on), Current limitation and Overcurrent detection are specified for VSUP < 28 V. • VSUP < 19 V: Mux_out limitation IO_0 and IO_1 maximum analog input voltage range is 19 V. Internal 2.5 V reference voltage accuracy degraded. • Buck only, VSUP < VSUP_UV_7: CAN communication is guaranteed for VSUP > 6.0 V. LIN communication according to SAEJ2602-2 specification is stopped (VSUP < 7.0 V). For VCCA and VAUX 5.0 V configuration, undervoltage triggers at low VSUP (refer to VCCA_UV_5 and VAUX_UV_5). 6.7 Power Management Operation A thermal sensor is implemented as close as possible to the pass transistor of each regulator (VPRE, VCORE, VCCA, VCAN) and an associated individual Thermal Shutdown (TSD) protect these regulators independently. When the TSD threshold of a specific regulator is reached, this regulator only is switched OFF and the information is reported in the main state machine. The regulator restarts automatically when the junction temperature of the pass transistor decrease below the TSD threshold. 33907/33908 46 Analog Integrated Circuit Device Data Freescale Semiconductor 6.7.1 VPRE Voltage Pre-regulator A highly flexible SMPS pre-regulator is implemented in the 33907/33908. Depending on the input voltage requirement, the device can be configured as “non-inverting buck-boost converter” (Figure 27) or “standard buck converter” (Figure 26). An external logic level MOSFET (N-type) is required to operate in “non-inverting buck-boost converter”. The connection of the external MOSFET is detected automatically during the start-up phase. The converter operates in Current Control mode in any configuration. The high-side switching MOSFET is integrated to make the current control easier. The PWM frequency is fixed at 440 kHz typical. The compensation network is fully integrated. VPRE output voltage is regulated between 6.0 V and 7.0 V. If the full current capability is not used for VCORE, VCCA, VAUX and CAN_5V, additional external LDO can be connected to VPRE to fulfill application needs while the current load remains below the maximum current capability in all conditions. PGND PGND PGND Cout_Vpre4 ESR cap. <10 m Cout_Vpre3 Cout_Vpre2 Cout_Vpre1 ESR cap. <100 m D_Vpre Cboot_pre Rsunb_Vpre Csnub_Vpre L_VPRE PGND PGND PGND PGND VPRE Gate_LS Boots_pre SW_pre2 SW_pre1 Figure 26. Pre-regulator: Buck configuration PGND PGND PGND PGND ESR cap. <10 m Cout_Vpre4 Cout_Vpre3 Cout_Vpre1 Cout_Vpre2 ESR cap. <100 m D_BB LS_BB D_Vpre Cboot_pre Rsunb_Vpre Csnub_Vpre L_Vpre PGND PGND Optional PGND VPRE Gate_LS Boots_pre SW_pre2 SW_pre1 Figure 27. Pre-regulator: Buck Boost configuration When the converter is set up to work in boost mode at low VSUP, the transition between buck and boost mode is automatically handled by the device at VSUP_UV_7 threshold. Transition between buck mode and boost mode is based on hysteresis (Figure 28). • When VSUP > VSUP_UV_7, the converter works in buck mode and VPRE output is regulated at 6.5 V typic. • When VSUP < VSUP_UV_7, the converter works in boost mode and VPRE output is regulated at 6.3 V typic. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 47 D (%) D buck D boost VPRE (V) 100 6.5 hysteresis 66 50 33 25 0 7.5 12 18 24 VIN (V) Figure 28. Transition between Buck and Boost 6.7.1.1 Power Up and Power Down Sequence VSNS_UV VSUP_UV_5 VSUP_UV_L_B Vbattery 0V Vsup Buck_Boost Mask Buck Boost Buck Boost Vpre_EN Vpre Vcore VCORE_FB_UV * ((R3+R4)/R4) INTB (Vddio=Vcore) RSTB RST delay time Figure 29. Buck Configuration Power-up and Power-down 33907/33908 48 Analog Integrated Circuit Device Data Freescale Semiconductor VSUP_UV_7 VSUP_UV_5 VSUP_UV_L Vbattery 0V Vsup Buck_Boost Mask Buck Boost Buck Boost Vpre_EN Vpre Vcore VCORE_FB_UV * ((R3+R4)/R4) INTB (Vddio=Vcore) RSTB RST delay time Figure 30. Buck Boost Configuration Power-up and Power-down 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 49 6.7.1.2 Cranking management When VPRE is set up to work in buck only mode, the application can work down to VSUP = VSUP_UV_L_B = 4.6V with a minimum of 500 mA current guaranteed on VPRE.. VSENSE VSUP VSNS_UV VSUP_UV_L_B Buck_Boost Mask Buck VPRE_EN VPRE VCORE VCORE_FB_UV * ((R3+R4)/R4) INTB RSTB Figure 31. Behavior During Cranking (Buck Configuration) When VPRE is set up to work in boost mode, the application can work down to VSUP = VSUP_UV_L = 2.7V with a minimum of 300 mA current guaranteed on VPRE. The boost mode configuration help to pass LV124 specification requiring a minimum of 3.2 V on VBAT supply during cold cranking conditions. 33907/33908 50 Analog Integrated Circuit Device Data Freescale Semiconductor VSUP VSUP_UV_7 VSUP_UV_L Buck_Boost Mask Buck Buck Boost Boost VPRE_EN VPRE VCORE VCORE_FB_UV * ((R3+R4)/R4) INTB RSTB Figure 32. Behavior during Cranking (Buck Boost Configuration) 6.7.1.3 Light Load Condition In order to improve the converter efficiency and avoid any unwanted output voltage increase, VPRE voltage regulator operates in Pulse Skipping mode during light load condition. The transition between Normal mode and Pulse Skipping mode is based on the comparison between the error amplifier output (EA_out) and pre-defined thresholds VPRE_LL_H and VPRE_LL_L. When the Error Amplifier output reaches VPRE_LL_L, VPRE high-side transistor is switched OFF. When the Error Amplifier output reaches VPRE_LL_H, VPRE high-side transistor is switched ON again for the next switching period (Figure 33). VPRE VSUP1/2 EA_out Vpre_LL_H Vpr e_L L_L Error Amplifier EA_out Light Load Comparator (Hyst 20mV) GN D Ref Vp re_LL_L VPRE HS Driver Lig ht L oa d fla g HS Ga te d rive SW_PRE Figure 33. Description of Light Load Condition 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 51 6.7.1.4 Input Power Feed Forward Condition In order to improve the converter efficiency during high input power condition, VPRE switching frequency is reduced from 440 kHz to 220 kHz when VSUP > VSUP_IPFF and IPRE > IPRE_IPFF_PK to decrease the switching losses. The transition between the two frequencies is transparent for the application. VSUP_IPFF VSUP Ipk envelop IPFF VPRE_FSW 440 kHz 220 KHz 440 kHz Figure 34. Input Power Feed Forward Principle 6.7.1.5 6.7.1.5.1 Overcurrent Detection and Current Limitation Overcurrent protection: In order to ensure the integrity of the high-side MOSFET, an overcurrent detection is implemented. The regulator is switched OFF by the Main State machine when the over-current detection threshold IPRE_OC is reached three consecutive times. The overcurrent detection is blanked when the pass transistor is switched ON during TPRE_OC to avoid parasitic switch OFF of the high-side gate driver. The VPRE output voltage decrease causes an undervoltage condition on one of the cascaded regulators (VCORE, VCCA, VAUX) and bring the device in Fail-safe state. The overcurrent protects the regulator in case of SW_PRE pin shorted to GND. The overcurrent works in Buck mode only. 6.7.1.5.2 Current Limitation: A current limitation is also implemented to avoid uncontrolled power dissipation inside the device (duty cycle control) and limits the current below IPRE_LIM. The current limitation is blanked when the pass transistor is switched ON during TPRE_BLK_LIM to allow short-circuit detection on SW_PRE pin. When IPRE_LIM threshold is reached during Buck mode, the high-side integrated MOSFET is switched OFF. When IPRE_LIM threshold is reached during Boost mode, the external low-side MOSFET is switched OFF. In both cases, the MOSFET is not switched ON again before the next rising edge of the switching clock. The current limitation will induce a duty cycle reduction and will lead to VPRE output voltage to fall down gradually and may cause an undervoltage condition on one of the cascaded regulators (VCORE, VCCA, VAUX) and bring the device in Fail-safe state. The current limitation does not switch OFF the regulator. The current limitation protects the regulator when VPRE pin is shorted to GND. 33907/33908 52 Analog Integrated Circuit Device Data Freescale Semiconductor IPRE_OC IPRE_LIM IPRE_SW SW_PRE TPRE_BLK_ILIM TPRE_OC VPRE Figure 35. Overcurrent and Current Limitation scheme 6.7.1.6 VPRE Voltage Monitoring The overvoltage detection switches OFF the regulator. The undervoltage detector is disabled when the regulator is switched OFF reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt. The undervoltage detection does not switches OFF the regulator. However, VPRE decrease may induce an undervoltage on a regulator attached to VPRE (VCORE, VCCA, VAUX, or CAN_5V), and bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1,2,3). 6.7.1.7 VPRE Efficiency VPRE efficiency versus current load is given for information based on typical external component criteria described in the table close to the graph and at three different VSUP voltages (8.0 V, 14 V, and 18 V) covering typical automotive operating range. The efficiency is valid in buck mode only and above 200 mA load on VPRE in order to be in continuous mode in the 22 µH inductor. The efficiency is calculated and has to be verified by measurement at application level. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Figure 36. VPRE Efficiency 6.7.2 VCORE Voltage Regulator This voltage regulator is a step-down DC-DC converter operating in Voltage Control mode. The high side switching MOSFET is integrated in the device and the PWM frequency is fixed at 2.4 MHz typical. The output voltage is configurable from 1.2 V to 3.3 V range and adjustable around these voltages with an external resistor divider (R3/R4) connected between VCORE and the feedback pin (FB_CORE) (Figure 37). VCORE = VCORE_FB x ((R3 + R4) / R4) The voltage accuracy is 2.0% (without the external resistor bridge R3/R4 accuracy) and the max output current is 1.5 A. The stability of the overall converter is done by an external compensation network (R1/C1/R2/C2) connected to the pin COMP_CORE. It is recommended to use 1% accuracy resistors and set R4 = 8.06 k and adjust R3 to obtain the final VCORE voltage needed for the MCU core supply. R3 GND PGND R1 PGND EMI Cout_Vcore Cout2_Vcore EMI Vcore_sns C1 Cout1_Vcore ESR cap. <100m D_Vcore Rsnub_Vcore Cboot_Core Csnub_Vcore L_Vcore PGND PGND PGND FB_CORE EMI FB_core BOOT_CORE SW_CORE VCORE_SNS GND R4 GND COMP_CORE Figure 37. VCORE Buck Regulator 33907/33908 54 Analog Integrated Circuit Device Data Freescale Semiconductor 6.7.2.1 Light Load Condition In order to improve the converter efficiency and avoid any unwanted output voltage increase, VCORE voltage regulator operates in Pulse Skipping mode during light load condition. The principle is the same as the VPRE implementation described in details in Light Load Condition. 6.7.2.2 Current Limitation A current limitation is implemented to avoid uncontrolled power dissipation inside the device (duty cycle control) and limits the current below ICORE_LIM. The current limitation is banked when the pass transistor is switched ON during TCORE_BLK_LIM to avoid parasite detection. When ICORE_LIM threshold is reached, the high-side integrated MOSFET is switched OFF. The MOSFET is not switched ON again before the next rising edge of the switching clock. The current limitation will induce a duty cycle reduction and will lead to VCORE output voltage to fall down gradually and may cause an undervoltage condition and bring the device in Fail-safe state. The current limitation does not switch OFF the regulator. 6.7.2.3 Voltage Monitoring The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1,2, 3). 6.7.2.4 VCORE Efficiency Vcore efficiency versus current load is given for information based on typical external component criteria described in the table close to the graph and at two different VCORE voltages (3.3 V, and 1.2 V) covering most of the 32-bit MCU supply range. The efficiency is valid above 200 mA load on VCORE in order to be in continuous mode in the 2.2 µH inductor. The efficiency is calculated and has to be verified by measurement at application level. One of the major contributor degrading the efficiency at VCORE = 1.2 V is the external diode during the recirculation phase. Lower the diode Forward Voltage (VF) is, the better the efficiency. Figure 38. VCORE Efficiency 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 55 6.7.3 Charge Pump and Bootstrap Both switching MOSFETs of VPRE and VCORE SMPS are driven by external bootstrap capacitors. Additionally, a charge pump is implemented to ensure 100% duty cycle for both converters. Each converter uses a 100 nF external capacitor minimum to operate properly. 6.7.4 VCCA Voltage Regulator VCCA is a linear voltage regulator mainly dedicated to supply the MCU I/Os, especially the ADC. The output voltage is selectable at 5.0 V or 3.3 V. Since this output voltage can be used to supply MCU I/Os, the output voltage selection is done using an external resistor connected to the SELECT pin and ground if VAUX is used. When VAUX is not used, the resistor is connected between the SELECT pin and VPRE. When VCCA is used with the internal MOS transistor, VCCA_E pin must be connected to VPRE. The voltage accuracy is 1.0% for 5.0V configuration and 1.5% for 3.3 V configuration with an output current capability at 100 mA. When VCCA is used with an external PNP transistor to boost the current capability up to 300 mA, the connection is detected automatically during the start-up sequence of the 33907/33908. In such condition, the internal pass transistor is switched OFF and all the current is driven through the external PNP to reduce the internal power dissipation. The output voltage accuracy with an external PNP is reduced to 3.0% at 300 mA current load. The VCCA output voltage is used as a reference for the Auxiliary voltage supply (VAUX) when VAUX is configured as a tracking regulator. 6.7.4.1 Current Limitation A current limitation is implemented to avoid uncontrolled power dissipation of the internal MOSFET or external PNP transistor. By default, the current limitation threshold is selected based on the auto detection of the external PNP during start up phase. • When the internal MOSFET transistor is used, the current is limited to ICCA_LIM_INT and the regulator is kept ON • When the external PNP transistor is used, the current is limited to ICCA_LIM_OUT and the regulator is switch OFF after a dedicated duration TCCA_LIM_OFF under current limitation. A SPI command is needed to restart the regulator. In case of external PNP configuration only, the lowest current limitation threshold can be selected by SPI in the register INIT VREG 2 instead of the highest one. In order to limit the power dissipation in the external PNP transistor in case of short circuit to GND of VCCA pin, a current limitation foldback scheme is implemented to reduce the current limitation to ICCA_LIM_FB when VCCA is below VCCA_LIM_FB. 6.7.4.2 Voltage Monitoring The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1, 2, 3). 6.7.5 VAUX Voltage Regulator VAUX is a highly flexible linear voltage regulator that can be used either as an auxiliary supply dedicated to additional device in the ECU or as a sensor supply (i.e. outside the ECU). An external PNP transistor must be used (no internal current capability). If VAUX is not used in the application, VAUX_E and SELECT pins must be connected to VPRE in order to not populate the external PNP as described in Figure 60. If VAUX is used as an auxiliary supply, the output voltage is selectable between 5.0 V, 3.3 V. Since this voltage rail can be used to supply MCU IOs, the selection is done with an external resistor connected between the SELECT pin and ground. In such case, the voltage accuracy is 3.0% with a maximum output current capability at 300 mA. If VAUX is used as a sensor supply rail, the output voltage is selectable between 5.0 V and 3.3 V. VCCA can be used as reference for the sensor supply used as tracker. The selection is done during the INIT phase and secured (bit VAUX_TRK_EN in the register INIT VREG2). The tracking accuracy is 15 mV. 33907/33908 56 Analog Integrated Circuit Device Data Freescale Semiconductor L3 - 2.2 µH Vcore VDD_LV_1.2V D4 C6 100nF R3 R1 PGND PGND Vcore_sns Boot_core SW2 C7 40µF C10 FB1 MCU R4 Vcore Buck – 1.5A GND Comp1 R2 C11 Vcca_E VCCA - LDO1 100/300mA V_Peripherals & I/O Vcca_B Vcca 5V V_ADC_5V C8 4.7 µF GND Input ref VAUX - LDO2 300mA Vaux_E PNP2 Vaux_B ADC_IN +/- 15mV Int 3.3/ 5V ref Vaux 5V Ext Sensor C9 4.7 µF GND GND 33907/33908 ECU limit Figure 39. Example of VAUX Used in Tracker Mode 6.7.5.1 Current limitation A current limitation is implemented to avoid uncontrolled power dissipation of the external PNP transistor. The current is limited to IAUX_LIM and the regulator is switch OFF after a dedicated duration TAUX_LIM_OFF under current limitation. A SPI command is needed to restart the regulator. In order to limit the power dissipation in the external PNP transistor in case of short-circuit to GND of VAUX pin, a current limitation foldback scheme is implemented to reduce the current limitation to IAUX_LIM_FB when VAUX is below VAUX_LIM_FB. VAUX Vaux (3.3Vor 5V) Vaux_LIM_FB IAUX Iaux_LIM_FB Iaux_LIM Figure 40. VAUX Current Limitation Scheme With Foldback Mechanism 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 57 6.7.5.2 Voltage Monitoring The overvoltage detection switches OFF the regulator. The regulator remains ON in case of undervoltage detection. Diagnostic is reported in the dedicated register, generate an Interrupt and may bring the application in Fail-safe state depending on the supervisor configuration (registers INIT SUPERVISOR 1, 2, 3). 6.7.6 CAN_5V Voltage Regulator The CAN_5V voltage regulator is a linear regulator fully dedicated to the internal HSCAN interface. By default, the CAN_5V regulator and the undervoltage detector are enabled, the overvoltage detector is disabled. The overvoltage detector can be enabled by SPI during INIT_MAIN sate. If the overvoltage detector is enabled, the CAN_5V regulator switches OFF when an overvoltage is detected. The undervoltage detector is disabled when the regulator is switched OFF reporting an undervoltage. Diagnostic is reported in the dedicated register and generate an Interrupt. The CAN_5V regulator is not safety regulator. Consequently, the CAN_5V voltage monitoring (overvoltage, undervoltage) will never assert RSTB or FS0B Fail-safe pins. If the 33907/33908 internal CAN transceiver is not used in the application, the CAN_5V regulator can be used to supply an external standalone CAN or FLEX-RAY transceiver, providing that the current load remains below the maximum current capability in all conditions. In that case, the internal CAN transceiver must be put in Sleep mode without wake-up capability. 6.7.7 Power Dissipation The 33907/33908 provides high performance SMPS and Linear regulators to supply high end MCU in automotive applications. Each regulator can deliver: • VPRE (6. 5V) up to 2.0 A • VCORE (from 1.2 V to 3.3 V range) up to 0.8 A (33907) or up to 1.5 A (33908) • VCCA (3.3 V or 5.0 V) up to 100 mA (with internal MOS) or up to 300 mA (with external PNP) • VAUX (3.3 V or 5.0 V) up to 300 mA (with external PNP) • VCAN (5.0 V) up to 100 mA A thermal dissipation analysis has to be performed based on application use case to ensure the maximum silicon junction temperature does not exceed 150 °C. Two use cases covering the two main VCORE voltage configurations are provided in Figure 41. • use case 1: VCORE = 3.3 V, ICORE = 0.7 A, VCCA with int. MOS • use case 2: VCORE = 1.2 V, ICORE = 1.4 A, VCCA with ext. PNP Both use cases have a total internal power dissipation below 0.9 W. A junction to ambient thermal resistivity of 30 °C/W allows the application to work up to 125 °C ambient temperature. A good soldering of the package expose pad is highly recommended to achieve such thermal performance. 33907/33908 58 Analog Integrated Circuit Device Data Freescale Semiconductor Vsup = 14V and 25% of CAN traffic Main contributors to the IC's Power dissipation Main contributors to the IC's Power dissipation Vcca 21% Vcore 33% Vcore 51% Vpre 28% Vpre 25% Vcca 2% Vaux 5% Vaux 5% CAN transceiver 8% Internal IC 8% TOTAL PDIS = Internal IC 7% TOTAL PDIS 0.765 W use case 1: Vcore=3.3V, Icore=0.7A, Vcca with int. MOS = CAN transceiver 7% 0.829 W use case 2: Vcore=1.2V, Icore=1.4A, Vcca with ext. PNP 1) CAN transceiver dissipation includes CAN_5V regulator dissipation. 2) 25% CAN traffic means the CAN bus is dominant for 25% of time and recessive for the remaining 75%. Figure 41. Power Dissipation Use Case The main contributors to the device power dissipation are VPRE, VCORE, and VCCA (when used with internal PMOS) regulators. In comparison, the power dissipation from the Internal IC, VAUX and CAN transceiver are negligible. VPRE power dissipation is mainly induced by the loading of the regulators it is supplying, mainly VCORE, VCCA and VAUX which are application dependant. The total device power dissipation, depending on the variation of these three regulators, is detailed in Figure 42 with the environmental conditions in the associated table. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 59 Vcore Pdis VS Icore 6.5V Icore + Icca + Iaux + Ican 3.3V and 1.2V Pdis VS Icca 6.5V Icore + Icca + Iaux + Ican 3.3V Icore from 0.25 to 1.5A 0.7A 0.3A Vcca 3.3V 3.3V and 5V 3.3V 50mA Vpre Ipre Pdis VS Ipre 6.5V From 0.5 to 2A 3.3V Icca 50mA 20 to 100mA Vaux 3.3V 3.3V 3.3V Iaux 200mA 200mA 200mA CAN_5V 5V 5V 5V Ican 33mA 33mA 33mA Figure 42. Power Dissipation Versus ICORE, ICCA, or IPRE 33907/33908 60 Analog Integrated Circuit Device Data Freescale Semiconductor 6.7.8 Start-up Sequence In order to provide a safe and well known start-up sequence, the 33907/33908 includes an undervoltage lock-out. This undervoltage lockout is only applicable when the device is under a Power-On-Reset condition, which means the initial condition is VSUP < VSUP_UV_L (i.e. below 2.7 V max). In all the other conditions (i.e. LPOFF), the device is able to operate (and therefore to restart) down to VSUP_UV_L. The other different voltage rails automatically start, as described in Figure 43. Vsup_uv_5 Vsup Vint_2.5 LBIST 120us Vpre_EN Vpre_uv Vpre Vcca/Vaux Vcore INTB (Vddio=Vcore) 1ms 1ms INIT ABIST FS Select pin config Softstart Vregs Main Select pin config UV Lock-out Softstart Vpre RSTB LS detect Select pin ~16ms Figure 43. Start-up Scheme The final value of VAUX and VCCA depends on the hardware configuration (resistor values on the SELECT pin). The typical start up sequence takes around 16 ms to release RSTB. RSTB can be pulled low after those 16 ms by the MCU, if it is not ready to run after power up. If an internal or external fault happen during this start up phase (ABIST fault due to regulator shorted for example), the 8.0 s timer monitoring the RSTB pin low, will finally send the device in Deep Fail-safe mode after 8.0 s. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 61 6.8 CAN transceiver The high speed CAN (Controller Area Network) transceiver provides the physical interface between the CAN protocol controller of an MCU and the physical dual wires CAN bus. It offers excellent EMC and ESD performance and meets the ISO 11898-2 and ISO11898-5 standards. CAN_5V VDDIO TXD Bus Biasing CAN_5V Monitor Input Pre Driver Dominant time out 2.5V VDDIO CAN_5V Mode RXD Buffer and Rin CAN L Pre Driver Control Main Logic CAN H Rin VDDIO Over Temperature VSUP3 WU report to main loic Differential Receiver Wake-up Receiver Figure 44. CAN Simplified Block Diagram 6.8.1 Operating Modes 6.8.1.1 Normal Mode When CAN mode bits configuration is “11” (CAN in normal operation), the device is able to transmit information from TXD to the bus and report the bus level to the RXD pin. When TXD is high, CANH and CANL drivers are off and the bus is in the recessive state (unless it is in an application where another device drives the bus to the dominant state). When TXD is low, CANH and CANL drivers are ON and the bus is in the dominant state. When CAN mode bits configuration is “01” (CAN in listen only), the device is only able to report the bus level to the RXD pin. TXD driver is OFF and the device is NOT able to transmit information from TXD to the bus. TXD is maintained high by internal pull up resistor TXDPULL-UP connected to VDDIO. 33907/33908 62 Analog Integrated Circuit Device Data Freescale Semiconductor high TXD low CANH CANL dominant 0.9V Vdiff (CANH - CANL) 0.5V recessive high 0.7VDDIO RXD 0.3VDDIO low Tloop (R-D) Tloop (D-R) Figure 45. CAN Timing Diagram 6.8.1.2 Sleep Mode When the device is in LPOFF mode, the CAN transceiver is automatically set in Sleep mode with or without wake-up capability depending on CAN mode bits configuration. In that case, the CANH and CANL pins are pulled down to GND via the internal RIN resistor, the TXD and RXD pins are pulled down to GND, both driver and receiver are OFF. The CAN mode is automatically changed to Sleep with wake-up capability if not configured to Sleep without wake-up capability when the device enters is LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored (Figure 46). CAN state before entering LPOFF CAN_mode [1:0] CAN state in LPOFF CAN_mode CAN state [1:0] 0 Sleep, no wake-up capability 1 Listen Only 10 Sleep, wake-up capability 11 Normal 0 10 CAN state Sleep, no wake-up capability Sleep, wake-up capability CAN state after LPOFF CAN_mode [1:0] CAN state 0 Sleep, no wake-up capability 1 Listen Only 10 Sleep, wake-up capability 11 Normal Figure 46. CAN Transition When Device Goes to LPOFF 6.8.2 6.8.2.1 Fault Detection TXD Permanent Dominant (timeout) If TXD is set low for a time longer than TDOUT parameter, the CAN drivers are disabled, and the CAN bus will return to recessive state. The CAN receiver continues to operate. This prevent the bus to be set in dominant state permanently in case a failure set the TXD input to low level permanently. The CAN_mode MSB bit is set to 0 and the flag TXD_dominant is reported in the Diag CAN1 register. The device recovers from this error detection after setting the CAN_mode to Normal Operation and when a high level is detected on TXD. The TXD failure detection is operating when the CAN transceiver is in Normal mode and Listen only mode. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 63 recovery condition: TXD high high TXD low dominant recessive dominant dominant BUS TDOUT TDOUT TDOUT TXD dom time out expired RXD high low Figure 47. TXD Dominant Timeout Detection 6.8.2.2 RXD permanent recessive If RXD is detected high for seven consecutive receive/dominant cycles, the CAN drivers and receiver are disabled, and the CAN bus will return to recessive state. This prevent a CAN protocol controller to start CAN message on TXD pin, while RXD is shorted to a recessive level, and seen from a CAN controller as a bus idle state. The CAN_mode MSB bit is set to 0 and the flag RXD_recessive is reported in the Diag CAN1 register. The device recovers from this error detection after setting the CAN_mode to Normal Operation. The RXD failure detection is operating when the CAN transceiver is in Normal mode and Listen only mode. 6.8.2.3 CAN Bus Short-circuits CANL short to GND and CANL short to Battery are detected and reported to the device main logic. The CAN driver and receiver are not be disabled. CANH short to GND and CANH short to Battery are detected and reported to the device main logic. The CAN driver and receiver are not be disabled. The CANH and CANL failure detection is operating when the CAN transceiver is in Normal mode. If the CAN bus is dominant for a time longer than TDOM, due for instance to an external short-circuit from another CAN node, the flag CAN_dominant is reported in the Diag CAN1 register. This failure does not disable the bus driver. The CAN bus dominant failure detection is operating when the CAN transceiver is in Normal mode and Listen Only mode. 6.8.2.4 CAN current limitation The current flowing in and out of the CANH and CANL driver is limited to 100 mA, in case of short-circuit (parameters ICANL-SK and ICANH-SC). 6.8.2.5 CAN Overtemperature If the driver temperature exceeds the TSD (TOT), the CAN drivers are disabled, and the CAN bus will return to recessive state. The CAN receiver continues to operate. The CAN_mode MSB bit is set to 0 and the flag CAN_OT is reported in the Diag CAN_LIN register. An hysteresis is implemented in this protection feature. The device overtemperature and recovery conditions are shown in Figure 48. The CAN drivers remain disabled until the temperature has fallen below the OT threshold minus hysteresis. The device will recover from this error detection after setting the CAN_mode to Normal Operation and when a high level is detected on TXD. 33907/33908 64 Analog Integrated Circuit Device Data Freescale Semiconductor Overtemperature Threshold Temperature Hysteresis Hysteresis Event 1 Event 1 Event 2 Event 2 Event 4 Event 3 TXD Event 3 high low recessive dominant dominant dominant BUS Event 1: over temperature detection. CAN driver disable. Event 2: temperature falls below “overtemp. threshold minus hysteresis” => CAN driver remains disable. Event 3: temperature below “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver enable. Event 4: temperature above “overtemp. threshold minus hysteresis” and TxD high to low transition => CAN driver remains disable. Figure 48. Overtemperature Behavior 6.8.2.6 Distinguish CAN diagnostics and CAN errors The CAN errors can generate an interruption while the CAN diagnostics are reported in the digital for information only. The interruption generated by the CAN errors can be inhibited setting INT_inh_CAN bit at “1” in the “INIT INT” register. The list of CAN Diagnostic and CAN Error bits is provided in Table 11. Table 11. CAN Diagnostic and CAN Error Bits Register DIAG CAN1 DIAG CAN_LIN 6.8.3 Bit Flag Type Effect CANH_batt Diagnostic No impact on CAN transceiver CANH_gnd Diagnostic No impact on CAN transceiver CANL_batt Diagnostic No impact on CAN transceiver CANL_gnd Diagnostic No impact on CAN transceiver CAN_dominant Error Turn OFF CAN transceiver RXD_recessive Error Turn OFF CAN transceiver TXD_dominant Error Turn OFF CAN transceiver CAN_OT Error Turn OFF CAN transceiver CAN_OC Diagnostic No impact on CAN transceiver Wake-up Mechanism The device include bus monitoring circuitry to detect and report bus wake-ups when the device is in LPOFF and CAN mode configuration is different than Sleep/NO wake-up capability. Two wake-up detection are implemented: single dominant pulse and multiple dominants pulses. The wake-up mechanism is selected by SPI in the main logic and wake-up events are reported. The event must occur within the T3PTOX timeout. T3PTOX = T3PTO1 or T3PTO2 depending on the SPI selection. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 65 6.8.3.1 Single Pulse Detection In order to activate wake-up report, 1 event must occur on the CAN bus: - event 1: a dominant level for a time longer that T1PWU Figure 49. Single Pulse Wake-up Pattern Illustration 6.8.3.2 Multiple Pulse Detection In order to activate wake-up report, three events must occur on the CAN bus: - event 1: a dominant level for a time longer that t1PWU followed by - event 2: a recessive level (event 2) longer than t3PWU followed by - event 3: a dominant level (event 3) longer than t3PWU. The three events and the timeout function avoid that a permanent dominant state on the bus generates permanent wake-up situation which would prevent system to enter in low-power mode. Figure 50. Multiple Pulse Wake-up Pattern Illustration 33907/33908 66 Analog Integrated Circuit Device Data Freescale Semiconductor 6.9 LIN Transceiver This chapter applies to 33907L and 33908L versions. The Local Interconnect Network (LIN) is a serial communication protocol, designed to support automotive networks in conjunction with a Controller Area Network (CAN). The LIN transceiver is operational from a VSUP of 7.0 V to 18 V DC and compatible with LIN Protocol Specification 1.3, 2.0, 2.1, 2.2 and SAEJ2602-2. 6.9.1 Simplified Block Diagram LIN Wake up LIN overtemperature LIN transmitter and receiver Enabled LIN transmitter in Recessive State VSUP3 Normal Baud Rate (20kbps) Slow Baud Rate (10kbps) Fast Baud Rate (100kbps) SR_control Sleep_mode VSUP Undervoltage LIN transmitter in Recessive State TXD Dominant LIN transmitter in Recessive State LIN Interface 30 k 725 k LIN LIN Driver X1 35µA TXD GND RXD Receiver Figure 51. LIN simplified block diagram 6.9.2 6.9.2.1 Operating Modes Normal Mode When LIN mode bits configuration is “11” (LIN in normal operation), the device is able to transmit information from TXDL to the bus and report the bus level to the RXDL pin. When TXDL is high, LIN driver is OFF and the bus is in the recessive state (unless it is in an application where another device drives the bus to the dominant state). When TXDL is low, LIN driver is ON and the bus is in the dominant state. When LIN mode bits configuration is “01” (LIN in listen only), the device is only able to report the bus level to the RXDL pin. TXDL driver is OFF and the device is NOT able to transmit information from TXDL to the bus. TXDL is maintained high by internal pull-up resistor TXDLPULL-UP connected to VDDIO. 6.9.2.2 Sleep Mode When the device is in LPOFF mode, the LIN transceiver is automatically set in Sleep mode with or without wake-up capability depending on LIN mode bits configuration. In that case, the LIN pin is pulled up to VSUP via the internal resistor and diode structure, the TXDL and RXDL pins are pulled down to GND. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 67 6.9.3 Baud Rate Selection The device has two selectable baud rates: 20 kB/s for Normal Baud rate and 10 kB/s for slow baud rate. An additional fast baud rate (100 kB/s) can be used to flash the MCU or in the garage for diagnostic. The LIN Consortium specification does not specified electrical parameters for this baud rate. The communication only is guaranteed. The baud rate selection is done by SPI setting during the INIT phase of the main logic. Depending of the baud rate setting, the corresponding LIN slope control is automatically selected. Figure 52. LIN timings for Normal Baud rate (20kB/s) Figure 53. LIN Timings for Slow Baud Rate (10 kB/s) 33907/33908 68 Analog Integrated Circuit Device Data Freescale Semiconductor Figure 54. LIN Receiver Timings 6.9.4 6.9.4.1 Fault Detection VSUP Undervoltage A VSUP undervoltage (VLIN_UV) detection is implemented to be compliant with SAEJ2602-2 standard. At low VSUP voltage (VSUP<VLIN_UV), the LIN bus goes in recessive state to avoid wrong communication. 6.9.4.2 TXDL Permanent Dominant (timeout) If TXDL is set low for a time longer than tXD_DOM parameter, the LIN driver is disabled and the LIN bus will return to recessive state. This prevents the bus to be set in dominant state permanently, in case a failure sets the TXDL input permanently to a low level. The LIN receiver continues to operate. The LIN_mode MSB bit is set to 0 and the flag TXDL_dominant is reported in the Diag CAN_LIN register. The device recovers from this error detection after setting the LIN_mode to normal operation and when a high level is detected on TXDL. The TXDL failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode. 6.9.4.3 RXDL Permanent Recessive If RXDL is detected high for seven consecutive receive/dominant cycles, the LIN driver and receiver are disabled and the LIN bus returns to recessive state. The LIN_mode MSB bit is set to 0 and the flag RXDL_recessive is reported in the Diag CAN_LIN register. The device recovers from this error detection after setting the LIN_mode to normal operation, and when a high level is detected on TXDL. The RXDL failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode. 6.9.4.4 LIN Bus Short-circuit If the LIN bus is dominant for a time longer than tLIN_SHORT_GND, due for instance to an external short-circuit to GND, the detection is reported to the device main logic. The BUS bus failure detection is operating when the LIN transceiver is in Normal mode and Listen Only mode. 6.9.4.5 LIN Current Limitation In case of LIN short-circuit to Battery, the current flowing out of the LIN driver is limited to 200 mA (parameter IBUS_LIM), and the LIN driver is not shut down. The LIN bus goes in recessive state when the current limitation occurs and returns in the same functional mode as before failure when the current falls below the current limitation value. 6.9.4.6 LIN Overtemperature If the driver temperature exceeds the TSD (tLIN_SD), the LIN driver is disabled and the LIN bus will return to recessive state. The LIN receiver continues to operate. The LIN_mode MSB bit is set to 0 and the flag LIN_OT is reported in the Diag CAN_LIN register. 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 69 A hysteresis is implemented in this protection feature. The LIN driver remain disabled until the temperature has fallen below the OT threshold minus hysteresis. The device recovers from this error detection after setting the LIN_mode to normal operation, and when a high level is detected on TXDL. 6.9.4.7 LIN errors The interruption generated by the LIN errors can be inhibited setting INT_inh_LIN bit at “1” in the “INIT INT” register. The list of LIN error bits is provided in Table 12. Table 12. LIN Error Bits Register DIAG CAN_LIN 6.9.5 Bit Flag Type Effect LIN_dominant Error Turn OFF LIN transceiver RXDL_recessive Error Turn OFF LIN transceiver TXDL_dominant Error Turn OFF LIN transceiver LIN_OT Error Turn OFF LIN transceiver Wake-up mechanism The device can wake-up by a LIN dominant pulse longer than tBUS_WU. Dominant pulse means: a recessive to dominant transition, wait for t > tBUS_WU, then a dominant to recessive transition. VLIN_REC VLIN_REC VBUS_WU VLIN_DOM TBUS_WU LIN Wake up validation Figure 55. LIN Wake-up Pattern Illustration 33907/33908 70 Analog Integrated Circuit Device Data Freescale Semiconductor 7 Serial Peripheral Interface 7.1 High Level Overview 7.1.1 SPI The device is using a 16 bits SPI, with the following arrangement: MOSI, Master Out Slave In bits: • Bit 15 read/write • Bit 14 Main or fail-safe register target • bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, Next bit (=0) in read mode. • bit7 to 0 (D7 to D0): control bits MISO, Master IN Slave Out bits: • bits 15 to 8 (S15 to S8) are device status bits • bits 7 to 0(Do7 to Do0) are either extended device status bits, device internal control register content or device flags. Figure 56 is an overview of the SPI implementation. 7.1.2 Parity Bit 8 Calculation The parity is used for write to register command (bit 15,14 = 01). It is calculated based on the number of logic ones contained in bits 15-9, 7-0 sequence (this is the whole 16-bits of the write command except bit 8). Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1 if the number of 1 is even. 7.1.3 Device Status on MISO When a write operation is performed to store data or control bit into the device, MISO pin reports a 16-bit fixed device status composed of two bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO reports the fixed device status (bits 15 to 8), and the next eight bits are content of the selected register. A standard serial peripheral interface (SPI) is integrated to allow bi-directional communication between the 33907/33908 and the MCU. The SPI is used for configuration and diagnostic purposes. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 MOSI R/W M/FS A4 A3 A2 A1 A0 register address MISO S15 S14 S13 S12 S11 S10 Bit 8 Bit 7 Bit 6 P D7 Bit 5 D6 D5 Parity S9 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D4 D2 D1 D0 Do2 Do1 Do0 D3 data S8 Do7 Do6 Do5 Do4 Do3 Extended Device Status, Register Control bits or Device Flags Device Status CSb CSb active low. Must be raised at end of 16 clocks, for write commands, MOSI bits [15] = [1]. SCLK SCLK signal is low outside of CSB active MOSI Don’t care MISO Tri state C1 S15 C0 D0 S14 Do0 Don’t care Tri state MOSI and MISO data changed at SCLK rising edge and sampled at falling edge. Msb first. MISO tri state outside of CSB active SPI wave form, and signals polarity Figure 56. SPI Overview 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 71 The device contains several registers. Their address is coded on 7 bits (bits 15 to 9). Each register controls or reports part of the device function. Data can be written to the register, to control the device operation or set default value or behavior. Every register can also be read back in order to ensure that its content (default setting or value previously written) is correct. 7.1.4 Register Description Although the minimum time between two NCS low sequences is defined by tONNCS (Figure 57), two consecutive accesses to the fail-safe registers must be done with a 3.5 µs minimum NCS high time in between. Although the minimum time between two fail-safe registers accesses is 3.5 µs, some SPI accesses to the main registers can be done in between (Figure 57). 7.2 Detail Operation Figure 57. MOSI / MISO SPI Command Organization Table 13. MOSI Bits Description Description R/W 0 READ 1 WRITE Description M / FS Main 1 Fail-safe 0 1 Description P Set the address to Read or Write See Register Mapping Parity bit (only use in Write mode). Set to 0 in Read mode 0 Number of “1” (bit15:9 and bit 7:0) is odd 1 Number of “1” (bit15:9) and bit 7:0) is even Description D7:0 Split the addresses between Fail-safe State machine and main Logic 0 Description A4:0 Set if it is a READ or WRITE Command 0 1 Data in Write mode. Shall be set to 00h in Read mode See Register Details 33907/33908 72 Analog Integrated Circuit Device Data Freescale Semiconductor Table 14. MISO Bits Description Description SPI_G 0 No Failure 1 Failure Reset Condition Description WU 1 WU event 1 CAN event Report a LIN event (diagnostic) No event 1 LIN event Description Power On Reset / When initial event cleared on read Report a change in IOs state 0 No IO transition 1 IO transition Reset Condition Description Power On Reset / when initial event cleared on read Report an event from VPRE-REGULATOR and battery monitoring (status change or failure) 0 No event 1 Event occurred Reset Condition Description Power On Reset / when initial event cleared on read Report an event from VCORE regulator (status change or failure) 0 No event 1 Event occurred Reset Condition Description VOTHERS_G Power On Reset / When initial event cleared on read 0 Reset Condition VCORE_G Report a CAN event (Diagnostic) No event Description VPRE_G Power On Reset / When initial event cleared on read 0 Reset Condition IO_G Report a wake-up event. Logical OR of all wake-up sources No WU event Description LIN_G Power On Reset / When initial event cleared on read 0 Reset Condition CAN_G Report an error in the SPI communication Power On Reset / when initial event cleared on read Report an event from VCCA, VAUX, or VCAN regulators (status change or failure) 0 No event 1 Event occurred Reset Condition Power On Reset / when initial event cleared on read SPI_G = SPI_err or SPI_clk or SPI_Req or SPI_Parity or SPI_FS_err or SPI_FS_clk or SPI_FS_Req or SPI_FS_Parity WU_G = IO_5_WU or IO_4_WU or IO_3_WU or IO_2_WU or IO_1_WU or IO_0_WU or PHY_WU CAN_G = CANH_BATT or CANH_GND or CANL_BATT or CANL_GND or CAN_dominant or RXD_recessive or TXD_dominant or CAN_OT or CAN_OC LIN_G = LIN_OT or RXDL_recessive or TXDL_dominant or LIN_dominant IO_G = IO_5 or IO_4 or IO_3 or IO_2 or IO_1 or IO_0 Vpre_G = VSNS_UV or VSUP_UV_7 or IPFF or ILIM_PRE or TWARN_PRE or BOB or VPRE_STATE_flag or VPRE_OV or VPRE_UV Vcore_G = ILIM_CORE or TWARN_CORE or VCORE_STATE_flag or VCORE_OV or VCORE_UV Vothers_G = ILIM_CCA or TWARN_CCA or TSD_CCA or ILIM_CCA_OFF or VCCA_UV or VCCA_OV or ILIM_AUX or VAUX_TSD or ILIM_AUX_OFF or VAUX_OV or VAUX_UV or ILIM_CAN or VCAN_UV or VCAN_OV or TSD_CAN 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 73 7.2.1 Register Address Table Table 15 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Table 15. Register Mapping of Main Logic Register Address Write description Table Ref #0(00h) N/A N/A 1 #1(01h) Write during INIT phase then read only Table 18 1 0 #2(02h) Write during INIT phase then read only Table 20 0 1 1 #3(03h) Write during INIT phase then read only Table 22 0 1 0 0 #4(04h) Write during INIT phase then read only Table 24 0 0 1 0 1 #5(05h) Write during INIT phase then read only Table 26 0 0 0 1 1 0 #6(06h) Write during INIT phase then read only Table 28 NOT USED 0 0 0 1 1 1 #7(07h) N/A N/A HW Config 0 0 1 0 0 0 #8(08h) Read only Table 30 WU Source 0 0 1 0 0 1 #9(09h) Read only Table 32 NOT USED 0 0 1 0 1 0 #10(0Ah) N/A N/A IO_input 0 0 1 0 1 1 #11(0Bh) Read only Table 34 Status Vreg#1 0 0 1 1 0 0 #12(0Ch) Read only Table 36 Status Vreg#2 0 0 1 1 0 1 #13(0Dh) Read only Table 38 Diag Vreg#1 0 0 1 1 1 0 #14(0Eh) Read only Table 40 Diag Vreg#2 0 0 1 1 1 1 #15(0Fh) Read only Table 42 Diag Vreg#3 0 1 0 0 0 0 #16(10h) Read only Table 44 Diag CAN1 0 1 0 0 0 1 #17(11h) Read only Table 46 Diag CAN_LIN 0 1 0 0 1 0 #18(12h) Read only Table 48 Diag SPI 0 1 0 0 1 1 #19(13h) Read only Table 50 NOT USED 0 1 0 1 0 0 #20(14h) N/A N/A MODE 0 1 0 1 0 1 #21(15h) Write during Normal and Read Table 52 Vreg Mode 0 1 0 1 1 0 #22(16h) Write during Normal and Read Table 54 IO_OUT/AMUX 0 1 0 1 1 1 #23(17h) Write during Normal and Read Table 56 CAN_LIN Mode 0 1 1 0 0 0 #24(18h) Write during Normal and Read Table 58 CAN Mode 2 0 1 1 0 0 1 #25(19h) Write during Normal and Read Table 60 FS/M A4 A3 A2 A1 A0 Hex NOT USED 0 0 0 0 0 0 INIT Vreg 1 0 0 0 0 0 INIT Vreg2 0 0 0 0 INIT CAN_LIN 0 0 0 INIT IO_WU1 0 0 INIT IO_WU2 0 INIT INT Table 16 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for fail-safe logic Table 16. Register Mapping of Fail-safe Logic Register Address Write description Table Ref #33(21h) Write during INIT phase then Read only Table 62 0 #34(22h) Write during INIT phase then Read only Table 64 1 1 #35(23h) Write during INIT phase then Read only Table 66 0 0 #36(24h) Write during INIT phase then Read only Table 68 FS/M A4 A3 A2 A1 A0 Hex INIT Supervisor#1 1 0 0 0 0 1 INIT Supervisor#2 1 0 0 0 1 INIT Supervisor#3 1 0 0 0 INIT FSSM#1 1 0 0 1 33907/33908 74 Analog Integrated Circuit Device Data Freescale Semiconductor Table 16. Register Mapping of Fail-safe Logic (continued) Address Register Write description Table Ref #37(25h) Write during INIT phase then Read only Table 70 0 #38(26h) Write (No restriction) and Read Table 72 1 1 #39(27h) Write (No restriction) and Read Table 74 0 0 0 #40(28h) Write (No restriction) and Read Table 76 1 0 0 1 #41(29h) Write (No restriction) Table 78 0 1 0 1 0 #42(2Ah) Write (No restriction) Table 80 1 0 1 0 1 1 #43(2Bh) Write during INIT phase then Read only Table 82 Diag FS1 1 0 1 1 0 0 #44(2Ch) Read only Table 84 WD_Counter 1 0 1 1 0 1 #45(2Dh) Read only Table 86 Diag_FS2 1 0 1 1 1 0 #46(2Eh) Read only Table 88 FS/M A4 A3 A2 A1 A0 Hex INIT FSSM#2 1 0 0 1 0 1 WD_Window 1 0 0 1 1 WD_LFSR 1 0 0 1 WD_answer 1 0 1 FS_OUT 1 0 RSTb request 1 INIT WD 7.2.2 Secured SPI Command Some SPI commands must be secured to avoid unwanted change of the critical bits. In the fail-safe machine and in the main state machine, the secured bits are calculated from the data bits sent as follows: Table 17. Secured SPI Bit7 Data 3 • • • • Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data 2 Data 1 Data 0 Secure 3 Secure2 Secure 1 Secure 0 Secure 3 = NOT(Bit5) Secure 2 = NOT(Bit4) Secure 1 = Bit7 Secure 0 = Bit6 7.3 Detail of Register Mapping 7.3.1 Init VREG 1 Table 18. INIT VREG1 Register Configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 0 0 1 P 0 0 Ipff_DIS 0 0 0 0 Vcore_ FB MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 0 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reserve Reserve Ipff_DIS d d Reserve Vcore_F d B Read MOSI 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 75 Table 18. INIT VREG1 Register Configuration MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 Reserve Reserve Ipff_DIS d d 0 0 Reserve Vcore_F d B Table 19. Description and Configuration of the Bits (Default value in bold) Description IPFF_DIS DISABLE the input Power Feed Forward (IPFF) function of VPRE 0 ENABLED 1 DISABLED Reset condition Power On Reset Configure the monitoring of the second VCORE resistor string Description Vcore_FB 0 No Monitoring (IO_1 is used as analog & digital input) 1 Monitoring enabled (IO_1 can NOT be used for analog/digital input neither for WU from LPOFF) Reset condition 7.3.2 Power On Reset Init Vreg 2 Table 20. INIT VREG2 Register Configuration Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 0 1 0 P 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Vaux_tr k_EN 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Vaux_tr reserved k_EN bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 Tcca_li m_off Icca_lim 0 0 Taux_li m_off Read Vaux_tr reserved k_EN Table 21. INIT VREG2. Description and Configuration of the Bits (Default value in bold) Description TCCA_LIM_OFF 0 10 ms 1 50 ms Reset condition Description ICCA_LIM Configure the current limitation duration before regulator is switched off. Only used for external PNP Power On Reset Configure the current limitation threshold. Only available for external PNP 0 ICCA_LIM_OUT 1 ICCA_LIM_INT Reset condition Power On Reset 33907/33908 76 Analog Integrated Circuit Device Data Freescale Semiconductor Table 21. INIT VREG2. Description and Configuration of the Bits (Default value in bold)(continued) Description TAUX_LIM_OFF Configure the current limitation duration before regulator is switched off. Only used for external PNP 0 10 ms 1 50 ms Reset condition Description Configure VAUX regulator as a tracker 0 No tracking. HW configuration is used 1 Tracking enabled Reset condition Power On Reset VAUX_TRK_EN 7.3.3 Power On Reset Init CAN_LIN Table 22. INIT CAN_LIN Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 0 1 1 P 0 CAN_w u_conf 0 0 CAN_w u_TO 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 CAN_w Reserve Reserve CAN_w u_conf d d u_TO bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G Vothers _G 0 LIN_SR LIN_SR _1 _0 Reserve LIN_SR LIN_SR d _1 _0 Read CAN_w Reserve Reserve CAN_w u_conf d d u_TO Reserve LIN_SR LIN_SR d _1 _0 Table 23. INIT CAN_LIN. Description and Configuration of the Bits (Default value in bold) Description CAN_wu_conf 0 3 dominant pulses 1 Single dominant pulse Reset condition Description CAN_wu_to Power On Reset Define the CAN wake-up timeout (in case of CAN_wu_conf = 0) 0 120 µs 1 360 µs Reset condition Description LIN_SR_1:0 Define the CAN wake-up mechanism Power On Reset Configure the LIN slew rate 00 20 kbits/s 01 10 kbits/s 1X Fast baud rate (Max: 100 kbits/s) Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 77 7.3.4 INIT IO_WU1 Table 24. INIT IO_WU1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 0 0 1 0 0 P MISO SPI_G WU CAN_G LIN_G IO_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 INT_inh _IO_1 INT_inh _IO_0 Vothers INT_inh WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU-2-1 WU_2_0 _G _IO_1 INT_inh _IO_0 WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU_2_1 WU_2_0 Read Vpre_G Vcore_G Vothers INT_inh WU_0_1 WU_0_0 WU_1_1 WU_1_0 WU-2-1 WU_2_0 _G _IO_1 INT_inh _IO_0 Table 25. INIT IO_WU1. Description and Configuration of the Bits (Default value in bold) Description WU_0_1:0 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Description WU_1_1:0 Wake-up configuration for IO_1 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Description Power On Reset Wake-up configuration for IO_2 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Description INT_inh_IO_1 Power On Reset 00 Reset condition WU_2_1:0 Wake-up configuration for IO_0 Power On Reset Inhibit the INT pulse for IO_1. IO_1 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Power On Reset 33907/33908 78 Analog Integrated Circuit Device Data Freescale Semiconductor Table 25. INIT IO_WU1. Description and Configuration of the Bits (Default value in bold) (continued) Description INT_inh_IO_0 Inhibit the INT pulse for IO_0. IO_0 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition 7.3.5 Power On Reset INIT IO_WU2 Table 26. INIT IO_WU2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 MOSI 1 0 0 0 1 0 1 P MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0 bit1 bit0 INT_inh INT_inh _IO_23 _IO_45 Vothers INT_inh INT_inh WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0 _G _IO_23 _IO_45 Read Vothers INT_inh INT_inh WU_3_1 WU_3_0 WU_4_1 WU_4_0 WU_5_1 WU_5_0 _G _IO_23 _IO_45 Table 27. INIT IO_WU2. Description and Configuration of the Bits (Default value in bold) Description WU_3_1:0 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Description WU_4_1:0 Wake-up configuration for IO_3 Power On Reset Wake-up configuration for IO_4 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 79 Table 27. INIT IO_WU2. Description and Configuration of the Bits (Default value in bold) (continued) Description WU_5_1:0 Wake-up configuration for IO_5 00 NO wake-up capability 01 Wake-up on rising edge only 10 Wake-up on falling edge only 11 Wake-up on any edge Reset condition Description INT_inh_IO_45 Inhibit the INT pulse for IO_4 & IO_5. IO_4 & IO_5 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition Description INT_inh_IO_23 Power On Reset Inhibit the INT pulse for IO_2 & IO_3. IO_2 & IO_3 masked in IO_G. Avoid INT when used in FS 0 INT NOT masked 1 INT masked Reset condition 7.3.6 Power On Reset Power On Reset INIT INT Table 28. INIT INT Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 1 1 0 P MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ G INT_inh INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh INT_inh _Vother ation _LIN _all _Vsns _Vpre _Vcore _CAN s INT_inh Vothers INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh INT_inh _Vother _G ation _LIN _all _Vsns _Vpre _Vcore _CAN s Read INT_inh Vothers INT_dur INT_inh INT_inh INT_inh INT_inh INT_inh INT_inh _Vother _G ation _LIN _all _Vsns _Vpre _Vcore _CAN s Table 29. INIT INT. Description and Configuration of the Bits (Default value in bold) Description INT_duration Define the duration of the INTerrupt pulse 0 100 µs 1 25 µs Reset condition Power On Reset 33907/33908 80 Analog Integrated Circuit Device Data Freescale Semiconductor Table 29. INIT INT. Description and Configuration of the Bits (Default value in bold) (continued) Description INT_inh_LIN Inhibit the INT for LIN error bits 0 All INT sources 1 LIN error bits changed INHIBITED Reset condition Description INT_inh_all Inhibit ALL the INT 0 All INT sources 1 All INT INHIBITED Reset condition Description INT_inh_Vsns 0 All INT sources 1 VSNS_UV INT INHIBITED 0 All INT sources 1 VPRE status changed INHIBITED Reset condition 0 All INT sources 1 VCORE status changed INHIBITED Reset condition Description 0 All INT sources 1 VCCA / VAUX / VCAN status changed INHIBITED Description Power On Reset Inhibit the INT for CAN error bits 0 All INT sources 1 CAN error bits changed INHIBITED Reset condition 7.3.7 Power On Reset Inhibit the INT for VCCA / VAUX and VCAN status event (cf. register status Vreg2) Reset condition INT_inh_CAN Power On Reset Inhibit the INT for VCORE status event (cf. register status Vreg2) Description INT_inh_Vothers Power On Reset Inhibit the INT for VPRE status event (cf. register status Vreg1) Description INT_inh_Vcore Power On Reset Inhibit the INT for VSNS_UV Reset condition INT_inh_Vpre Power On Reset Power On Reset HW Config Table 30. HW Config Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vaux_ HW 1 0 DBG Vpre_ Vcore_ Vother LS_det G G s_G ect Vaux not used Vcca_ Vcca_ PNP_d HW etect 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 81 Table 31. HW Config. Description and Configuration of the Bits (Default value in bold) Report the hardware configuration of VPRE (Buck only or Buck-Boost) Description LS_detect 0 Buck-Boost 1 Buck only Reset condition Report if VAUX is used Description VAUX not used 0 VAUX is used (external PNP is assumed to be connected, VAUX can be switched OFF/ON through SPI) 1 VAUX is not used Reset condition Description VCCA_PNP_DETECT 0 External PNP connected 1 Internal MOSFET Description 0 3.3 V 1 5.0 V Description 0 5.0 V 1 3.3 V Description Power On Reset / Refresh after LPOFF Report the configuration of the DEBUG mode 0 Normal operation 1 DEBUG mode selected Reset condition 7.3.8 Power On Reset / Refresh after LPOFF Report the hardware configuration for VAUX Reset condition DBG Power On Reset / Refresh after LPOFF Report the hardware configuration for VCCA Reset condition VAUX_HW Power On Reset / Refresh after LPOFF Report the connection of an external PNP on VCCA Reset condition VCCA_HW Power On Reset / Refresh after LPOFF Power On Reset / Refresh after LPOFF WU Source Table 32. WU Source Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G IO_5_ WU IO_4_ WU IO_3_ WU IO_2_ WU IO_1_ WU IO_0_ WU 0 Phy_W U Vpre_ Vcore_ Vother G G s_G Table 33. WU Source. Description and Configuration of the Bits (Default value in bold) Description IO_5_WU Report a wake-up event from IO_5 0 No Wake-up 1 WU event detected Reset condition Power On Reset / Read 33907/33908 82 Analog Integrated Circuit Device Data Freescale Semiconductor Table 33. WU Source. Description and Configuration of the Bits (Default value in bold)(continued) Description IO_4_WU Report a wake-up event from IO_4 0 No Wake-up 1 WU event detected Reset condition Description IO_3_WU Report a wake-up event from IO_3 0 No Wake-up 1 WU event detected Reset condition Description IO_2_WU 0 No Wake-up 1 WU event detected Description 0 No Wake-up 1 WU event detected Description 0 No Wake-up 1 WU event detected Description Power On Reset / Read Report a wake-up event from CAN or LIN 0 No Wake-up 1 WU event detected Reset condition 7.3.9 Power On Reset / Read Report a wake-up event from IO_0 Reset condition Phy_WU Power On Reset / Read Report a wake-up event from IO_1 Reset condition IO_0_WU Power On Reset / Read Report a wake-up event from IO_2 Reset condition IO_1_WU Power On Reset / Read Power On Reset / Read CAN_wu or/and LIN_wu IO Input Table 34. IO Input Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G IO_5 IO_4 0 IO_3 IO_2 0 IO_1 IO_0 Vpre_ Vcore_ Vother G G s_G Table 35. IO Input. Description and Configuration of the Bits Description IO_5 Report IO_5 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 83 Table 35. IO Input. Description and Configuration of the Bits(continued) Description IO_4 Report IO_4 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Description IO_3 Report IO_3 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Description IO_2 0 Low 1 High Description Power On Reset Report IO_1 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Description IO_0 Power On Reset Report IO_2 digital state in Normal mode. No update in LPOFF mode since wake-up features available Reset condition IO_1 Power On Reset Power On Reset Report IO_0 digital state in Normal mode. No update in LPOFF mode since wake-up features available 0 Low 1 High Reset condition Power On Reset 7.3.10 Status Vreg1 Table 36. STATUS VREG1 Register Description Read bit15 bit14 bit13 bit12 bit11 MOSI 0 0 MISO SPI_ G WU 0 1 1 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 0 0 0 IpFF Ilim_pre 0 0 0 CAN_ LIN_ Vpre_ Vcore_ Vothers_ IO_G G G G G G Twarn_pr Vpre_stat BoB e e Table 37. Status Vreg1. Description and Configuration of the Bits (Default value in bold) Description IPFF 0 Normal Operation 1 Ipff mode activated Reset condition Description ILIM_PRE Input Power Feed Forward Power On Reset / Read Report a current limitation condition on VPRE 0 No current limitation (IPRE_PK < IPRE_LIM) 1 Current limitation (IPRE_PK > IPRE_LIM) Reset condition Power On Reset / Read 33907/33908 84 Analog Integrated Circuit Device Data Freescale Semiconductor Table 37. Status Vreg1. Description and Configuration of the Bits (Default value in bold)(continued) Description TWARN_PRE Report a thermal warning from VPRE 0 No thermal warning (TJ < TWARN_PRE) 1 Thermal warning (TJ > TWARN_PRE) Reset condition Description BoB Report a running mode of VPRE 0 Buck 1 Boost Reset condition Description VPRE_STATE Power On Reset / Read Power On Reset Report the activation state of VPRE SMPS 0 SMPS OFF 1 SMPS ON Reset condition Power On Reset 7.3.11 Status VREG2 Table 38. STATUS VREG2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ Vcore_ Vother Ilim_co Twarn_ Vcore_ Twarn_ Ilim_cc Ilim_au Ilim_ca G G s_G re core state cca a x n 0 Table 39. Status Vreg2. Description and Configuration of the Bits (Default value in bold) ILIM_CORE Description Report a current limitation condition on VCORE 0 No current limitation (ICORE_PK < ICORE_LIM) 1 Current limitation (ICORE_PK > ICORE_LIM) Reset condition Description TWARN_CORE No thermal warning (TJ < TWARN_CORE) 1 Thermal warning (TJ > TWARN_CORE) Description Power On Reset / Read Report the activation state of VCORE SMPS 0 SMPS OFF 1 SMPS ON Reset condition Description TWARN_CCA Report a thermal warning from VCORE 0 Reset condition VCORE_STATE Power On Reset / Read Power On Reset Report a thermal warning from VCCA. Available only for internal pass MOSFET 0 No thermal warning (TJ < TWARN_CCA) 1 Thermal warning (TJ > TWARN_CCA) Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 85 Table 39. Status Vreg2. Description and Configuration of the Bits (Default value in bold)(continued) Description ILIM_CCA Report a current limitation condition on VCCA 0 No current limitation (ICCA < ICCA_LIM) 1 Current limitation (ICCA > ICCA_LIM) Reset condition Description ILIM_AUX Report a current limitation condition on VAUX 0 No current limitation (IAUX < IAUX_LIM) 1 Current limitation (IAUX > IAUX_LIM) Reset condition Description ILIM_CAN Power On Reset / Read Power On Reset / Read Report a current limitation condition on VCAN 0 No current limitation (ICAN < ICAN_LIM) 1 Current limitation (ICAN > ICAN _LIM) Reset condition Power On Reset / Read 7.3.12 Diag Vreg1 Table 40. DIAG VREG1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ Vcore_ Vother Vsns_u Vsup_u Tsd_pr G G s_G v v_7 e Vpre_ Vpre_u Tsd_co Vcore_ Vcore_ OV v re FB_OV FB_uv Table 41. Diag Vreg1. Description and Configuration of the Bits (Default value in bold) Description VSNS_UV 0 VBAT > VSNS_UV 1 VBAT < VSNS_UV Reset condition Description VSUP_UV_7 Detection of VSUP below VSUP_UV_7 VSUP > VSUP_UV_7 1 VSUP < VSUP_UV_7 Description Power On Reset / Read Thermal shutdown of VPRE 0 No TSD (TJ < TSD_PRE) 1 TSD occurred (TJ > TSD_PRE) Reset condition Description VPRE_OV Power On Reset / Read 0 Reset condition TSD_PRE Detection of VBATTERY below VSNS_UV Power On Reset / Read VPRE overvoltage detection 0 No overvoltage (VPRE < VPRE_OV) 1 Overvoltage detected (VPRE > VPRE_OV) Reset condition Power On Reset 33907/33908 86 Analog Integrated Circuit Device Data Freescale Semiconductor Table 41. Diag Vreg1. Description and Configuration of the Bits (Default value in bold) (continued) Description VPRE_UV VPRE undervoltage detection 0 No undervoltage (VPRE > VPRE_UV) 1 Undervoltage detected (VPRE < VPRE_UV) Reset condition Description TSD_CORE Thermal shutdown of VCORE 0 No TSD (TJ< TSD_CORE) 1 TSD occurred (TJ > TSD_CORE) Reset condition Description VCORE_FB_OV Power On Reset / Read VCORE overvoltage detection 0 No overvoltage (VCORE_FB < VCORE_FB_OV) 1 Overvoltage detected (VCORE_FB > VCORE_FB_OV) Reset condition Description VCORE_FB_UV Power On Reset / Read Power On Reset / Read VCORE undervoltage detection 0 No undervoltage (VCORE_FB > VCORE_FB_UV) 1 Undervoltage (VCORE_FB < VCORE_FB_UV) Reset condition Power On Reset / Read 7.3.13 Diag Vreg2 Table 42. DIAG VREG2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ Vcore_ Vother Tsd_C G G s_G an Vcan_ Vcan_u OV v 0 Tsd_au Ilim_au Vaux_ Vaux_u x x_off OV v Table 43. Diag Vreg2. Description and Configuration of the Bits (Default value in bold) Description TSD_CAN 0 NO TSD (TJ < TSD_CAN) 1 TSD occurred (TJ > TSD_CAN) Reset condition Description VCAN_OV Power On Reset / Read VCAN Overvoltage detection 0 No Overvoltage (VCAN < VCAN_OV) 1 Overvoltage detected (VCAN > VCAN_OV) Reset condition Description VCAN_UV Thermal shutdown of VCAN Power On Reset / Read VCAN undervoltage detection 0 No undervoltage (VCAN > VCAN_UV) 1 Undervoltage detected (VCAN < VCAN_UV) Reset condition Power On Reset / Read 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 87 Table 43. Diag Vreg2. Description and Configuration of the Bits (Default value in bold) (continued) Description TSD_AUX Thermal shutdown of VAUX 0 No TSD (TJ < TSD_AUX) 1 TSD occurred (TJ > TSD_AUX) Reset condition Description ILIM_AUX_OFF Maximum current limitation duration 0 T_LIMITATION < TAUX_LIM_OFF 1 T_LIMITATION >TAUX_LIM_OFF Reset condition Description VAUX_OV Power On Reset / Read VAUX overvoltage detection 0 No overvoltage (VAUX < VAUX_OV) 1 Overvoltage detected (VAUX > VAUX_OV) Reset condition Description VAUX_UV Power On Reset Power On Reset / Read VAUX undervoltage detection 0 No undervoltage (VAUX > VAUX_UV) 1 Undervoltage detected (VAUX < VAUX_UV) Reset condition Power On Reset / Read 7.3.14 Diag Vreg3 Table 44. DIAG VREG3 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G 0 Ilimcca_off 0 Vcca_ OV 0 Vcca_ UV 0 Vpre_ Vcore_ Vother Tsd_cc G G s_G a Table 45. Diag Vreg3. Description and Configuration of the Bits (Default value in bold) Description TSD_CCA 0 NO TSD (TJ < TSD_CCA) 1 TSD occurred (TJ > TSD_CCA) Reset condition Description ILIM_CCA_OFF Power On Reset / Read Maximum current limitation duration. Available only when an external PNP is connected 0 T_LIMITATION < TCCA_LIM_OFF 1 T_LIMITATION >TCCA_LIM_OFF Reset condition Description VCCA_OV Thermal shutdown of VCCA Power On Reset / Read VCCA overvoltage detection 0 No overvoltage (VCCA < VCCA_OV) 1 Overvoltage detected (VCCA > VCCA_OV) Reset condition Power On Reset / Read 33907/33908 88 Analog Integrated Circuit Device Data Freescale Semiconductor Table 45. Diag Vreg3. Description and Configuration of the Bits (Default value in bold) (continued) Description VCCA_UV VCCA undervoltage detection 0 No undervoltage (VCCA > VCCA_UV) 1 Undervoltage detected (VCCA < VCCA_UV) Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 89 7.3.15 Diag CAN1 Table 46. DIAG CAN1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G CAN_d Vpre_ Vcore_ Vother CANH_ CANH_ CANL_ CANL_ ominan G G s_G batt gnd batt gnd t 0 RXD_r TXD_d ecessiv ominan e t Table 47. Diag CAN1. Description and Configuration of the Bits (Default value in bold) Description CANH_batt 0 No failure 1 Failure detected Reset condition Description CANH_gnd 1 Failure detected 1 Failure detected Power On Reset / Read CANL short-circuit to GND detection 0 No failure 1 Failure detected Reset condition Description Power On Reset / Read CAN Bus dominant clamping detection 0 No failure 1 Failure detected Reset condition Description Power On Reset / Read RXD recessive clamping detection (short-circuit to 5.0 V) 0 No failure 1 Failure detected Reset condition Description TXD_dominant CANL short-circuit to battery detection No failure Description RXD_recessive Power On Reset / Read 0 Reset condition CAN_dominant CANH short-circuit to GND detection No failure Description CANL_gnd Power On Reset / Read 0 Reset condition CANL_batt CANH short-circuit to battery detection Power On Reset / Read TXD dominant clamping detection (short-circuit to GND) 0 No failure 1 Failure detected Reset condition Power On Reset / Read 33907/33908 90 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.16 Diag CAN_LIN Table 48. DIAG CAN_LIN Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G TXDL_ Vcore_ Vothers LIN_do domina G _G minant nt 0 RXDL_ LIN_O recessi T ve 0 CAN_O CAN_O T C Table 49. Diag CAN_LIN. Description and Configuration of the Bits (Default value in bold) Description LIN_dominant 0 No failure 1 Failure detected Reset condition Description TXDL_dominant 1 Failure detected LIN RXD recessive clamping detection (short-circuit to 5.0 V) No failure 1 Failure detected Description Power On Reset / Read LIN overtemperature detection 0 No failure 1 Failure detected Reset condition Description Power On Reset / Read CAN overtemperature detection 0 No failure 1 Failure detected Reset condition Description CAN_OC Power On Reset / Read 0 Reset condition CAN_OT LIN TXD dominant clamping detection (short-circuit to GND) No failure Description LIN_OT Power On Reset / Read 0 Reset condition RXDL_recessive LIN bus dominant clamping detection Power On Reset / Read CAN overcurrent detection 0 No failure 1 Failure detected Reset condition Power On Reset / Read 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 91 7.3.17 Diag SPI Table 50. DIAG SPI Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G 0 SPI_clk 0 SPI_re q 0 SPI_pa rity 0 CAN_G LIN_G Vcore_ Vothers SPI_err G _G Table 51. Diag SPI. Description and Configuration of the Bits (Default value in blue) Description SPI_err 0 No error 1 Error detected in the secured bits Reset condition Description SPI_CLK SCLK error detection 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or > 16) Description Power On Reset / Read Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address) 0 No error 1 SPI violation Reset condition Description SPI_parity Power On Reset / Read 0 Reset condition SPI_req Secured SPI communication check Power On Reset / Read SPI parity bit error detection 0 Parity bit OK 1 Parity bit error Reset condition Power On Reset / Read 33907/33908 92 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.18 Mode Table 52. MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 MOSI 1 0 1 0 1 0 1 P 0 0 MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 MOSI 0 0 1 0 1 0 1 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit5 bit4 bit3 bit2 bit1 bit0 Goto_L INT_re Secure Secure Secure Secure POFF quest _3 _2 _1 _0 Vcore_ Vothers Reserv Reserv Reserv Reserv G _G ed ed ed ed Reserv Reserv ed ed INIT Normal bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 Read CAN_G LIN_G Vcore_ Vothers Reserv Reserv Reserv Reserv G _G ed ed ed ed INIT Normal Reserv Reserv ed ed Table 53. MODE. Description and Configuration of the Bits (Default value in bold) Description Goto_LPOFF 0 No action 1 LPOFF mode Reset condition Description INIT Report if INIT mode of the main logic state machine is entered Not in INIT mode 1 INIT MODE Description Power On Reset Report if Normal mode of the main logic state machine is entered 0 Not in Normal mode 1 Normal mode Reset condition Description INT_request Power On Reset 0 Reset condition Normal Configure the device in Low Power mode VREG OFF (LPOFF) Power On Reset Request for an INT pulse 0 No Request 1 Request for an INT pulse Reset condition Description Secure 3:0 Power On Reset Secured bits based on write bits secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 93 7.3.19 Vreg Mode Table 54. VREG MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 MOSI 1 0 1 0 1 1 0 P MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_ G G s_G ed ed ed ed EN EN bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 MOSI 0 0 1 0 1 1 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vcore_ Vcca_ EN EN bit5 Vaux_ EN bit4 bit3 bit2 bit1 bit0 Vcan_ Secure Secure Secure Secure EN _3 _2 _1 _0 Vaux_ EN Vcan_ EN bit2 bit1 bit0 0 0 0 Vaux_ EN Vcan_ EN Read Vpre_ Vcore_ Vother Reserv Reserv Reserv Reserv Vcore_ Vcca_ G G s_G ed ed ed ed EN EN Table 55. VREG MODE. Description and Configuration of the Bits (Default value in bold) Description VCORE_EN 0 DISABLED 1 ENABLED Reset condition Description VCCA_EN 1 ENABLED Power On Reset VAUX control (Switch OFF NOT recommended if VAUX is SAFETY critical) 0 DISABLED 1 ENABLED Reset condition Description Power On Reset VCAN control 0 DISABLED 1 ENABLED Reset condition Description Secure 3:0 VCCA control (Switch OFF NOT recommended if VCCA is SAFETY critical) DISABLED Description VCAN_EN Power On Reset 0 Reset condition VAUX_EN VCORE control (Switch OFF NOT recommended if VCORE is SAFETY critical) Power On Reset Secured bits based on write bits secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 33907/33908 94 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.20 IO_OUT-AMUX Table 56. IO_OUT-AMUX Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 0 1 0 1 1 1 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 bit5 bit4 IO_out IO_out IO_out IO_out _4_EN _4 _5_EN _5 bit3 0 bit2 bit1 bit0 Amux_ Amux_ Amux_ 2 1 0 Vcore_ Vothers IO_out IO_oou IO_out IO_out Reserv Amux_ Amux_ Amux_ G _G _4_EN t_4 _5_EN _5 ed 2 1 0 Read CAN_G LIN_G Vcore_ Vothers IO_out IO_out IO_out IO_out Reserv Amux_ Amux_ Amux_ G _G _4_EN _4 _5_EN _5 ed 2 1 0 Table 57. IO_OUT-AMUX. Description and Configuration of the Bits (Default value in bold) Description IO_out_4_EN 0 High-impedance (IO_4 configured as input) 1 ENABLED (IO_4 configured as output gate driver) Reset condition Description IO_out_4 Configure IO_4 output gate driver state LOW 1 HIGH Description Power On Reset Enable the output gate driver capability for IO_5 0 High-impedance (IO_5 configured as input) 1 ENABLED (IO_5 configured as output gate driver) Reset condition Description IO_out_5 Power On Reset 0 Reset condition IO_out_5_EN Enable the output gate driver capability for IO_4 Power On Reset Configure IO_5 output gate driver state 0 LOW 1 HIGH Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 95 Table 57. IO_OUT-AMUX. Description and Configuration of the Bits (Default value in bold) (continued) Description AMUX_2:0 Select AMUX output 000 Vref 001 Vsns wide range 010 IO_0 wide range 011 IO_1 wide range 100 Vsns tight range 101 IO_0 tight range 110 IO_1 tight range 111 Die Temperature Sensor Reset condition Power On Reset 7.3.21 CAN_LIN Mode Table 58. CAN_LIN MODE Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 MOSI 1 0 1 1 0 0 0 P MISO SPI_G WU CAN_ G LIN_G IO_G CAN_ CAN_ Vpre_ Vcore_ Vother CAN_a LIN_m LIN_m LIN_au CAN_w LIN_wu mode_ mode_ G G s_G uto_dis ode_1 ode_0 to_dis u 1 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G CAN_ CAN_ CAN_a LIN_m LIN_m LIN_au mode_ mode_ uto_dis ode_1 ode_0 to_dis 1 0 bit1 0 bit0 0 Read CAN_ CAN_ Vpre_ Vcore_ Vother CAN_a LIN_m LIN_m LIN_au CAN_w LIN_wu mode_ mode_ G G s_G uto_dis ode_1 ode_0 to_dis u 1 0 Table 59. CAN_LIN MODE. Description and Configuration of the Bits (Default value in bold) Description CAN_mode_1:0 00 Sleep / NO wake-up capability 01 LISTEN ONLY 10 Sleep / Wake-up capability 11 Normal operation mode Reset condition Description CAN_auto_dis Configure the CAN mode Power On Reset Automatic CAN Tx disable 0 NO auto disable 1 Reset CAN_mode from “11” to “01” on CAN over temp or TXD dominant or RXD recessive event Reset condition Power On Reset 33907/33908 96 Analog Integrated Circuit Device Data Freescale Semiconductor Table 59. CAN_LIN MODE. Description and Configuration of the Bits (Default value in bold) (continued) Description LIN_mode_1:0 Configure the LIN mode 00 Sleep / NO wake-up capability 01 LISTEN ONLY 10 Sleep / Wake-up capability 11 Normal operation mode Reset condition Description LIN_auto_dis Power On Reset Automatic LIN Tx Disable 0 No Auto disable 1 Reset LIN_mode from “11” to “01” on LIN over temp or TXDL dominant or RXDL recessive event Reset condition Description CAN_wu Report a wake-up event from the CAN 0 No wake-up 1 Wake-up detected Reset condition Description LIN_WU Power On Reset / Read Report a wake-up event from the LIN 0 No wake-up 1 Wake-up detected Reset condition Power On Reset / Read Notes 33. CAN mode is automatically configured to “sleep + wake-up capability[10]” if CAN mode was different than “sleep + no wake-up capability [00]” before the device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored. 7.3.22 Can_Mode_2 Table 60. CAN_MODE_2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 MOSI 1 0 1 1 0 0 1 P 0 0 0 MISO SPI_G WU IO_G Vpre_G 0 0 0 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G 0 0 0 0 CAN_G LIN_G Vcore_ Vothers G _G bit4 bit3 bit2 bit1 bit0 Vcan_ secure secure secure secure OV_Mo _3 _2 _1 _0 n Vcan_ Reserv Reserv Reserv OV_Mo ed ed ed n Read CAN_G LIN_G Vcore_ Vothers G _G Vcan_ Reserv Reserv Reserv OV_Mo ed ed ed n 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 97 Table 61. CAN_MODE_2. Description and Configuration of the Bits (Default value in bold) Description Vcan_OV_Mon VCAN OV Monitoring 0 OFF. VCAN OV is not monitored. Flag is ignored 1 ON. VCAN OV flag is under monitoring. In case of OV the VCAN regulator is switched OFF. Reset condition Description Power On Reset Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure 3:0 7.3.23 INIT SUPERVISOR1 Table 62. INIT SUPERVISOR1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 0 0 1 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Vcore_ Vcore_ Vcca_F Vcca_F secure Secure Secure Secure FS1 FS_0 S_1 S_0 _3 _2 _1 _0 Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F G _G _err _CLK _Req _Parity FS1 FS_0 S_1 S_0 Read CAN_G LIN_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS Vcore_ Vcore_ Vcca_F Vcca_F G _G _err _CLK _Req _Parity FS1 FS_0 S_1 S_0 Table 63. INIT SUPERVISOR1. Description and Configuration of the Bits (Default value in bold) Description Vcore_FS1:0 00 No effect of VCORE_FB_OV and VCORE_FB_UV on RSTb and FSxx 01 VCORE_FB_OV DOES HAVE an impact on RSTb and FSxx. VCORE_FB_UV DOES HAVE an impact on RSTb only 10 VCORE_FB_OV DOES HAVE an impact on RSTb and FSxx. No effect of VCORE_FB_UV on RSTb and FSxx 11 Both VCORE_FB_OV and VCORE_FB_UV DO HAVE an impact on RSTb and FSxx Reset condition Description Vcca_FS1:0 VCORE safety input. Power On Reset VCCA safety input. 00 No effect of VCCA_OV and VCCA_UV on RSTb and FSxx 01 VCCA_OV DOES HAVE an impact on RSTb and FSxx. VCCA_UV DOES HAVE an impact on RSTb only 10 VCCA_OV DOES HAVE an impact on RSTb and FSxx. No effect of VCCA_UV on RSTb and FSxx 11 Both VCCA_OV and VCCA_UV DO HAVE an impact on RSTb and FSxx Reset condition Power On Reset 33907/33908 98 Analog Integrated Circuit Device Data Freescale Semiconductor Table 63. INIT SUPERVISOR1. Description and Configuration of the Bits (Default value in bold) (continued) Description Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 Description SPI_FS_err Secured SPI communication check, concerns Fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit Description SPI_FS_CLK 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in Normal mode, wrong address), concerns fail-safe logic only. Description SPI_FS_Req Power On Reset 0 No error 1 SPI violation Reset condition Description Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset SPI_FS_Parity 7.3.24 INIT SUPERVISOR2 Table 64. INIT SUPERVISOR2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 0 1 0 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 MOSI 0 1 0 0 0 1 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 Vaux_F Vaux_F S1 S_0 bit5 bit4 0 DIS_8s Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 Vaux_F Vaux_F S1 S_0 0 DIS_8s bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 DIS_8s Read CAN_G LIN_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity Vaux_F Vaux_F S1 S_0 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 99 Table 65. INIT SUPERVISOR2. Description and Configuration of the Bits (Default value in bold) Description Vaux_FS1:0 00 No effect of VAUX_OV and VAUX_UV on RSTb and FSxx 01 VAUX_OV DOES HAVE an impact on RSTb and FSxx. VAUX_UV DOES HAVE an impact on RSTb only 10 VAUX_OV DOES HAVE an impact on RSTb and FSxx. No effect of VAUX_UV on RSTb and FSxx 11 Both VAUX_OV and VAUX_UV DO HAVE an impact on RSTb and FSxx Reset condition Description DIS_8s 1 DISABLED Description Secured bits based on write bits Secured SPI communication check, concerns fail-safe logic only. 0 No error 1 Error detected in the secured bits Reset condition Description Power On Reset SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Description Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe Logic only 0 No error 1 SPI violation Reset condition Description SPI_FS_Parity Power On Reset Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 SPI_FS_Req Disable the 8.0 s timer used to enter Deep Fail-safe mode ENABLED Description SPI_FS_CLK Power On Reset 0 Reset condition SPI_FS_err VAUX safety input. Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907/33908 100 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.25 INIT SUPERVISOR3 Table 66. INIT SUPERVISOR3 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 MOSI 1 1 0 0 0 1 1 P 0 MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit6 bit5 Vcca_5 Vaux_5 D D bit4 0 Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 0 Reserv Vcca_5 Vaux_5 ed D D Read CAN_G LIN_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS G _G _err _CLK _req _Parity 0 Reserv Vcca_5 Vaux_5 ed D D Table 67. INIT SUPERVISOR3. Description and Configuration of the Bits (Default value in bold) Description VCCA_5D 0 Normal 5.0 V undervoltage detection threshold (VCCA_UV_5) 1 Degraded mode, i.e lower undervoltage detection threshold applied (VCCA_UV_D) Reset condition Description VAUX_5D Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V Normal 5.0 V undervoltage detection threshold (VAUX_UV_5) 1 Degraded mode, i.e lower undervoltage detection threshold applied (VAUX_UV_5D) Description Power On Reset Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2= NOT(bit4) Secured_1=bit7 Secured_0=bit6 Secure3:0 Description Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Description SPI_FS_CLK Power On Reset 0 Reset condition SPI_FS_err Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V Power On Reset SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 101 Table 67. INIT SUPERVISOR3. Description and Configuration of the Bits (Default value in bold) (continued) Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe logic only Description SPI_FS_Req 0 No error 1 SPI violation Reset condition Description Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset SPI_FS_Parity 7.3.26 Init FSSM1 Table 68. INIT FSSM1 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 1 0 0 1 0 0 P MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ Vcore_ Vother G G s_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G IO_01_ IO_1_F IO_45_ RSTb_l Secure Secure Secure Secure FS S FS ow _3 _2 _1 _0 SPI_F SPI_F SPI_F SPI_F IO_01_ IO_1_F IO_45_ RSTb_l S_Parit S_err S_CLK S_req FS S FS ow y Read Vpre_ Vcore_ Vother G G s_G SPI_F SPI_F SPI_F SPI_F IO_01_ IO_1_F IO_45_ RSTb_l S_Parit S_err S_CLK S_req FS S FS ow y Table 69. INIT FSSM1. Description and Configuration of the Bits (Default value in bold) Description IO_01_FS 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Description IO_1_FS Power On Reset Configure IO_1 as safety inputs 0 NOT SAFETY 1 SAFETY CRITICAL (External resistor bridge monitoring active) Reset condition Description IO_45_FS Configure the couple of IO_1:0 as safety inputs Power On Reset Configure the couple of IO_5:4 as safety inputs 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Power On Reset 33907/33908 102 Analog Integrated Circuit Device Data Freescale Semiconductor Table 69. INIT FSSM1. Description and Configuration of the Bits (Default value in bold) (continued) Description RSTb_low Configure the Rstb LOW duration time 0 10 ms 1 1.0 ms Reset condition Description Power On Reset Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 Description SPI_FS_err Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK_ bit Description SPI_FS_CLK 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe logic only Description SPI_FS_Req Power On Reset 0 No error 1 SPI violation Reset condition Description Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset SPI_FS_Parity 7.3.27 Init FSSM2 Table 70. INIT FSSM2 Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 1 0 1 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 0 1 0 0 1 0 1 0 0 0 0 0 0 CAN_G LIN_G bit7 bit6 RSTb_ IO_23_ err_FS FS bit5 bit4 PS 0 bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_ G _G _err _CLK _req _Parity err_FS FS PS 0 bit2 bit1 bit0 0 0 0 Read MOSI 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 103 Table 70. INIT FSSM2 Register Description (continued) MISO SPI_G WU CAN_G LIN_G IO_G Vpre_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS RSTb_ IO_23_ G _G _err _CLK _req _Parity err_FS FS PS 0 Table 71. INIT FSSM2. Description and Configuration of the Bits (Default value in bold) Description IO_23_FS 0 NOT SAFETY 1 SAFETY CRITICAL Reset condition Description RSTb_err_FS 1 intermediate = 1; final = 2 1 Fccu_eaout_1:0 active LOW Power On Reset Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 Description Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Description Power On Reset SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by SPI_CLK_ bit 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Description Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe Logic only 0 No error 1 SPI violation Reset condition Description SPI_FS_Parity Configure the FCCU polarity Fccu_eaout_1:0 active HIGH Description SPI_FS_Req Power On Reset 0 Reset condition SPI_FS_CLK Configure the values of the RSTb error counter intermediate = 3; final = 6 Description SPI_FS_err Power On Reset 0 Reset condition PS Configure the couple of IO_3:2 as safety inputs for FCCU monitoring Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907/33908 104 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.28 WD window Table 72. WD WINDOW Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 0 1 1 0 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WD_wi WD_wi WD_wi WD_wi Secure Secure Secure Secure ndow3 ndow2 ndow1 ndow0 _3 _2 _1 _0 Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi G _G _err _CLK _req _Parity ndow3 ndow2 ndow1 ndow0 Read CAN_G LIN_G Vcore_ Vothers SPI_FS SPI_FS SPI_FS SPI_FS WD_wi WD_wi WD_wi WD_wi G _G _err _CLK _req _Parity ndow3 ndow2 ndow1 ndow0 Any WRITE command to the WD_window in the Normal mode must be followed by a READ command to verify the correct change of the WD window duration Table 73. WD Window. Description and Configuration of the Bits (Default value in bold) Description WD_Window_3:0 Configure the watchdog window duration. Duty cycle if set to 50% 0000 DISABLE 0001 1.0 ms 0010 2.0 ms 0011 3.0 ms 0100 4.0 ms 0101 6.0 ms 0110 8.0 ms 0111 12 ms 1000 16 ms 1001 24 ms 1010 32 ms 1011 64 ms 1100 128 ms 1101 256 ms 1110 512 ms 1111 1024 ms Reset condition Description Secure3:0 Power On Reset Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 105 Table 73. WD Window. Description and Configuration of the Bits (Default value in bold) (continued) Description SPI_FS_err Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK bit. Description SPI_FS_CLK 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe logic only Description SPI_FS_Req Power On Reset 0 No error 1 SPI violation Reset condition Description Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset SPI_FS_Parity 7.3.29 WD_LFSR Table 74. WD LFSR Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 1 0 0 1 1 1 P MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ G WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0 Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF G s_G SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0 Read Vcore_ Vother WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF WD_LF G s_G SR_7 SR_6 SR_5 SR_4 SR_3 SR_2 SR_1 SR_0 33907/33908 106 Analog Integrated Circuit Device Data Freescale Semiconductor Table 75. WD LFSR. Description and Configuration of the Bits (Default value in bold) Description WD 8 bits LFSR value. Used to write the seed at any time 0... WD_LFSR_7:0 bit7:bit0: 10110010 default value at start-up or after a Power on reset: 0xB2 (34), (35) 1... Reset condition Power On Reset Notes 34. Value Bit7:Bit0: 1111 1111 is prohibited. 35. During a write command, MISO reports the previous register content. 7.3.30 WD answer Table 76. WD ANSWER Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 0 0 P MISO SPI_G WU IO_G Vpre_G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 0 1 0 1 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WD_an WD_an WD_an WD_an WD_an WD_an WD_an WD_an swer_7 swer_6 swer_5 swer_4 swer_3 swer_2 swer_1 swer_0 Vcore_ Vothers RSTb G _G FS0 WD FS0_G IO_FS_ G 0 FS_EC FS_reg C _Ecc bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 FS0 WD FS0_G IO_FS_ G 0 Read CAN_G LIN_G Vcore_ Vothers RSTb G _G FS_EC FS_reg C _Ecc Table 77. WD answer. Description and Configuration of the Bits (Default value in bold) Description WD_answer_7:0 0... 1... Reset condition Description RSTb FS0b WD answer from the MCU Answer = (NOT(((LFSR x 4)+6)-4))/4 Power On Reset / RSTb LOW Report a reset event 0 No Reset 1 Reset occurred Reset condition Power On Reset / Read Description Report a fail-safe event 0 No fail-safe 1 Fail safe event occurred / Also default state at power-up after LPOFF as FS0b is asserted low Reset condition Power On Reset / Read 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 107 Table 77. WD answer. Description and Configuration of the Bits (Default value in bold) (continued) Description WD Report a watchdog refresh ERROR 0 WD refresh OK 1 WRONG WD refresh Reset condition Description FS0_G Report a fail-safe output failure 0 No failure 1 Failure Reset condition Description IO_FS_G 0 No error 1 Error detected Description Power On Reset Report an error code correction on fail-safe state machine 0 No ECC 1 ECC done Reset condition Description FS_req_ECC Power On Reset / Read Report an IO monitoring error Reset condition FS_ECC Power On Reset / Read Power On Reset / Read Report an error code correction on fail-safe registers 0 No ECC 1 ECC done Reset condition Power On Reset / Read FS0_G = RSTB_short_high or FS0B_short_high or FS0B_short_low IO_FS_G = IO_01_fail or IO_1_fail or IO_23_fail or IO_45_fail Values of the three registers WD_answer, WD_counter, and DIAG_FS2 are updated at the end of any SPI access to one of these registers. To always get up to date values, it is recommended to make two consecutive SPI accesses to these registers. Example: read WD_answer, read again WD_answer, read WD_counter, read DIAG_FS2. The first read updates the three registers and the second read report the latest information. 7.3.31 Fail-safe Out (FS_out) Table 78. Fail-safe Out Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 0 1 P MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FS_out FS_out FS_out FS_out FS_out FS_out FS_out FS_out _7 _6 _5 _4 _3 _2 _1 _0 Vcore_ Vothers G _G 0 0 0 0 0 0 0 0 Table 79. Fail-Safe Out. Description and Configuration of the Bits (Default value in bold) Description FS_out_7:0 0... 1... Reset condition Secured 8 bits word to release the FS0b Depend on LFSR_out value and calculation Power On Reset -> Default = 00h 33907/33908 108 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.32 RSTB Request Table 80. RSTb REQUEST register description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 MOSI 1 1 0 1 0 1 0 P 0 0 RSTb_r equest 0 MISO SPI_G WU IO_G Vpre_G 0 0 0 0 0 0 0 0 bit4 bit3 bit2 bit1 bit0 CAN_G LIN_G Vcore_ Vothers G _G bit3 bit2 bit1 bit0 Secure Secure Secure Secure _3 _2 _1 _0 Table 81. RSTb Request. Description and configuration of the bits (Default value in bold) Description RSTb_request Request a RSTb low pulse 0 No request 1 Request a RSTb low pulse Reset condition Description Power On Reset / When RSTb done Secured bits based on write bits Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 7.3.33 INIT_WD Table 82. INIT WD Register Description Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 MOSI 1 1 0 1 0 1 1 P MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ G bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU CAN_ G LIN_G IO_G Vpre_ G Vcore_ Vother G s_G bit7 bit6 bit5 WD_C WD_C WD_C WD_C secure secure secure secure NT_err NT_err NT_refr NT_refr 3 2 1 0 or_1 or_0 esh_1 esh_0 SPI_F WD_C WD_C WD_C WD_C SPI_F SPI_F SPI_F S_Parit NT_err NT_err NT_refr NT_refr S_err S_CLK S_Req y or_1 or_0 esh_1 esh_0 Read Vcore_ Vother G s_G SPI_F WD_C WD_C WD_C WD_C SPI_F SPI_F SPI_F S_Parit NT_err NT_err NT_refr NT_refr S_err S_CLK S_Req y or_1 or_0 esh_1 esh_0 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 109 Table 83. INIT WD. Description and Configuration of the Bits (Default value in bold) Description WD_CNT_error_1:0 00 6 01 6 10 4 11 2 Reset Condition Description WD_CNT_refresh_ 1:0 01 4 10 2 11 1 Description Secured bits based on write bits Secured SPI communication check, concerns fail-safe logic only 0 No error 1 Error detected in the secured bits Reset condition Description Power On Reset SCLK error detection, concerns internal error in fail-safe logic only and external errors (at pin level) for both main and fail-safe logics. Other errors flagged by the SPI_CLK bit. 0 16 clock cycles during NCS low 1 Wrong number of clock cycles (<16 or >16) Reset condition Description Power On Reset Invalid SPI access (Wrong Write or Read, Write to INIT registers in normal mode, wrong address), concerns fail-safe logic only 0 No error 1 SPI violation Reset condition Description SPI_FS_Parity Power On Reset Secured_3 = NOT(bit5) Secured_2 = NOT(bit4) Secured_1 = bit7 Secured_0 = bit6 Secure3:0 SPI_FS_Req Configure the maximum value of the WD refresh counter 6 Description SPI_FS_CLK Power On Reset 00 Reset Condition SPI_FS_err Configure the maximum value of the WD error counter Power On Reset SPI parity bit error detection, concerns fail-safe logic only 0 Parity bit OK 1 Parity bit ERROR Reset condition Power On Reset 33907/33908 110 Analog Integrated Circuit Device Data Freescale Semiconductor 7.3.34 Diag FS1 Table 84. DIAG FS1 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G 0 0 0 CAN_G LIN_G Vcore_ Vothers RSTb_ RSTb_ G _G ext diag 0 FS0b_ FS0b_ diag_1 diag_0 Table 85. Diag FS1. Description and Configuration of the Bits (Default value in bold) Description RSTb_diag Report a RSTb short-circuit to HIGH 0 No Failure 1 Short-circuit HIGH Reset condition Power On Reset / Read Description Report an external RSTb RSTb_ext 0 No external RSTb 1 External RSTb Reset condition Power On Reset / Read Description Report a failure on FS0b FS0b_diag_1:0 00 No Failure 01 Short-circuit LOW / open load 1X Short-circuit HIGH Reset condition Power On Reset / Read 7.3.35 WD Counter Table 86. WD COUNTER Register Description Read bit15 bit14 bit13 bit12 bit11 MOSI 0 1 MISO SPI_ G WU 0 1 1 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 1 0 0 0 0 0 0 0 0 0 CAN_ LIN_ Vpre_ Vcore_ Vothers_ WD_err WD_err WD_err IO_G G G G G G _2 _1 _0 0 WD_ref WD_refr WD_refr resh_2 esh_1 esh_0 0 Table 87. WD counter. Description and Configuration of the Bits (Default value in bold) Description WD_err_2:0 000 to 110 Reset condition Report the value of the watchdog error counter From 0 to 5 (6 generates a Reset and this counter is reset to 0) Power On Reset 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 111 Table 87. WD counter. Description and Configuration of the Bits (Default value in bold) Description Report the value of the watchdog refresh counter 000 WD_refresh_2:0 From 0 to 6 (7 generate a decrease of the RST_err_cnt and this counter is reset to 0) to 111 Reset condition Power On Reset 7.3.36 Diag FS2 Table 88. DIAG FS2 Register Description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 MISO SPI_G WU IO_G Vpre_G CAN_G LIN_G Vcore_ Vothers RSTb_ RSTb_ RSTb_ G _G err_2 err_1 err_0 0 IO_45_ IO_23_ IO_1_F IO_01_ fail fail ail fail Table 89. Diag FS2. Description and Configuration of the Bits (Default value in bold) Description RSTb_err_2:0 000 001 … 110 Reset condition Description IO_45_fail Report an error in the IO_45 protocol 1 Error detected Power On Reset / Read Report an error in the FCCU protocol 0 No error 1 Error detected Reset condition Description Power On Reset / Read Report an error in the IO_1 monitoring (external resistor string monitoring) 0 No error 1 Error detected Reset condition Description IO_01_fail Power On Reset No error Description IO_1_fail Error counter is set to 1 by default 0 Reset condition IO_23_fail Report the value of the RSTb error counter Power On Reset Report an error in the IO_01 protocol 0 No error 1 Error detected Reset condition Power On Reset / Read 33907/33908 112 Analog Integrated Circuit Device Data Freescale Semiconductor 8 List of Interruptions and Description The INTB output pin generates a low pulse when an Interrupt condition occurs. The INTB behavior as well as the pulse duration are set through the SPI during INIT phase. It is possible to mask some Interruption source (see Detail of Register Mapping). Table 90. Interruptions list Event Description VSNS_UV Detection of VBATTERY below 8.5 V VSUP_UV_7 Detection of VSUP below 7.0 V (after reverse current protection diode) IPFF Input power feed forward. Based on VSUP and IPRE_PEAK ILIM_PRE Pre-regulator Current Limitation TWARN_PRE Temperature warning on the pass transistor BoB Return the running state of VPRE converter (Buck or Boost mode) VPRE_STATE (VPRE_SMPS_EN) Return the activation state of VPRE DC/DC converter VPRE OV Report a VPRE overvoltage detection VPRE UV Report a VPRE undervoltage detection ILIM_CORE VCORE Current limitation TWARN_CORE Temperature warning on the pass transistor VCORE_STATE (VCORE_SMPS_EN) Return the activation state of VCORE DC/DC converter VCORE OV Report a VCORE overvoltage detection VCORE UV Report a VCORE undervoltage detection ILIM_CCA VCCA Current limitation TWARN_CCA Temperature warning on the pass transistor (Internal Pass transistor only) TSDVCCA Temperature shutdown of the VCCA ILIM_CCA_OFF Current limitation maximum duration expiration. Only used when external PNP connected. VCCA OV Report a VCCA overvoltage detection VCCA UV Report a VCCA undervoltage detection ILIM_AUX VAUX Current limitation ILIM_AUX_OFF Current limitation maximum duration expiration. Only used when external PNP connected. VAUX OV Report a VAUX overvoltage detection VAUX UV Report a VAUX undervoltage detection TSDVAUX Temperature shutdown of the VAUX ILIM_CAN VCAN Current limitation VCAN OV Report a VCAN overvoltage detection VCAN UV Report a VCAN undervoltage detection TSDCAN Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN - TSDCAN_HYST). IO_0 Report IO_0 digital state change IO_1 Report IO_1 digital state change IO_2 Report IO_2 digital state change IO_3 Report IO_3 digital state change IO_4 Report IO_4 digital state change IO_5 Report IO_5 digital state change 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 113 Table 90. Interruptions list (continued) IO_0_WU Report IO_0 WU event IO_1_WU Report IO_1 WU event IO_2_WU Report IO_2 WU event IO_3_WU Report IO_3 WU event IO_4_WU Report IO_4 WU event IO_5_WU Report IO_5 WU event CAN_WU Report a CAN wake-up event CAN_OT CAN overtemperature detection RXD_recessive CAN RXD recessive clamping detection (short-circuit to 5.0 V) TXD_dominant CAN TXD dominant clamping detection (short circuit to GND) CAN_dominant CAN bus dominant clamping detection LIN_WU Report a LIN wake-up event LIN_OT LN over-temperature detection RXDL_recessive LIN RXDL recessive clamping detection (short to high) TXDL dominant LIN TXDL dominant clamping detection (short to GND) LIN dominant LIN bus dominant clamping detection INT_Request MCU request for an Interrupt pulse SPI_err Secured SPI communication check SPI_CLK Report a wrong number of CLK pulse different than 16 during the NCS low pulse in Main state machine SPI_Req Invalid SPI access (Wrong write or read, write to INIT registers in normal mode, wrong address) SPI_Parity Report a Parity error in Main state machine 33907/33908 114 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications PGND PGND GND RSelect Key on Resistor must be close to Select pin GND 5.1 k R1(+/‐5%) 200 510 C1 R2(+/‐5%) 220pF 39K 680pF 18K C2 Cout 1nF 2*10µF 150pF 2*10µF IO_2 FCCU monitoring from Freescale MCU MOSI MISO SCLK NCS MCU inputs GND INTB MCU Int. VDDIO 5.1K GND RSTB MCU RESET VDDIO or VSUP3 GND FS0B IO_5 MUX_OUT (output selected by SPI) Vsense or VIO_0 or VIO_1 or Internal 2.5V reference voltage (2.5V +/-1%) 5.1 k GND CAN BUS CANH DEBUG Ground Connections PGND ground plane connected to DGND pin GND ground plane connected to AGND and GND_COM pins PGND (DGND) and GND (AGND & GND_COM) connected together far from PGND ground plane. CANL VSUP3 LIN GNDA GND_COM DGND GND GND PGND 5.1K if connected to VDDIO >10K if connected to Vsup3 To Fail Safe circuitry 5.1K Vpre 10K GND 120 LIN BUS 100nF 0R MUX_OUT Vaux (5V or 3.3V) 300mA capability +/-3% accuracy IO_3 5.1 k 10 µF MCU SPI IO_4 GND 4.7 µF 4 GND 10 nF Recommended connection for IOs not used in the application R4(+/‐1%) 8.06K 8.06K Vcca (5V or 3.3V), available configurations Whithout Ext. PNP : 100mA capability +/-1% accuracy for 5V configuration, +/-1.5% accuracy for 3.3V configuration, With Ext. PNP : < 200mA +/-2% accuracy With Ext. PNP : 300mA capability +/-3% accuracy IO_1 Optional R3(+/‐1%) 4.32K 24.9K (If connected to Vcore, must be connected closed to coutx 10µF x 2) SELECT IO_0 From 2nd Vcore resistor bridge 22 pF GND Connected to Vcca or Vcore VDDIO 1 nF Vbat Vcore voltage 1.23V 3.3V EMI sup. Capacitor must be connected closed to load (220nF) and connected to GND 10 nF CAN-5V Optional Example of IO connection and usage 5.1K +/-5% 12K +/-5% 24K +/-5% 51K +/-5% Components selection for Vcore voltage (current range 10mA ‐> 800mA, DI/DT = 2A/µs) 1µF ESR cap. <100m Capacitor closed to Vcca pin Capacitor must be close to Vaux pin GND Optional Recommended Value 100 nF VAUX 3.3V < 7 5V 10.8 <<13.2 5V 21.6 <<26.4 3.3V 45.9 <<56.1 Vcca_PNP VCCA DEBUG mode 10 nF 4.7µF EMI sup. Capacitor must be connected closed to load (100nF + 100pF) and connected to GND 3.3V 5V 3.3V 5V VAUX_B ESR cap. <100m Optional 1 nF Vaux_PNP Rselect (K) C2 VCCA_B GND Vaux GND Optional VCCA_E VAUX_E PGND R4 R4 GND R2 SELECT pin Configuration for VCCA & VAUX (R select connected to GND) Vcca PGND PGND To IO_1 COMP_CORE VSENSE 1µF R3 R1 GND VCORE_SNS FB_CORE BOOTS_CORE VPRE 5.1 k SW_CORE VSUP3 R3 330pF PGND GATE_LS BOOT_PRE SW_PRE2 SW_PRE1 VSUP2 VSUP1 PGND GND 10 µF 2.2nF 100nF 7.5 10 µF Optional 4.7 µF 4.7 µF 22 µF 22 µF PGND Vcore Voltage ESR cap. <10m C1 PGND PGND GND GND PGND PGND 2.2 µH Capacitors must be close to Vpre pin PGND 1K ESR cap. <10m 10 µF 10 µF ESR cap. <100m 8 1 µH Vbat Snubber values must be fine tuned as linked also to board layout performance 22 µH 100nF 2.2nF Snubber values must be fine tuned as linked also to board layout performance 10 µF 9 11K GND RXD TXD GND MCU CAN TXDL MCU LIN RXDL Figure 58. 33907/33908 Simplified Application Schematic with Non-inverting Buck-boost Configuration 33907/33908 33907L_08L VCCA_E VAUX_B VCCA_B VCCA ESR cap. <100 m Cout_Vaux VAUX RSelect GND Optional Vcca_PNP ESR cap. <100 m Cout_Vcca Vaux_PNP VAUX_E GND SELECT GND Figure 59. VAUX/VCCA Connection 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 115 VPRE 33907/33908 33907L_08L NC VAUX_E VCCA_E VAUX_B VCCA_B Optional Vcca_PNP ESR cap. <100 m NC Cout_Vcca VCCA VAUX RSelect GND SELECT Figure 60. VCCA Connection, VAUX Not Used NC 33907/33908 33907L_8L VAUX_E VCCA_E VAUX_B VCCA_B VCCA NC RSelect VAUX NC ESR cap. <100 m Cout_Vcca VPRE GND SELECT Figure 61. VAUX Not Used, VCCA Configuration up to 100 mA 33907/33908 116 Analog Integrated Circuit Device Data Freescale Semiconductor 10 Packaging 10.1 Package Mechanical Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 91. Package Mechanical Dimensions Package 7.0 x 7.0, 48-Pin LQFP Exposed Pad, with 0.5 mm pitch, and a 4.5 x 4.5 exposed pad Suffix AE Package Outline Drawing Number 98ASA00173D 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 117 33907/33908 118 Analog Integrated Circuit Device Data Freescale Semiconductor 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 119 11 References The following are URLs where you can obtain information on related Freescale products and application solutions Freescale.com Support Pages Description URL AN4766 MC33907_08 System Basis Chip: Recommendations for PCB layout and external components AN4661 Designing the VCORE Compensation Network http://www.freescale.com/files/analog/doc/app_note/AN4661.pdf For The MC33907/MC33908 System Basis Chips AN4442 Integrating the MPC5643L and MC33907/08 for Safety Applications http://www.freescale.com/files/analog/doc/app_note/AN4442.pdf AN4388 Quad Flat Package (QFP) http://www.freescale.com/files/analog/doc/app_note/AN4388.pdf https://www.freescale.com/webapp/Download?colCode=AN4766 Power Dissipation Tool (Excel file) http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=MC33908&fpsp=1&tab=Design_Tools_Tab MC33907_8SMUG MC33907_8 Safety Manual - User Guide https://www.freescale.com/webapp/Download?colCode=MC33907_8SMUG FMEDA MC33907_8 FMEDA Upon demand KIT33907LAEEVB Evaluation Board http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=KIT33907LAEEVB KIT33908LAEEVB Evaluation Board http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=KIT33908LAEEVB KITMPC5643DBEVM Evaluation Daughter Board (Qorivva MPC5643L) http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=KITMPC5643DBEVM MC33907 Product Summary Page http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=MC33907 MC33908 Product Summary Page http://www.freescale.com/webapp/sps/site/ prod_summary.jsp?code=MC33908 Analog Home Page http://www.freescale.com/analog 33907/33908 120 Analog Integrated Circuit Device Data Freescale Semiconductor 12 Revision History REVISION 1.0 DATE 11/2014 • Product Preview release 12/2014 • Initial release. No change to content. 2.0 1/2015 3.0 1/2015 4.0 DESCRIPTION OF CHANGES 2/2015 • • • • • • • • Corrected WD_LFSR register access in read mode Added (35) Added clarifications after Table 77 Correct minor typographic errors Changed document status to Advance Information Changed the document order number to MC33907-MC33908D2 Corrected Revision History Corrected typo for ICORE_LIM • • • • • • Updated VSUP_UV_7 max. value from 8.2 to 8.0 V in Table 4 Updated Thermal Resistance values in Table 3 Changed Thermal Resistance Junction to Case Top value from 14.4 to 24.2 in Table 3 on page 10 Corrected a typo on page 46 (changed “For VSUP and VAUX 5.0 V” to “For VCCA and VAUX 5.0 V”) Corrected typo for VBUS_CNT in Table 4 on page 20 Corrected typo for D2 and D3 in Table 5 on page 25 33907/33908 Analog Integrated Circuit Device Data Freescale Semiconductor 121 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com on the information in this document. Web Support: freescale.com/support There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, Energy Efficient Solutions, and SafeAssure logos are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. Document Number: MC33907-MC33908D2 Rev. 4.0 2/2015