Freescale Semiconductor, Inc. Application Note Document Number: AN4661 Rev. 1.0, 10/2013 Designing the VCORE Compensation Network For The MC33907/MC33908 System Basis Chips 1 Introduction This application note explains how to design an effective compensation network for the VCORE error amplifier of the MC33907 and MC33908. The VCORE Regulator integrated inside these System Basis Chips is a non-synchronous voltage mode buck regulator. It generates the microcontroller core supply voltage. This voltage is adjusted using an external voltage divider in the range of 0.9V to 5V. As with any switch-mode DC/DC converter, the VCORE Regulator needs a compensation network for stabilizing the converter. It is necessary for compensating the gain and phase shift caused by the output filter of the buck regulator. Only with proper compensation can the buck converter react fast enough to load steps without falling into an unstable mode. © Freescale Semiconductor, Inc., 2013. All rights reserved. Contents 1 Introduction 1 2 Closed Loop System 2 3 Modulator Stage 2 4 Output Filter 3 5 The Compensated System 4 6 The Compensation Network 5 7 Calculation of the Compensation Network 7 8 Conclusion 9 9 References 10 10 Revision History 11 Closed Loop System 2 Closed Loop System Every buck converter has three main blocks: the modulator stage, the output filter and the compensation network (Figure 1). Reference Voltage + Modulator Stage Output Filter Output - Compensation Figure 1. Buck Converter Functional Blocks For the complete system the closed loop is expressed by Gain loop(s) = Gain Modulatorstage ⋅ Gain Filter(s) ⋅ Gain EA(s) Each of these stages has a specific transfer function. The characteristics of each block are shown in the next chapters. 3 Modulator Stage The modulator stage is the part which modulates the pulse width of the switch mode converter. It compares the output signal of the error amplifier with the sawtooth voltage of the oscillator and adjusts the pulse width (Figure 2). VIN VOSC Sawtooth Oscillator Output Filter Error Amplifier Figure 2. Pulse Width Modulation Stage AN4661 Application Note Rev. 1.0 10/2013 2 Freescale Semiconductor, Inc. Output Filter The gain of the modulator stage is defined by the quotient of input voltage VIN and the oscillator peak-to-peak voltage VOSC. V IN Gain Modulatorstage = --------------V OSC In case of the MC33907 and MC33908 the input voltage for the core regulator is the output voltage of the pre-regulator, typically 6.5 V. The peak-to-peak oscillator voltage VOSC is 1.45 for the devices. So the gain of the modulator stage is 4.48, or 13 dB respectively. 4 Output Filter The output filter comprises the output inductor (LOUT), its DC resistance (DCR), the output capacitor (COUT) and the equivalent series resistance of the output capacitor (ESR). LOUT DCR Power Stage COUT RLOAD ESR Figure 3. Output Filter The transfer function for this stage is as follows: 1 ------------------ + ESR sC OUT Gain Filter(s) = -------------------------------------------------------------------------------------------------------------------1 sL OUT + DCR + R LOAD || ⎛ ------------------ + ESR⎞ ⎝ sC OUT ⎠ With the assumption DCR = ESR ≈ 0, the equation can be simplified s 1 + -----ωz Gain Filter(s) = -------------------------------------------2 s s 1 + ----------- + ⎛ ------⎞ Qω 0 ⎝ ω 0⎠ with 1 ω Z = -------------------------------ESR ⋅ C OUT AN4661 Application Note Rev. 1.0 10/2013 Freescale Semiconductor, Inc. 3 . The Compensated System 1 ω 0 = ----------------------LC OUT C OUT Q = R LOAD -------------L From these equations, it is obvious that the gain and the phase shift of the output filter are affected by a zero caused by the ESR and a double pole created by LOUT and COUT. Let's remember, a pole changes the slope of the gain by -20 dB/decade and the phase changes from 0 to -90° over the range from one decade below to one decade above the pole frequency. For the double-pole created by LOUT and COUT, gain is therefore -40 dB/decade and phase is decreased by 180° with a very sharp roll off. For a zero the gain changes with +20 dB/decade and the phase changes from 0 to +90°, from one decade below to one decade above the zero frequency. The graph below shows a Bode plot (gain and phase) for an output filter with low ESR ceramic capacitors. In this example the components have following values: L = 2.2 µH, C = 20 µF and ESR = 10 mΩ. This filter has a double pole ω0 around 24 kHz and the zero ωZ is around 795 kHz. double pole at LC resonant frequency zero at output capacitor ESR 20 0 0 − 40 − 90 Phase [deg] Gain [dB] − 45 − 20 − 60 − 135 − 80 − 100 100 3 1×10 4 5 1×10 1×10 6 1×10 − 180 7 1×10 Frequency [Hz] Figure 4. Frequency Response for Output Filter with Low ESR Capacitors 5 The Compensated System To have a stable closed loop, the frequency response of the output filter and the gain of the modulator stage have to be compensated. Otherwise a load change could cause instabilities of the system. Compensation is done with the compensation network, which is connected to the error amplifier. A compensated system fulfills the following criteria: • • • The gain crosses 0 dB at the desired bandwidth (fC = crossover frequency) The gain rolls off with -20 dB/decade at the crossover frequency The phase margin is more than 45° below the crossover frequency One common question is how to choose the right crossover frequency fC. For a voltage mode buck converter, fC should be at least three times above the double-pole frequency. On the other hand, the crossover frequency has to be less than half of the switching frequency (fSW). With a higher crossover frequency, one can reach a faster load transient response, but circuits with high fC are prone to pick up noise. AN4661 Application Note Rev. 1.0 10/2013 4 Freescale Semiconductor, Inc. The Compensation Network 6 The Compensation Network A compensation network is necessary to meet the above-mentioned criteria for the stability of the closed loop system. There are different compensation networks which set gain and phase differently. The voltage mode buck converter with the double pole needs a compensation network that creates a large phase boost. Such an amplifier circuit is the so called “type 3 amplifier compensation”. It gives a very good transient response to the circuit. Zf Zi C3 Vin C2 C1 R3 R2 R1 Vout R Vref Figure 5. Compensation Network The transfer function of the type 3 amplifier block is 1 1 ---------- || ⎛ R 2 + ----------⎞ sC 1⎠ sC 2 ⎝ Zf Gain EA(s) = ----- = --------------------------------------------Zi 1 R 1 || ⎛⎝ R 3 + ----------⎞⎠ sC 3 Based on the transfer function, the poles and zeros of this circuit are: 1 ω zero1 = -------------R2 C1 1 ω zero2 = --------------------------------( R 1 + R 3 )C 3 C1 + C2 ω pole1 = ---------------------R2 C1 C2 1 ω pole2 = -------------R3 C3 AN4661 Application Note Rev. 1.0 10/2013 Freescale Semiconductor, Inc. 5 . The Compensation Network Figure 6 shows the gain and phase of an ideal type 3 amplifier, Figure 7 provides a more realistic simulation result. Figure 6. Frequency Response and Phase Margin for Ideal Type 3 Amplifier maximum phase boost at fC 50 90 40 30 0 20 10 0 100 − 45 ٛ pole_1 Plateau gain 20*log(R2/R1) Phase [deg] Gain [dB] 45 and ٛ zero_1 3 1×10 1×10 ٛ pole_2 ٛ zero_2 4 Frequency [Hz] 1×10 5 − 90 7 1×10 6 1×10 Figure 7. Type 3 Amplifier Simulated Frequency Response and Phase Margin AN4661 Application Note Rev. 1.0 10/2013 6 Freescale Semiconductor, Inc. Calculation of the Compensation Network 7 Calculation of the Compensation Network As already mentioned, the LC filter with low ESR ceramic capacitors creates a phase shift close to -180°. On the contrary, the phase margin has to be at least 45° below the crossover frequency. This means the phase shift must not be below -135°. The type 3 amplifier gives the necessary phase boost. The following example calculation is based on the filter parameter as used in the example above: L = 2.2 µH, C = 20 µF and ESR = 10 mΩ. The desired output voltage is 3.3 V. At first, select a crossover frequency, for example fC = 150 kHz. This is around six times the resonant frequency of the LC filter and below half of the switching frequency. The input voltage divider built using R1 and R defines the output voltage of the VCORE regulator. Therefore we already know R1, which in our example is 24.9 kΩ. In the next step, R2 is calculated. The ratio R2/R1 defines the plateau gain and, therefore, the crossover frequency. At the crossover frequency fC, the gain of the closed loop Gloop(s) is 0 dB. “Plateau gain” is the gain of the compensation circuit at the second zero ωzero_2. We will place this zero at the resonant frequency of the LC filter. As is already known, upwards from this zero, the gain is +20 dB / decade. From the Bode plot of the LC filter, one can read -31.5 dB at the crossover frequency. The required plateau gain (see also Figure 7) can now be calculated using Gain plateau(f zero2) = Gain Filter(f C) + Gain Modulatorstage + Gain slopez2 with fc Gain slopez2 = --------------f zero2 In our example, fc Gain plateau(f zero2) = – 31.5dB + 13dB + 20 log ⎛ ---------------⎞ = 2.5dB ⎝ f zero2⎠ This can be simplified to f c V OSC R 2 = -------- ⋅ --------------- ⋅ R 1 f LC V IN We get R2 = 34.7 kΩ. The first zero of the compensation network ωzero_1 should be placed at half of the LC filter pole frequency (½ * ω0). With this, C1 can be calculated. 2 C 1 = -------------R2 ω0 C 1 = 382pF Next, the first pole ωpole_1 of the compensation network is calculated. Because the ESR zero, ωZ, is far above the crossover frequency and does not play a role in the overall compensation, we can place this pole at half of the switching frequency of the VCORE regulator. C1 C 2 = ------------------------------------f SW πR 2 C 1 – 1 AN4661 Application Note Rev. 1.0 10/2013 Freescale Semiconductor, Inc. 7 . Calculation of the Compensation Network With fSW = 2.4 MHz, we calculate C2 = 3.8 pF. This small capacitance is already included within the circuit due to parasitic elements. In addition, a lower C2 boosts the phase at fC a little bit, but has no influence on gain and phase below fC. Therefore there is no need to insert this capacitor in the real circuit. R3 and C3 define the second zero ωzero_2 and second pole ωpole_2 of the compensation network. The second zero is placed at the same frequency as the first zero, at half of the LC filter's double pole ω0, whereas the second pole of the compensation is also placed at the same frequency as the first zero, at half of the switching frequency of the VCORE regulator, so we now have a double pole at this frequency. With some modification, we get the following equations: R1 R 3 = ------------------f SW --------- – 1 f LC 1 C 3 = -------------------πf SW R 3 For the switching frequency fSW = 2.4 MHz and the LC filter double pole frequency fLC = 24 kHz, we calculate R3 = 251 Ω and C3 = 527 pF. In order to meet the preferred component requirements list, the following values are selected: C1 = 390 pF R1 = 24.9 kΩ C3 = 560 pF R2 = 34.8 kΩ R3 = 249 Ω With the above selected values, we get the following zeros and poles for the compensation network: ωzero_1 → 11.7 kHz ωpole_1 → 1.15 MHz ωzero_2 → 11.3 kHz ωpole_2 → 1.15 MHz The Bode diagram for the complete loop is shown in Figure 8. The gain rolls off with -20 db/decade at the selected crossover frequency of 150 kHz and the phase margin is always more than 45° for the range below the crossover frequency. Figure 8. Frequency Response and Phase Margin for Complete System Loop AN4661 Application Note Rev. 1.0 10/2013 8 Freescale Semiconductor, Inc. Conclusion 8 Conclusion This application note shows how to design the proper compensation network for the VCORE error amplifier of the MC33907 and MC33908. This compensation network has to be adjusted for different output voltages as well for different LC filters. The sharp phase lag caused by low ESR capacitors at the output always requires a type 3 compensation network. Note: It is recommended to verify the calculated results with a tool like Spice or a mathematical program. AN4661 Application Note Rev. 1.0 10/2013 Freescale Semiconductor, Inc. 9 . References 9 References Author Pressmann, A., K. Billings and T. Morey Title, Publisher and Date Switching Power Supply Design. New York: McGraw-Hill, 2009. AN4661 Application Note Rev. 1.0 10/2013 10 Freescale Semiconductor, Inc. Revision History 10 Revision History Revision 1.0 Date 10/2013 Description of Changes • Initial release AN4661 Application Note Rev. 1.0 10/2013 Freescale Semiconductor, Inc. 11 . How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Home Page: freescale.com products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no circuits based on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2013 Freescale Semiconductor, Inc. Document Number: AN4661 Rev. 1.0 10/2013

- Similar pages