MC33903_4_5FS, System Basis Chip Gen2 with High Speed CAN and LIN Interface

Analog, Mixed-Signal and Power Management
MC33903/4/5
System Basis Chip Gen2 with High Speed CAN and
LIN Interface
Overview
The MC33903/4/5 is the second generation
family of System Basis Chips, which combine
several features and enhance present module
designs. The device works as an advanced
power management unit for the MCU and
additional integrated circuits such as sensors
and CAN transceivers. It has a built-in enhanced
high speed CAN interface (ISO11898-2 and -5),
with local and bus failure diagnostics, protection,
and fail safe operation mode. The SBC may
include one or two LIN 2.1/J2602-2 interfaces
with LIN master terminal outputs. It includes
wake-up input pins than can also be configured
as output drivers for flexibility.
This device implements multiple Low Power
modes with very low-current consumption. In
addition, the device is part of a family concept
where pin compatibility, among the various
devices with and without LIN interfaces, adds
versatility to module design.
The MC33903/4/5 also implements an
innovative and advanced fail-safe state machine
and concept solution. This family of devices are
supported by an enablement ecosystem that
includes an evaluation board, software interface,
EMC/ESD conformance reports and training
material that allows a faster time to market and
eases your designs.
MC33903/4/5 Block Diagram
MCU Voltage Regulator (VDD)
Internal CAN Regulator (VCAN)
Legend
Low Power Modes
SPI Adv W/D
Flexible (I/O)
33903
33903S
33903D
Secured State Machine
CAN High Speed
33904
33905S
Power Sharing (VDD BALLAST)
33905D
Ballast Regulator (VAUX)
LIN 1
LIN 2
Power Management Scalability
• MCU power supply (VDD): 5.0 or 3.3 V /
150 mA (power split option for scalable
needs - up to 300 mA)
• 5.0 or 3.3 V voltage regulator (VAUX) for
auxiliary loads
• Dedicated 5.0 V voltage regulator (5 V
CAN) for High Speed CAN
Functional Safety
• Innovative cranking pulse management
during VDD low
• Fail safe & configurable state machine
• Enhanced protections and diagnostics
Energy Savings
• Ultra low power modes (typ 15 µA with
VDD off)
• Innovative Wake-up management and
cyclic sense capability
Robust Physical Layers
• Certification to LIN 2.1, J2602-2, and
ISO11898-2-5 standards
• Successfully certified for stringent EMC,
ISO, and ESD standards
Easy to Use
• Ecosystem to lower development time and
simplify access
• Debug mode to save time during
application development
Flexibility & Compatibility:
• Selectable parameters (RST time, W/D
type, VDD under-voltage threshold, VAUX
3.3 or 5.0 V)
• 1 or 2 LIN options (33903S, 33905S and
33903D, 33905D)
• Scalable (I/O pins configurable as wake-up
inputs or output LIN master terminations)
IDEAL COMPANION CHIP FOR MCU IN BODY, SAFETY, AND POWERTRAIN APPLICATIONS
Segment
Applications
Proposed FSL MCU
Body
Body Controller
S12x, MPC560x
Gateway
Seat Module
Door Module
Lighting Control Module
S12x, MPC560x, S08x
Column Module
HVAC
Cluster
Safety & Chassis
Seat Belt Pre-tensioner
Electric Parking Brake
S12x, MPC560x
Steering
Power Train
Fuel Pump
Water Pump
S12x, S08x
Glow Plug
Engine Management Low End
S12x, MPC563x
Key Characteristics
Parameter
Characterization
MCU Linear VREG (LDO)
5.0 / 3.3 V
Output Current
(300 mA for 33903D/S, 33904, 33905D/S with optional external PNP implementation)
Bus Output
CAN
33903D/S, 33905D/S only
LIN
Data Rate
CAN
40 kB/s – 1.0 MB/s
LIN
10.4 kB/s – 20 kB/s (100 kB/s in fast mode)
Low Power VDD OFF/ VDD ON Current
15/25 µA
ESD - Module Level (CAN and LIN)
±8000 V
Operating Voltage
5.5 - 28 V
Maximum Input Voltage
27 VDC, 40 V (Load Dump)
Operating Temperature
-40 °C<TA<125 °C
MC33905D Simplified Application Drawing
VBAT
Q2
D1
Features
Q1
(5.0 V/3.3 V)
VCAUX VAUX VSUP1
VBAUX
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
VDD
5 V Auxiliary
Regulator
VSUP2
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
VB
VE
VDD Regulator
• Under-voltage management for cranking
VS2-INT
SAFE
Fail-safe
Power Management
DBG
State Machine
Oscillator
GND
SPI
INT
• Low current consumption in sleep mode
MOSI
• Fail safe state machine linked with SAFE pin
SCLK
VS2-INT
Configurable
Input-Output
Enhanced High-speed CAN
Physical Interface
SPLIT
CAN Bus
LIN Bus
LIN-TERM1
LIN-1
5V-CAN
5 V-CAN
Regulator
I/O-1
CANH
• High precision VSUP sense monitoring
MUX-OUT
Signals Condition & Analog MUX
I/O-0
• Secured SPI with Watchdog capability
MISO
CS
Analog Monitoring
VSENSE
CANL
• Internal 5.0 V regulator for CAN driver supply
RST
TXD
RXD
VS2-INT
TXD-L1
LIN Interface - #1
RXD-L1
• Multiple Analog sensing to 1 MUX output
• Dual configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved VSUP slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
• 2 LIN transceivers - 2.0, 2.1, and SAE J2602-2 compliant
VS2-INT
TXD-L2
LIN Bus
LIN Interface - #2
LIN-TERM2
RXD-L2
LIN-2
VDD output
voltage
Freescale Part Number
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
VAUX
VSENSE
MUX
Package
2
2 wake-up + 2 LIN terms
or
3 wake-up + 1 LIN terms
or
4 wake-up + no LIN terms
Yes
Yes
Yes
SOIC 54 pins
exposed pad
Yes
Yes
Yes
SOIC 32 pin
exposed pad
MC33905D (Dual LIN)
MCZ33905BD3EK/R2
3.3 V
MCZ33905CD3EK/R2
MCZ33905D5EK/R2
1
MCZ33905BD5EK/R2
5.0 V
MCZ33905CD5EK/R2
MC33905S (Single LIN)
MCZ33905BS3EK/R2
3.3 V
MCZ33905CS3EK/R2
3 Wake-up + 1 LIN terms
MCZ33905S5EK/R2
1
MCZ33905BS5EK/R2
1
or
4 Wake-up + no LIN terms
5.0 V
MCZ33905CS5EK/R2
MC33905S Simplified Application Drawing
VBAT
Q2
D1
Features
Q1
(5.0 V/3.3 V)
VCAUX VAUX VSUP1
VBAUX
VSUP2
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
VE VB
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
5 V Auxiliary
Regulator
VDD Regulator
VDD
• Under voltage management for cranking
RST
• Internal 5.0 V regulator for CAN driver supply
VS2-INT
SAFE
Fail-safe
Power Management
DBG
GND
INT
Oscillator
SPI
SCLK
MISO
CS
Analog Monitoring
VSENSE
MOSI
State Machine
Signals Condition & Analog MUX
MUX-OUT
Configurable
Input-Output
I/O-1
5 V-CAN
Regulator
5V-CAN
I/O-3
CANH
Enhanced High-speed CAN
Physical Interface
SPLIT
CAN Bus
TXD
RXD
CANL
LIN-T
LIN
• Secured SPI with Watchdog capability
• High precision VSUP sense monitoring
• Triple configurable I/O with W/U feature
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved VSUP slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN, ISO11898-2 and 11898-5 compliant
VS2-INT
LIN Term
LIN Bus
• Fail safe state machine linked with SAFE pin
• Multiple Analog sensing to 1 MUX output
VS2-INT
I/O-0
VBAT
• Low current consumption in sleep mode
TXD-L
LIN Interface
RXD-L
• 1 LIN transceiver - 2.0, 2.1, and SAE J2602-2 compliant
MC33904 Simplified Application Drawing
Features
VBAT
Q2
D1
Q1
(5.0 V/3.3 V)
VCAUX VAUX VSUP1
VBAUX
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional external ballast
transistor
VE VB
• LDO Auxiliary Regulator with ballast transistor (5.0 / 3.3 V configurable)
5 V Auxiliary
Regulator
VSUP2
VDD Regulator
VDD
• Under-voltage management for cranking
RST
• Internal 5.0 V regulator for CAN driver supply
VS2-INT
SAFE
Fail Safe
Power Management
DBG
State Machine
Oscillator
GND
SPI
Analog Monitoring
Configurable
Input-Output
I/O-2
I/O-3
CANH
VS2-INT
• Secured SPI with Watchdog capability
• High precision VSUP sense monitoring
5V-CAN
Regulator
Enhanced High Speed CAN
Physical Interface
SPLIT
• Fail safe state machine linked with SAFE pin
SCLK
MUX-OUT
Signals Condition & Analog MUX
I/O-0
I/O-1
• Low current consumption in sleep mode
MOSI
MISO
CS
VSENSE
VBAT
INT
5V-CAN
• Quad configurable I/O with W/U feature
TxD
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved VSUP slow ramp up behavior, enhanced device current
consumption, and improved oscillator
RXD
• CAN transceiver: ISO11898-2 and 11898-5 compliant
CANL
CAN Bus
Freescale Part Number
VDD output
voltage
• Multiple Analog sensing to 1 MUX output
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
VAUX
VSENSE
MUX
Package
1
0
4 Wake-up
Yes
Yes
Yes
SOIC 32 pins
exposed pad
MC33904
MCZ33904B3EK/R2
3.3 V
MCZ33904C3EK/R2
MCZ33904A5EK/R2
MCZ33904B5EK/R2
5.0 V
MCZ33904C5EK/R2
MC33903 Simplified Application Drawing
Features
VSUP1
• LDO Linear Power Supply 5.0 or 3.3 V
VDD Regulator
VSUP2
VS-INT
SAFE
Power Management
State Machine
DBG
GND
I/O-0
SPI
• VDD does not allow usage of an external PNP on the 33903. Output current limited to
150 mA
RST
• Under-voltage management for cranking
INT
• Internal 5.0 V regulator for CAN driver supply
MOSI
• Low current consumption in sleep mode
SCLK
• Fail safe state machine linked with SAFE pin
MISO
CS
Oscillator
Configurable
Input-Output
VDD
VS-INT
• Configurable I/O with W/U feature
5 V-CAN
Regulator
5 V-CAN
CANH
SPLIT
Enhanced High Speed CAN
Physical Interface
TxD
RXD
CANL
Freescale Part Number
• Secured SPI with Watchdog capability
VDD output
voltage
• “B” versions are recommended for new designs. Changes implemented on “B”
versions: resolved VSUP slow ramp up behavior, enhanced device current
consumption, and improved oscillator
• CAN transceiver: ISO11898-2 and 11898-5 compliant
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
VAUX
VSENSE
MUX
Package
1
0
1 Wake-up
No
No
No
SOIC 32 pins
exposed pad
MC33903
MCZ33903B3EK/R2
3.3 V
MCZ33903C3EK/R2
MCZ33903B5EK/R2
MCZ33903C5EK/R2
5.0 V
MC33903D Simplified Application Drawing
VSUP
VE
Features
VB
VS2-INT
• Under-voltage management for cranking
SAFE
Fail-safe
Power Management
DBG
State Machine
Oscillator
GND
VSENSE
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional
external ballast transistor
VDD
VDD Regulator
RST
• Internal 5.0 V regulator for CAN driver supply
INT
• Low current consumption in sleep mode
MOSI
• Fail safe state machine linked with SAFE pin
SCLK
SPI
• Secured SPI with Watchdog capability
MISO
CS
Analog Monitoring
• High precision VSUP sense monitoring
• Multiple Analog sensing to 1 MUX output
Signals Condition & Analog MUX
MUX-OUT
• Configurable I/O with W/U feature
VS2-INT
IO-0
Configurable
Input-Output
5 V-CAN
Regulator
5 V-CAN
• “B” versions are recommended for new designs. Changes implemented on
“B” versions: resolved VSUP slow ramp up behavior, enhanced device
current consumption, and improved oscillator
TXD
• CAN, ISO11898-2 and 11898-5 compliant
RXD
• 2 LIN transceivers - 2.0, 2.1, and SAE J2602-2 compliant
CANH
Enhanced High-speed CAN
Physical Interface
SPLIT
CANL
VS2-INT
TXD-L1
LIN 2.1 Interface - #1
LIN-T1
LIN-1
RXD-L1
VS2-INT
TXD-L2
LIN-T2
LIN 2.1 Interface - #2
RXD-L2
LIN-2
VDD output
voltage
Freescale Part Number
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
VAUX
VSENSE
MUX
Package
No
Yes
Yes
SOIC 32 pins
exposed pad
MC33903D (Dual LIN)
MCZ33903BD3EK/R2
1 wake-up + 2 LIN terms
3.3 V
MCZ33903CD3EK/R2
1
MCZ33903BD5EK/R2
2
or
3 wake-up + no LIN terms
5.0 V
MCZ33903CD5EK/R2
or
2 wake-up + 1 LIN terms
MC33903S Simplified Application Drawing
VSUP
VS-INT
Features
VE VB
VDD
VDD Regulator
• LDO Linear Power Supply 5.0 or 3.3 V, up to 300 mA with an optional
external ballast transistor
• Under-voltage management for cranking
SAFE
Fail Safe
Power Management
DBG
GND
Oscillator
VSENSE
State Machine
SPI
RST
• Internal 5.0 V regulator for CAN driver supply
INT
• Low current consumption in sleep mode
MOSI
• Fail safe state machine linked with SAFE pin
SCLK
MISO
CS
Analog Monitoring
• Secured SPI with Watchdog capability
• High precision VSUP sense monitoring
• Multiple Analog sensing to 1 MUX output
Signals Condition & Analog MUX
MUX-OUT
• Configurable I/O with W/U feature
5 V-CAN
• “B” versions are recommended for new designs. Changes implemented on
“B” versions: resolved VSUP slow ramp up behavior, enhanced device
current consumption, and improved oscillator
VS-INT
I/O-0
Configurable
Input-Output
I/O-3
5 V-CAN
Regulator
• CAN, ISO11898-2 and 11898-5 compliant
CANH
Enhanced High Speed CAN
Physical Interface
SPLIT
CANL
TXD
RXD
VS-INT
LIN-T
LIN
LIN Term #1
TXD-L
LIN 2.1 Interface - #1
RXD-L
• 1 LIN transceiver - 2.0, 2.1, and SAE J2602-2 compliant
Freescale Part Number
VDD output
voltage
CAN
interface
LIN
interface(s)
I/O Wake-up Capability
VAUX
VSENSE
MUX
Package
1
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
SOIC
32 pin
expose
d pad
No
Yes
Yes
0
3 Wake-up
SOIC
32 pin
expose
d pad
No
Yes
Yes
MC33903S (Single LIN)
MCZ33903BS3EK/R2
B
MCZ33903CS3EK/R2
C
MCZ33903BS5EK/R2
B
MCZ33903CS5EK/R2
C
3.3 V
5.0 V
MC33903P
MCZ33903CP5EK/R2
MCZ33903CP3EK/R2
5.0 V
C
3.3 V
MC33903, MC33904, AND MC33905 KEY FEATURES AND BENEFITS
Features
Benefits
Ecosystem
Easy-to-Use Ecosystem
•
•
•
•
Faster time to market.
EVB + SW interface to ease SBC usage & programming.
Electrical and EMC/ESD conformance reports.
Training material.
Ultra Low Power Modes
• Best-in-class quiescent current down to 15 µA including LIN and
CAN wake-up active.
• Reduces contribution of active blocks during stand-by mode.
Innovative Wake-up Event
• Save time during cyclic check by reducing the number of state
machine transitions. This contributes in reducing overall ECU
energy consumption (Energy = Current x Time).
Scalable Power Supply
• Enables platform solution (150 mA internal supply, or up to
300 mA with an optional ballast transistor).
Flexible Fail Safe Modes
• Flexibility to address the ECU functional safety assessment and
program the default fail safe behavior via hardware
implementation.
Secured SPI
• Fast SPI access – higher frequency combined with new register
addressing methodology to save time.
• Parity checks.
Innovative Cranking Pulse
Management
• System alternative to save customer cost (PCB space, cost of
capacitor) while keeping some degraded functionalities during
cranking mode.
Advanced Watchdog
• Improved, safer and optional Watchdog (in addition to time-out
and window watchdog) implemented to avoid unpredictable
Watchdog recognition, so that closed loop MCU activity can be
detected.
Ease Customer Debug Mode
• The DBG pin is used to inhibit the watchdog during debug mode.
This helps hardware and software designers save time during
application development.
Certification and Car OEM
Approval Process
• LIN and CAN HS P/L meets conformance tests and EMC/ESD
standard requirements to secure the customer design
Energy Management
System Management
Robust Physical Layers
Development Tools
Part Number
Description
KIT33903BD3EVBE
Evaluation board to demonstrate the key features of the MC33903
KIT33903BD5EVBE
Evaluation board to demonstrate the key features of the MC33903
KIT33905BD3EVBE
Evaluation board to demonstrate the key features of the MC33903/4/5
KIT33905D5EKEVBE
Evaluation board to demonstrate the key features of the MC33903/4/5
Documentation
Document Number
Title
Description
MC33903_4_5
Data Sheet
Presents the specifications for the product
SG1002
Selector Guide
Analog and power management device comparison
SG187
Selector Guide
Automotive device comparison
Questions
• Are you looking for an automotive certified
High Speed CAN and LIN Physical Layer
integrated on a single chip SBC?
• What is the maximum current capability of
your MCU?
• Do you need to implement very low
application quiescent current?
• How many wake-up sources are required
by your system?
• Do you need to monitor bus failures during
network communications?
• What battery voltage range is required by
your system? What is the application
behavior expected during cranking pulse?
Freescale Semiconductor is a leading provider
for over 25 years of high-performance products
using SMARTMOS technology that combines
digital, power and standard analog functions.
The company supplies analog and power
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management ICs for the automotive, consumer,
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analog and power ICs complement our broad
portfolio of micro controllers, microprocessors,
ZigBee® technology, digital signal processors,
sensors, with development tools and support to
provide system solutions to customers.
• Do you need continuous system
monitoring (temperature, battery voltage,
inputs signals,...)?
• What are the safety level requirements of
your application? Do you need external
components to monitor your MCU
(watchdog,...)?
• How many regulator outputs, and what
logic voltage levels are required by your
system (3.3 or 5.0 V)?
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Document Number: MC33903_4_5FS, Rev. 6.0