74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state Rev. 05 — 25 March 2010 Product data sheet 1. General description The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, but has a different pin arrangement. 2. Features and benefits Balanced propagation delays All inputs have a Schmitt trigger action Common 3-state output enable input Functionally identical to the 74AHC373; 74AHCT373 Inputs accept voltages higher than VCC Input levels: For 74AHC573: CMOS input level For 74AHCT573: TTL input level ESD protection: HBM EIA/JESD22-A114E exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC573D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHC573PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHC573BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 74AHCT573D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHCT573PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHCT573BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 74AHC573 74AHCT573 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 3-STATE OUTPUTS Q3 16 Q4 15 11 LE 1 OE mna809 Fig 1. Functional diagram 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 11 C1 1 1 2 3 4 5 6 7 8 9 2 OE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 Fig 2. 3 18 4 17 16 5 16 15 6 15 14 7 14 8 13 9 12 17 13 12 mna807 mna808 Logic symbol Fig 3. D0 D1 D Q D2 D 19 1D 18 LE 11 EN1 Q D3 D Q IEC logic symbol D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig 4. Logic diagram 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 5. Pinning information 5.1 Pinning 1 OE terminal 1 index area D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 D5 7 14 Q5 D4 6 D6 8 13 Q6 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 D7 9 12 Q7 GND 10 11 LE 15 Q4 GND 10 573 LE 11 OE 001aal532 Transparent top view 001aad099 Fig 5. 20 VCC 74AHC573 74AHCT573 Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) LE 11 latch enable (active HIGH) Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output VCC 20 supply voltage 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 6. Functional description Table 3. Function table[1] Operating mode Input Internal latch Output OE LE Dn Enable and read register (transparent mode) L H L H H H Latch and read register L L l L L h H H l L Z h H Z Latch register and disable outputs [1] H L Qn L L H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit −0.5 +7.0 V −0.5 +7.0 V IIK input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) ICC supply current - IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] −20 - mA −20 +20 mA −25 +25 mA +75 mA [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V 74AHC573 VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT573 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C Δt/ΔV input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Typ Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - - V VCC = 2.0 V - - 0.5 - 0.5 - - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - - V IO = −50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - - V IO = −50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - - V LOW-level VI = VIH or VIL output voltage IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - - 0.1 V IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - - 0.1 V IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - - 0.55 V 74AHC573 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Min Typ Max Min Max Min Typ Unit Max IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V - - ±0.25 - ±2.5 - - II input leakage current - - 0.1 - 1.0 - - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - - 80 μA CI input capacitance - 3 10 - 10 - - 10 pF CO output capacitance - 4 - - - - - 10 pF VI = VCC or GND; VCC = 0 V to 5.5 V VI = VCC or GND ±10.0 μA 74AHCT573 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 μA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 μA IO = 8.0 mA 4.4 4.5 - 4.4 - 4.4 - - V 3.94 - - 3.80 - 3.70 - - V - 0 0.1 - 0.1 - - 0.1 V V - - 0.36 - 0.44 - - 0.55 IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - ±0.25 - ±2.5 - - ±10.0 μA II input leakage current - - 0.1 - 1.0 - - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - - 80 μA ΔICC additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - - 1.5 mA CI input capacitance - 3 10 - 10 - - 10 pF CO output capacitance - 4 - - - - - 10 pF 74AHC_AHCT573_5 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = VCC or GND All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 5.5 11.0 1.0 13.0 1.0 14.0 ns CL = 50 pF - 7.8 14.5 1.0 16.5 1.0 18.5 ns - 3.9 6.8 1.0 8.0 1.0 8.5 ns - 5.5 8.8 1.0 10.0 1.0 11.0 ns CL = 15 pF - 5.8 11.9 1.0 14.0 1.0 15.0 ns CL = 50 pF - 8.3 15.4 1.0 17.5 1.0 19.5 ns - 4.2 7.7 1.0 9.0 1.0 10.0 ns - 5.9 9.7 1.0 11.0 1.0 12.5 ns CL = 15 pF - 5.8 11.5 1.0 13.5 1.0 14.5 ns CL = 50 pF - 8.3 15.0 1.0 17.0 1.0 19.0 ns CL = 15 pF - 4.4 7.7 1.0 9.0 1.0 10.0 ns CL = 50 pF - 6.3 9.7 1.0 11.0 1.0 12.5 ns CL = 15 pF - 6.8 11.0 1.0 13.0 1.0 14.0 ns CL = 50 pF - 9.7 14.5 1.0 16.5 1.0 18.5 ns CL = 15 pF - 4.6 7.7 1.0 9.0 1.0 10.0 ns CL = 50 pF - 7.4 9.7 1.0 11.0 1.0 12.5 ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns VCC = 4.5 V to 5.5 V 3.5 - - 3.5 - 3.5 - ns 74AHC573 tpd propagation delay Dn to Qn; see Figure 7 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF LE to Qn; see Figure 8 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 [3] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tdis disable time OE to Qn; see Figure 9 [4] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW tsu pulse width set-up time 74AHC_AHCT573_5 Product data sheet LE HIGH; see Figure 8 Dn to LE; see Figure 10 All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter th CPD hold time power dissipation capacitance 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns VCC = 4.5 V to 5.5 V 1.5 - - 1.5 - 1.5 - ns - 12 - - - - - pF - 3.5 5.5 1 6.5 1 7.0 ns - 4.9 7.5 1 8.5 1 9.5 ns - 3.9 6.0 1 7.0 1 7.5 ns - 5.5 8.5 1 9.5 1 11.0 ns - 4.1 6.5 1 7.5 1 8.5 ns - 5.9 8.5 1 10.0 1 11.0 ns Dn to LE; see Figure 10 [5] fi = 1 MHz; VI = GND to VCC 74AHCT573; VCC = 4.5 V to 5.5 V tpd propagation delay Dn to Qn; see Figure 7 [2] CL = 15 pF CL = 50 pF LE to Qn; see Figure 8 [2] CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 [3] CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 9 [4] CL = 15 pF - 4.5 6.5 1 7.5 1 8.5 ns CL = 50 pF - 6.4 9.0 1 10.0 1 11.5 ns tW pulse width LE HIGH; see Figure 8 5.0 - - 5.0 - 5.0 - ns tsu set-up time Dn to LE; see Figure 10 3.5 - - 3.5 - 3.5 - ns th hold time Dn to LE; see Figure 10 1.5 - - 1.5 - 1.5 - ns CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC - 18 - - - - - pF [5] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPHL and tPLH. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 11. Waveforms VI VM Dn input GND tPLH tPHL VOH VM Qn output mna811 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Data input to output propagation delays 1/fmax VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL mna812 VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Latch enable input to output propagation delays 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state VI OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY Qn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled mna813 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times VI VM Dn input GND th th t su t su VI LE input VM GND mna814 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 10. Data set-up and hold times Table 8. Measurement points Type Input Output VM VM VX VY 74AHC573 0.5 × VCC 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74AHCT573 1.5 V 0.5 × VCC VOL + 0.3 V VOH − 0.3 V 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC G VI VCC VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. S1 = test selection switch. Fig 11. Test circuitry for switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC573 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT573 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 12 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT163-1 (SO20) 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 14 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 14. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 15 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT573_5 20100325 Product data sheet - 74AHC_AHCT573_4 74AHC_AHCT573_4 20100303 Product data sheet - 74AHC_AHCT573_3 Modifications: • Added type numbers 74AHC573BQ and 74AHCT573BQ (DHVQFN20 / SOT764-1 package). 74AHC_AHCT573_3 20080424 Product data sheet - 74AHC_AHCT573_2 74AHC_AHCT573_2 20031208 Product specification - 74AHC_AHCT573_1 74AHC_AHCT573_1 19990927 Product specification - - 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 16 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74AHC_AHCT573_5 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 17 of 19 74AHC573; 74AHCT573 NXP Semiconductors Octal D-type transparant latch; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT573_5 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 25 March 2010 © NXP B.V. 2010. All rights reserved. 18 of 19 NXP Semiconductors 74AHC573; 74AHCT573 Octal D-type transparant latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 March 2010 Document identifier: 74AHC_AHCT573_5