Design and application guidelines for the COG LCD drivers PCF8538 and PCA8538

AN11491
Design and application guidelines for the COG LCD drivers
PCF8538 and PCA8538
Rev. 1 — 9 January 2014
Application note
Document information
Info
Content
Keywords
PCA8538, PCF8538, LCD driver, segment driver, LCD, Liquid Crystal
Display, COG, Chip-On-Glass, TN, Twisted Nematic, STN, Super
Twisted Nematic, VA, Vertical Alignment
Abstract
The PCF8538 and PCA8538 are fully featured Chip-On-Glass (COG)
Liquid Crystal Display (LCD) drivers, designed for high-contrast Vertical
Alignment (VA) LCDs with multiplex rates up to 1:9. They generate the
drive signals for a static or multiplexed LCD containing up to 9
backplanes, 102 segments, and up to 918 elements. They feature an
internal charge pump with internal capacitors for on-chip generation of the
LCD driving voltage. This application note provides additional information
about using these drivers.
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Design guidelines for PCF8538 and PCA8538
Revision history
Rev
Date
Description
1
Initial release
20140109
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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1. Introduction
The PCF8538 and PCA8538 are fully featured Chip-On-Glass (COG) Liquid Crystal
Display (LCD) drivers, designed for high-contrast Vertical Alignment (VA) LCD with
multiplex rates up to 1:9. They generate the drive signals for a static or multiplexed LCD
containing up to 9 backplanes, 102 segments, and up to 918 elements. They feature an
internal charge pump with internal capacitors for on-chip generation of the LCD driving
voltage. To ensure an optimal and stable contrast over the full temperature range, the
PCF8538 and PCA8538 offer a programmable temperature compensation of the LCD
supply voltage. They can be easily controlled by a microcontroller through either the two2
line I C-bus or a four-line bidirectional SPI-bus.
The PCF8538U is qualified for industrial and consumer applications; the PCA8538U is
qualified according the AEC-Q100 grade 2 standard that makes the product suitable for
automotive applications. For further information please refer to the appropriate data
sheets.
This application note provides additional information about using these drivers. In the
remainder of this document, PCF8538 and PCA8538 are also referred to as PCx8538.
2. Display technologies which can be driven
The PCF8538U and the PCA8538U are suitable to drive any monochrome LCD
technology like TN (Twisted Nematic) and STN (Super Twisted Nematic), including also
the newer Vertical Alignment (VA) displays, which impose stricter requirements on the
driver.
Vertical Alignment is a display technology in which the liquid crystals naturally align
vertically to the glass substrates. When no voltage is applied, the liquid crystals remain
perpendicular to the substrate creating a black display between crossed polarizers; when
a voltage is applied, the liquid crystals shift to a horizontal position allowing light to pass
through and create a white display image. Compared to the traditional TN displays, VA
displays have a deeper black background, a much higher contrast ratio, a much wider
viewing angle and better image quality at extreme temperatures.
This display technology is particularly well suited for applications where the display is:
•
exposed to sunlight, i.e. needs to be sunlight readable
•
mounted on an otherwise black background, e.g. in instrument clusters in a car
•
located sideways from the viewer, e.g. in the centre stack of a car, and thus
needs to be viewable under a wide angle. VA displays are in growing demand for
both automotive and non-automotive applications.
Compared to TN and STN displays, the VA display technologies have different
requirements with respect to the drive signals, mainly in terms of higher LCD supply
voltage VLCD and higher frame frequency. In order to meet these requirements and to be
able to drive the VA displays, the PCF8538U and the PCA8538U have been designed
with higher VLCD which is programmable up to 12 V, and higher frame frequency,
programmable up to 300 Hz.
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3. Possible display configurations
The PCF8538U and the PCA8538U are suitable to drive any display, containing up to
918 elements. The display configurations possible depend on the number of active
backplane outputs (commons) required. A selection of possible display configurations is
given in Table 1.
Table 1.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/characters
7-segment
14-segment
Dot matrix/
Elements
9
918
114
57
918 dots (9 x 102)
8
816
102
51
816 dots (8 x 102)
6
612
76
38
612 dots (6 x 102)
4
408
51
25
408 dots (4 x 102)
2
204
25
12
204 dots (2 x 102)
1 (static mode)
102
12
6
102 dots (1 x 102)
Some examples are shown below.
3.1 Dot matrix display
The PCF8538U and the PCA8538U can drive a dot matrix display up to 9 x 102 dots.
See Fig 1.
Example, not full number of columns shown.
Fig 1.
Dot matrix display
3.2 Dot matrix displays with icons
The PCF8538U and the PCA8538U can drive a dot matrix display that includes also
some icons or segments, according to the specific applications. The total number of
display elements (icons, segments and dots) is up to 918. This is illustrated in Fig 2.
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Fig 2.
Dot matrix with segments
3.3 Segmented displays
The PCF8538U and the PCA8538U can drive a segmented display up to 918 segments.
The example below shows a display where a considerable number of segments is used,
along with a small dot-matrix section. This display is used on the demo board, refer to
section 9, demo board.
Segmented display, also with a dot matrix section
Fig 3.
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Mainly segmented display
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4. Maximum display size that can be driven
In this section, an estimation of the maximum display element dimensions (pixel, icon,
segment) that can be used in conjunction with the PCx8538 is discussed. The display
size is related to this. Given the maximum size of a display element and the number of
display elements, the display size can be derived.
The maximum size of the display elements that can be driven by the PCF8538U or the
PCA8538U depends not only on the driver but also on the display characteristics. The
relevant parameters are the following:
•
The output resistance of the LCD driver outputs (segment and
backplane/common outputs)
•
The segment and backplane ITO track resistances
•
The capacitance of the display element
The various parameters are indicated in Fig 4.
Fig 4.
Driver output stages with resistances and display capacitance
Note: The calculations given in this example are valid for the PCF8538 and PCA8538.
However, the way of working is universal and can be used to determine the maximum
display element size that can be driven by any LCD driver. Obviously, the parameter
values must be adapted to the actual values.
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4.1 The output resistance of the LCD outputs
The output resistances of the PCx8538U are specified as follows:
•
Ro (SEG) = 2.5 kΩ (typ.)
•
Ro (COM) = 1.0 kΩ (typ.)
4.2 Segment and common ITO track resistances
The segment and common ITO track resistances depend on the module design. Factors
determining the resistance are length and width of the tracks and the sheet resistance
(square resistance) of the ITO, which can be influenced by varying the thickness.
For the segment ITO track, the following assumptions are made:
•
One bump per segment; bump pitch: 45 µm
•
SEG ITO track width: 45 µm
•
SEG ITO track length: 70 mm (worst case)
•
SEG ITO number of squares: 1555
•
R(ITO) = 15 Ω / square
•
RSEG(ITO) = 23.3 kΩ
For the common ITO track, the following assumptions are made:
•
Two bumps per segment; bump pitch: 90 µm
•
COM ITO track width: 500 µm
Note: Typically, there is much more space available for a common track than for
a segment track.
•
COM ITO track length: 150 mm (worst case)
•
COM ITO number of squares: 300
•
R(ITO) = 15 Ω / square
•
RCOM(ITO) = 4.5 kΩ
Actual track length may be much less, which will have a positive influence on the display
size that can be driven.
Note that the LCD drive section includes nine backplane outputs: COM0 to COM8. The
backplanes are double implemented (two sets of outputs) to offer a higher flexibility for
the glass layout. If the correspondent COM outputs are connected together, the drive
strength will be further increased.
4.3 Pixel capacitance
The pixel capacitance depends on the display technology, the liquid used, the pixel size
and on the state (ON or OFF). A display manufacturer could provide the value of the
display capacitance per mm2 or the value of the total display capacitance, and then the
average pixel capacitance can be derived.
A pixel capacitance of 10 pF / mm2 is a realistic value.
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4.4 Drive capability
A display element forms a capacitor, and it must be charged and discharged when
switching ON and OFF. As a rule of thumb, the actual waveform should be at 95% of its
value within 10 % of the selection time slot, which is the pulse width. Considering the
default case (multiplex mode 1:9, bias mode ¼, line inversion and frame frequency equal
to 80 Hz), the selection time slot is equal to the frame period divided by 18, see Fig 5,
that is about 694 µs. In general, the selection time slot is equal to the frame frequency
divided by the multiplex rate n.
The total cell capacitance is hard to estimate due to the display appearing as a network,
with many resistances and capacitances. A segment output will only drive a small portion
of the display whereas a common output drives a much larger portion of the display.
Therefore it is necessary to look at the drive capability separately.
More in to detail:
3 × RSEG ( tot ) × C ≤ 10% × 694 µs = 69.4 µs
(1)
3 × RCOM ( tot ) × C × N ≤ 10% × 694 µs = 69.4 µs
(2)
Where:
•
RSEG(tot) is the total output resistance of each segment output, which is the sum of
the on-chip output resistance of the segment output driver (see section 4.1) plus
the resistance of the segment ITO track (see section 4.2); that is:
RSEG(tot) = 2.5 kΩ + 23.3 kΩ = 25.8 kΩ (typ.);
•
RCOM Tot. is the total output resistance of each common output, which is the sum
of the on-chip output resistance of the common output driver (see section 4.1)
plus the resistance of the common ITO track (see section 4.2); that is:
RCOM(tot) = 1.0 kΩ + 4.5 kΩ = 5.5 kΩ (typ.);
•
N is the total number of segments per each common line, here that is 102;
•
C is the pixel capacitance.
From equation (1):
C ≤ 69.4 µs / (3 × RSEG ( tot ) ) = 69.4 µs / 77.4 kΩ = ~ 900 pF
(3)
From equation (2):
C ≤ 69.4 µs / (3 × RCOM ( tot ) × 102 ) = 69.4 µs / 1683 kΩ = ~ 41 pF
(4)
From equations (3) and (4) follows that the maximum pixel capacitance is about 41 pF.
However, considering the tolerance of the semiconductor process as well as the
tolerance of the ITO track resistance, it is assumed that RCOM(tot) = 8 kΩ (max.). Using this
value instead of the typical value of 5.5 kΩ, equation (4) is rewritten as follows:
C ≤ 69.4 µs / (3 × RCOM Tot × 102 ) = 69.4 µs / 2448 kΩ = ~ 28.35 pF
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Vstate1(t) = VSn(t) – VBP0(t).
(1) Vstate2(t) = VSn + 1(t) – VBP0(t).
Fig 5.
Von(RMS)(t) = 0.408VLCD.
VOFF(RMS)(t) = 0.289VLCD
Waveforms for 1:9 multiplex drive mode with ¼ bias and line inversion (n = 1)
Assuming a pixel capacitance of 10 pF / mm2 (see Section 4.3), the maximum area of the
display element to be driven is about 2.835 mm2.
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For a segmented LCD, where there are different display elements with different sizes and
thus different capacitances, the driving capability is better expressed as the maximum
capacitance or maximum area of the display element that can be driven:
•
Maximum pixel area: 2.835 mm2.
This information is transferred into the maximum display area if a pure dot matrix display
is considered, where all display elements have the same size:
•
Maximum dot size: 1.684 mm x 1.684 mm
•
Gap between dots: 0.05 mm
•
Maximum X size: (1.684 + 0.05) x 102 = 177 mm
•
Maximum Y size: (1.684 + 0.05) x 9 = 15.6 mm
•
Maximum D size: ~178 mm = ~7 inches.
With all the above reasonable assumptions, the PCF8538U (or PCA8538U) can safely
drive a 7” display (17.8 cm).
When the display driver is used at lower multiplex rates, the selection time is longer and
therefore larger display elements can be driven. Also lowering the frame frequency from
the 80 Hz value used in this example, will allow larger displays.
It is recommended to maximize the ITO track width in order to keep the resistance as low
as possible. Furthermore it is recommended to balance the resistances:
•
Layout the display such that the spread on the various RCOM is minimized (about
equal values)
•
Layout the display such that the values of the various RSEG are about the same.
In dot matrix applications, contrast variations are more visible and therefore these
recommendations should be followed especially in such applications.
5. Cascading more drivers
In large display configurations, up to four PCx8538 can be cascaded. In the context used
here, cascading means combining more than one LCD driver in a design in such a way,
that makes all drivers together appear to the rest of the application as one larger LCD
driver, capable of driving a larger display than the individual LCD drivers would be able
to. In order to appear as one LCD driver to the microcontroller, all drivers used in the
cascade must use the same I2C address. The individual drivers can be differentiated on
the same I2C bus by using a 2-bit hardware sub-address (A0 and A1). These hardware
sub-addresses can be set by connecting the respective pins (A0 and A1) on the LCD
driver to either VSS or VDD, in order to make them either LOW or HIGH.
Table 2.
Pin A1
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Addressing cascaded PCx8538
Pin A0
Device
0
0
0 (master)
0
1
1 (slave)
1
0
2 (slave)
1
1
3 (slave)
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5.1 Wiring common and segment outputs
When the cascaded PCx8538 are synchronized, they can share the common
(backplane) signals from one of the devices in the cascade. Such an arrangement is
cost-effective in large LCD applications since the common outputs of only one device
need to be through-plated to the common electrodes of the display. The other PCx8538
of the cascade contribute additional segment outputs. Their common outputs can either
be connected together to enhance the drive capability or they can be left open-circuit.
See Fig 6 where external VLCD is used (common for both) and the internal clock.
Alternatively, given that the common outputs of the drivers carry the same signals, some
common outputs of the master can be taken and some of the slave in order to facilitate
the layout of the display. High flexibility in creating the glass layout is further provided by
the dual set of backplane outputs on the PCx8538.
(1) Is master (OSC connected to VSS1)
(2) Is slave (OSC connected to VDD1)
Fig 6.
Cascaded configuration with two PCA8538 with external VLCD and internal clock
In this example (external VLCD) the internal charge pump of all drivers in the cascade
must be disabled. The synchronization signal SYNC1, which is provided to synchronize
the charge pumps, must not be connected.
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5.2 Cascading more drivers using the on-chip charge pump
Using the internal VLCD charge pump is advantageous because it removes the need for
an additional supply voltage, and it provides the option of temperature compensation of
VLCD. It will however increase the power consumption of the LCD driver.
Fig 7 shows a cascaded setup where the internal charge pump is used to generate VLCD.
In this setup, the internal charge pump of all drivers in the cascade must be enabled and
VLCD of all must be set to the same voltage. The pins VLCDOUT, VLCDSENSE and VLCDIN must
be connected together, and also connected to the same pins of the other drivers. This
results in the charge pumps working in parallel, thus increasing driving capability.
Synchronization signal SYNC1 is used to synchronize the charge pumps. It is organized
as an input/output pin. The SYNC1 pins must be connected together if the on-chip VLCD
generation is used. In addition this pin must be enabled using the SYNC1_pin command.
(1) Is master (OSC connected to VSS1)
(2) Is slave (OSC connected to VDD1)
Fig 7.
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Cascaded configuration with two PCA8538 with internal VLCD and internal clock
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5.3 Choice of oscillator and synchronization
PCx8538 offers the choice of using the internal oscillator or an external oscillator. When
the internal oscillator is used, the frame frequency can be selected in the range from
45 Hz to 300 Hz, factory calibrated, with a tolerance of ± 5 Hz (at 80 Hz).
Both the internally generated clock signal or an externally supplied clock signal can be
used in cascaded applications.
In cascaded applications that use the internal clock, the master PCx8538 with device
address A[1:0] = 00 must have the OSC pin connected to VSS1 whilst the COE bit is set to
logic 1, so that this device uses its internal oscillator to generate a clock signal at the
CLK pin. The other PCx8538 devices are having the OSC pin connected to VDD1,
meaning that these devices are ready to receive an external clock signal which is
provided by the master device with subaddress A[1:0] = 00.
If the master is providing the clock signal to the slave devices, care must be taken that
the sending of the display enable or disable will be received by the master and slaves at
the same time. When the display is disabled, the output from pin CLK is disabled too. Not
providing a clock signal may result in a DC component for the display.
In cascaded applications that use an external clock, all devices have the OSC pin
connected to VDD1 and thus an external CLK is being provided for the system. Here all
devices are connected to the same external CLK.
Independent from whether an internal or external clock is used, the correct
synchronization between all cascaded PCx8538 must be maintained. For this purpose
the SYNC0 and SYNC1 lines are provided. The synchronization is guaranteed after the
Power-On Reset (POR). SYNC0 is used to synchronize the output drive signals. SYNC1
is used to synchronize the charge pumps.
If a PCx8538 is configured as the master, its SYNC lines are configured as outputs. Only
the master drives the SYNC0 and SYNC1 signals. In case the PCx8538 has been
configured as a slave, the SYNC0 and SYNC1 pads are inputs.
For proper functionality of the synchronization it is important that the contact resistance
between the SYNC pads of cascaded devices is within the given limits. This is especially
true for the SYNC1 tracks, where the limit is lower than for the SYNC0 tracks. However,
for practical purposes, the limits are considered to be equal, and thus determined by the
limitation for the SYNC1 ITO track resistances. If the resistance is too high then the
devices will not be able to synchronize properly. Table 3 shows the limiting values for
the contact resistance.
Table 3.
SYNC line contact resistance
Number of devices Maximum contact resistance of SYNC track from master to any slave
1 to 4
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10 kΩ
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5.4 Display data
The storage of display data is determined by the contents of the device address register
(see datasheet). Storage is allowed only when the content of the device address register
matches with the hardware device address applied to the pins A0 and A1. If the content
of the device address register and the hardware device address do not match, data
storage is inhibited but the data pointer is incremented as if data storage had taken
place. The hardware device address must not be changed while the device is being
accessed on the interface.
6. Compensating VLCD over temperature
Whether there is a need for temperature compensation for the LCD voltage depends on
the display technology used and on the temperature range over which the display is
used. Segment displays using TN technology are less sensitive to temperature changes
than STN and VA displays. Therefore, with TN technology and if the temperature range
is limited, it may be possible to manage with just a fixed voltage applied to VLCD.
However, intrinsically the LC cell needs compensation. The values of the threshold and
saturation voltage depend on the liquid crystal, the cell parameters and the temperature.
The temperature coefficient is negative. The temperature characteristics of the liquid
should be provided by the LCD manufacturer. In many cases, the temperature over
which a display is used varies over a wide range. Furthermore, the VA technology with its
improved black and contrast is more sensitive to temperature variations. It should be
noted that for a correct functioning temperature compensation the driver ‘needs to know’
the temperature of the LC. This is not always simple and usually COG modules have
better sensing conditions than modules with the driver on foil or displays with the driver
on the board. PCx8538 is a COG driver and if the VLCD voltage is generated internally,
the integrated 8-bit temperature compensation can be used to always apply an optimal
supply voltage to the display, irrespective of temperature. The temperature value can
also be read by command, irrespective of whether temperature compensation is enabled
or not.
In order to be able to implement an accurate temperature compensation of the VLCD
voltage, it is necessary to know the temperature characteristics of the liquid. The ambient
temperature range is divided into six independently programmable regions, and therefore
to each a different temperature coefficient can be applied.
In the datasheet a detailed description of how to implement the temperature
compensation is given.
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7. Compensating the frame frequency over temperature
Since PCx8538 provides an integrated temperature sensor and integrated charge pump
for the generation of VLCD, it is easy to implement the required temperature compensation
of VLCD. However, in some applications it may be preferred to not use the integrated
charge pump, and to apply an external voltage VLCD instead. For example, if lowest
current consumption is a prime consideration for a certain application, not using the
integrated charge pump will reduce the current consumption.
Implementing temperature compensation of an externally applied voltage VLCD will add
cost and complexity to the application. An alternative can then be changing the frame
frequency as a function of temperature.
The frame frequency can be used for ‘indirect’ temperature compensation. At a lower
temperature, the frame frequency can be lowered, because at lower temperatures the LC
viscosity increases (the liquid becomes less fluid) and the LC’s response time increases.
The LC gets a more RMS-like behavior where flicker due to a low frame frequency is less
easily seen. Because of the increase of the fluid’s viscosity the TV-curve (TV-curve: Light
Transmission as a function of Voltage) will shift less, and consequently there is more
margin for shifts in VLCD due to temperature changes.
(1) The transmission curve shifts as a function of frequency
Fig 8.
Frequency dependence of TV-curve and consequences for Von/Voff tolerance
Therefore it is possible to use the internal temperature sensor to read out the
temperature, and depending on the temperature, set the frame frequency.
The TV curve of a typical LC depends on the frequency of the cell driving signal as
shown in Fig 8.
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8. Guidelines for the COG module design
In COG applications the resistance of ITO tracks must not be neglected. Special
attention must be paid to the ITO layout in order to keep the side effects of track
resistance to an acceptable level.
For COG applications the power supply circuits of NXP LCD driver ICs are separated
internally into VDD1, VDD2, VDD3 and the corresponding VSS1, VSS2 and VSS3.
With PCx8538, VDD1 is the supply voltage 1, used for analog and digital. VDD2 is used to
supply the charge pump and VDD3 is the supply voltage for analog. This allows the
module maker to connect these supply circuits using separate ITO tracks. In this way the
common (shared) part of the ITO track is minimized or eliminated. This reduces the
amount of common-mode electrical noise.
For similar reasons, the LCD drive supply circuits are separated internally into VLCDIN,
VLCDOUT and VLCDSENSE. The shared part of the ITO supply track is thus kept to a
minimum. Fig 9 represents this schematically.
(1) In this example, VDD1 = VDD2 = VDD3
Fig 9.
Typical configuration
Excessive track resistance, especially common (shared) track and connection resistance
can result in:
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•
a deterioration of the display quality
•
increased power consumption
•
incorrect operation
•
higher sensitivity to EMI
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8.1 ITO layout recommendations for ESD/EMC robustness in COG
applications
The crucial factor for gaining an EMC and ESD robust application is the quality of the
VSS1 line.
•
To get an EMC/ESD robust ITO/glass layout, the RITO(VSS1) has to be kept as low
as possible;
•
In the most common applications VSS1 will be connected to the pins T1, T2, A0,
A1, OSC, SA0, SA1 and IFS (in the case of using the SPI interface) by using a
very wide ITO connection;
•
If possible, the ITO connection of VSS1 should be made wide, for example by
fanning out the other connections;
•
When the display is enabled, the charge and discharge caused by display
activity affects the VSS1 line. This causes a dynamic current in the VSS1 line which
means that dynamic voltage peaks in the VSS1 line may interfere with the low
voltage part of the PCx8538. Therefore a low RITO(VSS1) is also important for an
improved noise immunity of the PCx8538, especially at high VLCD values
(VLCD > 10 V);
•
A low RITO(VSS1) will also improve the communication stability with the
microcontroller by reducing the effects of local ground (VSS1) bounce caused by
high SDAACK currents;
•
It should be considered that VSS1 is internally connected to the IC substrate,
therefore noise on the VSS1 line will cause noise inside the IC.
In order to keep the ITO track resistance to a minimum, pitch and position of the module
connections must be selected such that the power tracks run as straight as possible to
the glass edge. In order to minimize common connection resistance, use low-ohmic
elastomeric connections, metal pin connections or ACF bonded foil cable.
Fig 10 and Fig 11 are showing the recommended ITO connections for a COG layout
according to the interface type being used.
More detailed information about all aspects of COG layout design is given in
reference [3], AN10170.
AN11491
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 January 2014
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AN11491
Application note
Rev. 1 — 9 January 2014
(3) RITO ≤ 200 Ω
Fig 10. Recommended ITO connections when I2C-interface is used
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© NXP B.V. 2014. All rights reserved.
Design guidelines for PCF8538 and PCA8538
(2) RITO ≤ 50 Ω
All information provided in this document is subject to legal disclaimers.
(1) RITO ≤ 100 Ω
NXP Semiconductors
AN11491
Application note
(3) RITO ≤ 200 Ω
(2) RITO ≤ 50 Ω
Fig 11. Recommended ITO connections when SPI-interface is used
AN11491
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© NXP B.V. 2014. All rights reserved.
Design guidelines for PCF8538 and PCA8538
Rev. 1 — 9 January 2014
All information provided in this document is subject to legal disclaimers.
(1) RITO ≤ 100 Ω
AN11491
NXP Semiconductors
Design guidelines for PCF8538 and PCA8538
9. Demo board
A demo board, type number OM13501, has been developed in order to provide a low
cost tool to engineers, wishing to demonstrate and evaluate the PCx8538 LCD driver,
and to get hands-on experience with writing code for it. Code written while using this
board can serve as an example for the final application. This enables rapid prototyping.
The board consists of a base board, with a plugged in LPCXpresso board which contains
the microcontroller to control the display driver.
Features:
•
Demonstrates PCA8538 LCD driver
•
Features a vertical alignment (VA) COG display module with integrated backlight
•
Includes a plugged in OM13035 LPCXpresso board with LPC1115
microcontroller
•
3 push buttons
•
User modifiable firmware, In-System/In-Application Programming (ISP/IAP) via
USB.
•
Power supply can be either using two AA batteries, via USB or via an AC
adapter/external power supply. This can also be used for external VLCD.
•
Jumpers allow quick selection between usage of I2C or SPI interface
•
Provisions to easily measure the current consumption to VDD and VLCD lines
•
Provisions to easily inject an external oscillator signal
•
Box contents:
o
OM13501 base board (marked on the board)
o
OM13035 LPCXpresso board
The LPCXpresso board contains a JTAG/SWD debugger called the “LPC-Link” and a
target MCU, which in this case is the LPC1115. LPC-Link is equipped with a 10-pin JTAG
header and it seamlessly connects to the target via USB. When the firmware needs to be
updated, the LPCXpresso board will be connected using USB to the computer on which
the IDE (Integrated Development Environment) is installed.
The 12NC of the OM13501 board is 9353 014 43598 and a picture is shown in Fig 12.
AN11491
Application note
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Rev. 1 — 9 January 2014
© NXP B.V. 2014. All rights reserved.
20 of 25
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NXP Semiconductors
Design guidelines for PCF8538 and PCA8538
Fig 12. Top view of OM13501 demo board
10. References
The documents listed below provide further useful information. They are available at
NXP’s website www.nxp.com.
AN11491
Application note
[1]
PCA8538 Product datasheet
[2]
PCF8538 Product datasheet
[3]
AN10170 – Design guidelines for COG modules with NXP monochrome LCD
drivers
[4]
AN11267 – EMC and system level ESD design guidelines for LCD drivers
[5]
UM10718 – OM13501, PCA8538 demo board user manual
[6]
R_10015 – Chip-On-Glass (COG) – a cost-effective and reliable technology for
LCD displays, White paper
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 January 2014
© NXP B.V. 2014. All rights reserved.
21 of 25
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Design guidelines for PCF8538 and PCA8538
11. Legal information
11.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
11.2 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
AN11491
Application note
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be
liable to customer for any special, indirect, consequential, punitive or
incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
Translations – A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
11.3 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 January 2014
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AN11491
NXP Semiconductors
Design guidelines for PCF8538 and PCA8538
12. List of figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Dot matrix display ............................................. 4
Dot matrix with segments .................................. 5
Mainly segmented display ................................. 5
Driver output stages with resistances and
display capacitance ........................................... 6
Waveforms for 1:9 multiplex drive mode with ¼
bias and line inversion (n = 1) ........................... 9
Cascaded configuration with two PCA8538 with
external VLCD and internal clock ...................... 11
Cascaded configuration with two PCA8538 with
internal VLCD and internal clock ....................... 12
Frequency dependence of TV-curve and
consequences for Von/Voff tolerance ................ 15
Typical configuration ....................................... 16
Recommended ITO connections when I2Cinterface is used .............................................. 18
Recommended ITO connections when SPIinterface is used .............................................. 19
Top view of OM13501 demo board ................. 21
AN11491
Application note
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Rev. 1 — 9 January 2014
© NXP B.V. 2014. All rights reserved.
23 of 25
AN11491
NXP Semiconductors
Design guidelines for PCF8538 and PCA8538
13. List of tables
Table 1.
Table 2.
Table 3.
Selection of possible display configurations ...... 4
Addressing cascaded PCx8538 ...................... 10
SYNC line contact resistance.......................... 13
AN11491
Application note
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Rev. 1 — 9 January 2014
© NXP B.V. 2014. All rights reserved.
24 of 25
AN11491
NXP Semiconductors
Design guidelines for PCF8538 and PCA8538
14. Contents
1.
2.
3.
3.1
3.2
3.3
4.
4.1
4.2
4.3
4.4
5.
5.1
5.2
5.3
5.4
6.
7.
8.
8.1
9.
10.
11.
11.1
11.2
11.3
12.
13.
14.
Introduction ......................................................... 3
Display technologies which can be driven ....... 3
Possible display configurations ........................ 4
Dot matrix display ............................................... 4
Dot matrix displays with icons ............................ 4
Segmented displays ........................................... 5
Maximum display size that can be driven ......... 6
The output resistance of the LCD outputs .......... 7
Segment and common ITO track resistances .... 7
Pixel capacitance ............................................... 7
Drive capability ................................................... 8
Cascading more drivers ................................... 10
Wiring common and segment outputs .............. 11
Cascading more drivers using the on-chip charge
pump ................................................................ 12
Choice of oscillator and synchronization .......... 13
Display data ..................................................... 14
Compensating VLCD over temperature ............. 14
Compensating the frame frequency over
temperature........................................................ 15
Guidelines for the COG module design........... 16
ITO layout recommendations for ESD/EMC
robustness in COG applications ....................... 17
Demo board ....................................................... 20
References ......................................................... 21
Legal information .............................................. 22
Definitions ........................................................ 22
Disclaimers....................................................... 22
Trademarks ...................................................... 22
List of figures..................................................... 23
List of tables ...................................................... 24
Contents ............................................................. 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2014.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 9 January 2014
Document identifier: AN11491
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