AH1401: Application Hints - Dual high speed CAN transceiver TJA1059

AH1401
Application Hints - Dual high speed CAN transceiver TJA1059
Rev. 1.0 — 09 January 2014
Document information
Info
Content
Title
Application Hints - Dual high speed CAN transceiver TJA1059
Author(s)
Frank Schade
Department
Systems & Applications, Automotive Innovation Center Hamburg
Keywords
Controller Area Network, Dual HS-CAN, TJA1059
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Summary
The intention of this application hints document is to provide the necessary information for hardware and
software designers for creation of automotive applications using the dual high speed CAN transceiver TJA1059.
Revision history
Rev
Date
Description
1.0
2014-01-09
Initial version
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
2 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Contents
1.
2.
3.
3.1
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.2
3.5.3
3.5.4
3.6
3.7
4.
4.1
5.
6.
7.
7.1
7.2
Introduction .............................................................................................................................................................. 4
Basics of high speed CAN applications ................................................................................................................. 6
The TJA1059 – Dual high speed CAN transceiver with Standby Mode ............................................................... 7
Main features .......................................................................................................................................................... 7
Operating modes..................................................................................................................................................... 8
Normal Mode........................................................................................................................................................... 8
Standby Mode ......................................................................................................................................................... 9
OFF Mode ............................................................................................................................................................... 9
Remote Wake-up (via CAN bus) ........................................................................................................................... 10
System fail-safe features ....................................................................................................................................... 12
TXD dominant clamping detection in Normal Mode .............................................................................................. 12
Bus dominant clamping prevention at entering Normal Mode ............................................................................... 12
Bus dominant clamping detection in Standby Mode .............................................................................................. 12
Undervoltage detection & recovery ....................................................................................................................... 13
Hardware application ............................................................................................................................................ 14
VCC pin .................................................................................................................................................................. 15
Thermal load consideration for the VCC voltage regulator ..................................................................................... 15
Dimensioning the bypass capacitor of the voltage regulator ................................................................................. 16
VIO pin ................................................................................................................................................................... 17
TXD pin ................................................................................................................................................................. 17
RXD pin ................................................................................................................................................................. 17
STB1 & STB2 pins ................................................................................................................................................ 17
Bus Pins CANH / CANL ........................................................................................................................................ 18
Appendix ................................................................................................................................................................. 19
Pin FMEA .............................................................................................................................................................. 19
Abbreviations ......................................................................................................................................................... 23
References .............................................................................................................................................................. 24
Legal information ................................................................................................................................................... 25
Definitions ............................................................................................................................................................. 25
Disclaimers............................................................................................................................................................ 25
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
3 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
1. Introduction
The TJA1051, TJA1042, TJA1043, TJA1048, TJA1059 and TJA1049 and their variants
TJA1042/3, TJA1051/3, TJA1051/E, TJA1049/3 are 3rd generation standalone high
speed CAN transceivers from NXP Semiconductors and a step up from high speed CAN
transceivers TJA1040, TJA1041A and TJA1050 (see Fig 1).
All transceivers provide the physical link between the protocol controller and the physical
transmission medium according to the ISO11898 ([2], [3]) and SAE J2284 [4]. This
ensures full interoperability with other ISO11898 compliant transceiver products.
TJA1041A
better
performance
24
TJA1043
24
TJA1048
24
PCA82C251
plus power
management and
I/O level shifter
plus power
management and I/O
level shifter
plus 2nd
TJA1042/3
integrated
dual TJA1042/3
24
TJA1042/3
plus I/O
level shifter
better
performance
plus 24V robustness
PCA82C250
plus power
saving
better
performance
TJA1040
VeLIO
certified
24
TJA1042
24
TJA1049
24
TJA1049/3
plus Standby Mode
plus 2nd
TJA1049/3
integrated
dual TJA1049/3
24
TJA1059
TJA1050
plus
Off Mode
24
TJA1051/E
plus I/O
level shifter
24
TJA1051/3
better
performance
24
TJA1051
2nd generation
3rd generation
Introduction
1st generation
Fig 1. Overview on the current NXP high speed CAN standalone transceiver portfolio
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
4 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
The TJA1049/3, TJA1042/3 and TJA1051/3 allow interfacing to 3V microcontrollers via
pin VIO. The TJA1051/E offers a dedicated Off mode to completely disable the
transceiver. The dual high speed CAN standalone transceiver TJA1048 offers two
integrated TJA1042/3 blocks. The dual high speed CAN standalone transceiver TJA1059
offers two integrated TJA1049/3 blocks.
Compared to their functional predecessors the 3
transceivers from NXP Semiconductors offer
rd
generation high speed CAN

a significantly improved ESD robustness,

a further reduction in electromagnetic emission (EME)

beside an improved electromagnetic immunity (EMI),

a higher voltage robustness in order to full support 24V applications

and a predictable undervoltage behavior at all supply conditions.
With the extended portfolio of high speed CAN transceivers NXP Semiconductors
enables ECU designers to find the best application fitting standalone transceiver product
in order to cover all main application specific requirements (Fig 2).
5V
TJA1051/3
8
1






3-5V
TJA1051/E
8
1






5V
TJA1042
8
1








5V
TJA1042/3
8
1








3-5V
8
1








5V
8
1








3-5V
14
2







3-5V
14
2







3-5V
14
1





1
TJA1049/3
1
TJA1048
TJA1059
1, 2
TJA1043



1
VeLIO certified
2
Comply with all global OEM requirements; allows a one-fits-all approach



3-5V



Introduction
TJA1049

SPLIT pin

Host Interface

Local via WAKE
Temperature protection

Remote via CAN
Short circuit protection

Error detection
Undervoltage detection

Bus dominant timer

TXD dominant timer
1
Off
8
Sleep
Listen-only
TJA1051
HSCAN device
Standby
Normal
Wake-up
No. of CAN channels
Fail-safe features
No. of pins
Modes
rd
Fig 2. Feature overview of 3 generation high speed CAN standalone transceiver portfolio
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
5 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
2. Basics of high speed CAN applications
The protocol controller outputs a serial transmit data stream to the TXD input of the CAN
transceiver. An internal pull-up function sets the TXD input to logic HIGH, which means
that the bus output driver stays recessive in the case of a TXD open circuit condition. In
the recessive state (Fig 3) the CANH and CANL pins are biased to a voltage level of VCC
divided by 2. If a logic LOW level is applied to TXD, the output stage is activated,
generating a dominant state on the bus line Fig 3.
Single Ended
Bus Voltage
CANH
3.6V
2.5V
CANL
1.4V
Differential
Bus Voltage
5.0V
Differential input voltage
range for dominant state
0.9V
0.5V
Differential input voltage
range for recessive state
-1.0V
time
Recessive
Dominant
Recessive
Fig 3. Nominal bus levels according to ISO11898
The receiver converts the differential bus signal to a logic level signal, which is output at
RXD. The serial receive data stream is provided to the bus protocol controller for
decoding. The internal receiver comparator is always active. It monitors the bus while the
bus node is transmitting a message. This is required to support the non-destructive bitby-bit arbitration scheme of CAN.
Details about high speed CAN applications in general are explained in the NXP
application hints document [5] ― Rules and recommendations for in-vehicle CAN
networks.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
6 of 26
Basics of high speed CAN applications
If no bus node transmits a dominant bit, the bus stays in recessive state. If one or
multiple bus nodes transmit a dominant bit, then the bus lines enter the dominant state
overriding the recessive state (wired-AND characteristic).
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3. The TJA1059 – Dual high speed CAN transceiver with Standby Mode
3.1 Main features
The TJA1059 is a dual high-speed CAN transceiver from NXP Semiconductors providing
two independent CAN channels with a low power mode (called Standby mode) besides a
Normal mode. The TJA1059 can be interfaced directly to microcontrollers with supply
voltages from 3V to 5V [1].
The TJA1059 is the excellent choice for all types of HS-CAN networks containing more
than one HS-CAN interface that require a low-power mode with wake-up capability via
the CAN bus, especially for Body Control and Gateway units.
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
Due to the compliance with all global OEM requirements the TJA1059 allows a one-fitsall approach.
Fig 4. Block diagram and pinning of the TJA1059
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
7 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.2 Operating modes
The TJA1059 offers 2 different power modes, Normal mode and Standby mode which
are directly selectable for each CAN channel. Taking into account the VIO undervoltage
condition a third power mode can be entered; the so-called OFF mode, selected
generally for both CAN channels. Fig 5 shows how the different operation modes can be
entered. Every mode provides a certain behavior and terminates the CAN channel to a
certain value. The following sub-chapters give a short overview of those features.
STB = 0
AND
VCC > VUVD(VCC)
AND
VIO > VUVD(VIO)
Normal
Mode
VIO < VUVD(VIO)
STB = 1
OR
VCC < VUVD(VCC)
Standby
Mode
[STB = 1
OR
VCC < VUVD(VCC)]
AND
VIO > VUVD(VIO)
OFF
Mode
VIO < VUVD(VIO)
Fig 5. State diagram TJA1059
3.2.1 Normal Mode
In Normal mode the CAN communication is enabled. The digital bit stream input at TXD
is transferred into corresponding analog bus signals. Simultaneously, the transceiver
monitors the bus, converting the analog bus signals into the corresponding digital bit
stream output at RXD. The bus lines are biased to VCC/2 in recessive state and the
transmitter is enabled. The Normal mode is entered setting STB1 or STB2 to LOW.
Switching into Normal mode is CAN channel independently.
In Normal mode the transceiver provides the following functions:
 The CAN transmitter is active.
 The normal CAN receiver is active.
 The low power CAN receiver is active.
 CANH and CANL are biased to VCC/2.
 Pin RXD reflects the normal CAN Receiver.
 VCC and VIO undervoltage detectors are active for undervoltage detection.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
8 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
STB = 0
AND
VCC > VUVD(VCC))
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.2.2 Standby Mode
The Standby mode is used to reduce the power consumption of the TJA1059
significantly. In Standby mode the specific CAN channel is not capable of transmitting
and receiving regular CAN messages, but it monitors the bus for CAN messages. After
passing the wake-up filter the bus signal is transferred to RXD with an additional time
delay tfltr(wake)bus. To reduce the current consumption as far as possible the bus is
terminated to GND rather than biased to VCC/2 as in Normal mode. The Standby mode is
selected setting STB1 or STB2 to HIGH channel independently or by undervoltage
detection on VCC for both channels at the same time. Due to an internal pull-up function
on the pins STB1 and STB2 it is the default mode if the pins are unconnected.
In Standby mode the transceiver provides the following functions:
 The CAN transmitter is off.
 The normal CAN receiver is off.
 The low power CAN receiver is active.
 CANH and CANL are biased to GND.
 Pin RXD reflects the low power CAN receiver.
 VIO undervoltage detector is active for undervoltage detection.
 VCC undervoltage detector may be disabled.
The non-operation Off mode is introduced offering total passive behaviour the to bus
system. The OFF mode is entered by undervoltage detection on VIO. Entering and
leaving OFF Mode is done for both channels at the same time, thus not independently. In
OFF mode the transceiver provides the following functions:
 The CAN transmitter is off.
 The normal CAN receiver is off.
 The low power CAN receiver is off.
 CANH and CANL are floating (lowest leakage current on bus pins).
 VIO undervoltage detector is active for undervoltage detection.
 VCC undervoltage detector may be disabled.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
9 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
3.2.3 OFF Mode
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Table 1.
Characteristics of the different modes
Ch1 Op. Ch2 Op.
mode
mode
STB1
pin
STB2
pin
VCC
VIO
underv. underv.
Normal
Normal
0
0
no
no
Standby
Normal
1
0
no
no
Normal
Standby
0
1
no
no
Standby Standby
1
1
no
no
Standby Standby
X
X
yes
no
X
X
X
yes
OFF
OFF
RXD1 pin
Low
High
Bus
dom.
Bus
rec.
WakeNo
up
wake-up
detected detected
Bus
dom.
RXD2 pin
Bus2
bias
Low
High
VCC/2
Bus
dom.
Bus
rec.
VCC/2
GND
Bus
dom.
Bus
rec.
VCC/2
VCC/2
WakeNo
up
wake-up
detected detected
GND
WakeNo
up
wake-up
detected detected
GND
WakeNo
up
wake-up
detected detected
GND
WakeNo
up
wake-up
detected detected
GND
WakeNo
up
wake-up
detected detected
GND
-
Bus
rec.
Bus1
bias
-
float
-
-
float
In comparison to the TJA1049 the TJA1059 offers a slightly enhanced remote wake-up
procedure. The TJA1049 in Standby mode transfers the bus signal to RXD with an
additional time delay tfltr(wake)bus in oder to filter noise and spikes.
A dedicated wake-up sequence (specified in ISO11898-5) must be received to wake-up
the TJA1059 from Standby mode [1]. This filtering improves the robustness against
spurious wake-up events due to a dominant clamped CAN bus or dominant phases
caused by noise or spikes on the bus.
The wake-up pattern consists of:
 A dominant phase of at least twake(busdom) followed by
 A recessive phase of at least twake(busrec) followed by
 A dominant phase of at least twake(busdom)
The complete dominant-recessive-dominant pattern must be completed within tto(wake)bus
to be recognized as a valid wake-up pattern (see Fig 6). Otherwise the internal wake-up
logic gets reset and the complete wake-up pattern needs to be re-applied to the low
power receiver of CAN1 or CAN2 before generating a proper remote wake-up. Pins
RXD1 and RXD2 will remain high until the wake-up event has been triggered.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
10 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
3.3 Remote Wake-up (via CAN bus)
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
CANH
VO(diff)bus
CANL
twake(dom)bus
twake(rec)bus
twake(dom)bus
RXD
tfltr(wake)bus
tfltr(wake)bus
tto(wake)bus
tto(wake)bus = 0.5ms to 5ms
tfltr(wake)bus = 0.5µs to 5µs
twake(busdom) = twake(busrec) = 0.5µs to 5µs
Fig 6. Wake-up timings and behaviour
A wake-up event will not be registered if any of the following events occurs while a wakeup sequence is being received:
 The TJA1059 switches to Normal mode
 The complete wake-up pattern was not received within tto(wake)bus
 A VIO undervoltage was detected (VIO < Vuvd(VIO))
If any of these events occurs while a wake-up sequence is being received, the internal
wake-up logic will be reset and the complete wake-up sequence will have to be retransmitted to trigger a wake-up event.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
11 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
After the wake-up sequence has been detected, the TJA1059 behaves equal to the
TJA1049 and will remain in Standby mode with the bus signals reflected on RXD1/RXD2.
Note that dominant or recessive phases less than tfltr(wake)bus will not be detected by the
low power differential receiver and will not be reflected on RXD1/RXD2 in Standby mode.
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.4 System fail-safe features
3.4.1 TXD dominant clamping detection in Normal Mode
The TXD dominant clamping detection prevents an erroneous CAN-controller from
clamping the bus to dominant level by a continuously dominant TXD signal.
Fig 7. TXD dominant clamping in Normal mode
3.4.2 Bus dominant clamping prevention at entering Normal Mode
The TJA1059 provides bus dominant clamping prevention at entering Normal mode. The
TXD pin needs to be set HIGH before transmitting its first dominant bit to the bus in
Normal mode. This prevents the transceiver clamping the entire bus when starting up
with not well defined TXD.
3.4.3 Bus dominant clamping detection in Standby Mode
The extended wake-up filter allows a system enter the Standby mode even with a
permanently dominant clamped bus (see also chapter 3.3). Because the first wake-up
sequence will not be passed. In this case the RXD pin keeps high. For same reasons the
RXD keeps high if the dominant clamped bus occurs in Standby mode. If the wake-up
filter is passed for certain reasons and the bus keeps clamped dominat the RXD
becomes low and keeps this state as long as the failure is present.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
12 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
After a maximum allowable TXD dominant time tto(dom)TXD the transmitter is disabled (see
Fig 7). According to the CAN protocol only a maximum of eleven successive dominant
bits are allowed on TXD (worst case of five successive dominant bits followed
immediately by an error frame). Along with the minimum allowable TXD dominant time,
this limits the minimum bit rate to 40 kbit/s.
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.4.4 Undervoltage detection & recovery
The TJA1059 provides two supply pins, VCC and VIO. The VCC voltage is needed for the
CAN physical interface. VCC provides the current needed for the CAN transmitter and
receiver in Normal mode. Pin VIO should be connected to the microcontroller supply
voltage. This will adjust the signal levels of pins TXD1, TXD2, RXD1, RXD2, STB1 and
STB2 to the I/O levels of the microcontroller. Pin VIO also provides the internal supply
voltage for the low power differential receiver of each integrated transceiver. For
applications running in low power, this allows the bus lines to be monitored for activity
even if there is no supply voltage on pin VCC.
Both voltages are independent from each other. An undervoltage detection circuitry at
VCC and VIO indicates either a VCC or VIO undervoltage condition that is used for mode
control. A VCC undervoltage condition forces both CAN channels of the TJA1059 to enter
Standby mode. The logic state of pins STB1 and STB2 will be ignored until VCC has
recovered. This allows saving current in case of switching off the supply voltage or faulty
behaviour of host electronic control unit. As long as VIO keeps present the TJA1059
offers the full wake-up capability. A VIO undervoltage condition forces both CAN channels
of the TJA1059 to switch off (OFF mode) and to disengage from the bus (zero loads)
until VIO has recovered. In OFF mode both CAN transceivers behave passive to the bus.
Table 2 gives an overview of the undervoltage behaviour. As long as no undervoltage is
detected the TJA1059 keeps fully operational.
Device behaviour in different power conditions
Undervoltage condition
Operating mode
CAN1 / CAN2 biasing
Bus wake-up
capability
VCC
VIO
no
no
Normal or Standby
VCC/2 or GND
yes
yes
no
Standby
GND
yes
no
yes
OFF
float
no
yes
yes
OFF
float
no
DOC95810
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
Table 2.
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
13 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.5 Hardware application
Fig 8 shows how to integrate the TJA1059 within a typical application. The application
example assumes a 3V supplied host microcontroller. There is a dedicated 5V regulator
supplying the TJA1059 transceiver on its VCC supply pin (necessary for proper CAN
transmit capability).
BAT
3V
*
e.g.
47nF
*
e.g.
47nF
Global module
reverse supply
protection diode
5V
VIO
VCC
VDD
CANH1
RT **
CAN
bus
RT **
e.g.
100pF
TxD1
TxDx
RxD2
RxDx
C
+
CAN
e.g.
4,7nF
STB1
I/O
TxD2
TxDy
RxD2
RxDy
STB2
I/O
CANL1
TJA1059
CANH2
RT **
e.g.
100pF
GND
CAN
bus
RT **
e.g.
4,7nF
CANL2
e.g.
100pF
GNDA
GNDB
* Size of capacitor depends on regulator.
** For bus line end nodes RT = 60Ohm in order to support the „Split termination concept“.
For stub nodes an optional "weak" termination of e.g. RT = 1,3kΩ ...4,7kΩ can be foreseen, if required by the OEM.
General remark: A dedicated application may depend on specific OEM requirements.
Fig 8. Application diagram TJA1059
Note: For detailed hardware application guidance please refer to next chapters
explaining how the pins of the TJA1059 are properly connected in an application
environment.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
14 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
e.g.
100pF
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.5.1 VCC pin
The VCC supply provides the current needed for the transmitter and receiver of the high
speed CAN transceiver. The VCC supply must be able to deliver current of 90 mA in
average for the transceiver (see chapter 3.5.1.1).
Typically a capacitor between 47nF and 100nF is recommended being connected
between VCC and GND close to the transceiver. This capacitor buffers the supply voltage
during the transition from recessive to dominant, when there is a sharp rise in current
demand.
Using a linear voltage regulator, it is recommended to stabilize the output voltage with an
additional bypass capacitor (see chapter 3.5.1.2) that is usually placed at the output of
the voltage regulator. Its purpose is to buffer disturbances on the battery line and to
buffer extra supply current demand in the case of bus failures. The calculation of the
bypass capacitor value is shown in chapter 3.5.1.2, while in chapter 3.5.1.1 the average
VCC supply current is calculated for thermal load considerations of the V CC voltage
regulator. This can be done in absence and in presence of bus short-circuit conditions.
3.5.1.1
Thermal load consideration for the VCC voltage regulator
The averages VCC supply current can be calculated in absence and in presence of bus
short-circuit conditions (see Table 3). Assuming a transmit duty cycle of 50% on pin TXD
the maximum average supply current in absence of bus failures calculates to:
ICC_norm_avg = 0.5 • (ICC_REC_MAX + ICC_DOM_MAX)
Maximum VCC supply current in recessive and dominant state
Device
ICC_REC_MAX [mA]
ICC_DOM_MAX [mA]
TJA1059
20 (both channel recessive)
140 (both channel dominant)
This results in an average supply current of ICC_norm_avg = 80mA.
In presence of bus failures the VCC supply current for the transceiver can increase
significantly (see Table 4). The maximum dominant VCC supply current ICC_DOM_SC_MAX
flows in the case of an applied short circuit between CANH to GND. Along with the
CANH short circuit output current IO(dom)MAX = 100mA the maximum dominant VCC supply
current ICC_DOM_SC_MAX calculates to about 220mA.
ICC_DOM_SC_MAX = (ICC_REC_MAX + IO(dom)MAX)
This results in an average supply current of 110mA in worst case of a short circuit from
CANH to GND. The VCC voltage regulator must be able to handle this average supply
current.
Table 4.
Average VCC supply current
Device
ICC_norm_avg [mA]
TJA1059
80 (both channels transmitting) 220 (both channels shorted)
DOC95810
ICC_AVG_SC_MAX [mA]
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
15 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
Table 3.
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.5.1.2
Dimensioning the bypass capacitor of the voltage regulator
Depending on the power supply concept, the required worst-case bypass capacitor and
the extra current demand in the case of bus failures can be calculated.
I CC _ max_ sc  t dom _ max
C BUFF 
Vmax
Dimensioning the capacitor gets very important with a shared voltage supply between
transceiver and microcontroller. Here, extra current demand with bus failures may not
lead to an unstable supply for the microcontroller. This input is used to determine the
bypass capacitor needed to keep the voltage supply stable under the assumption that all
the extra current demand has to be delivered from the bypass capacitor.
The quiescent current delivered from the voltage regulator to the transceiver is
determined by the recessive VCC supply current ICC_REC.
In absence of bus failures the maximum extra supply current is calculated by:
ΔICC_max = (ICC_DOM_MAX – ICC_REC_MIN)
In presence of bus failures the maximum extra supply current may be significantly higher.
Considering the worst case of a short circuit from CANH to GND the maximum extra
supply current is calculated by:
ΔICC_max_sc = (ICC_DOM_SC_MAX – ICC_REC_MIN)
With ICC_dom_sc_max = 220 mA (estimated) and ICC_rec_min = 4 mA the maximum extra supply
current calculates to
ΔICC_max_sc = 216 mA
In the case of a short circuit from CANH to GND, the bus is clamped to the recessive
state, and according to the CAN protocol the uC transmits 17 subsequent dominant bits
on TXD. That would mean the above calculated maximum extra supply current has to be
delivered for at least 17 bit times. The reason for the 17 bit times is that at the moment
the CAN controller starts a transmission, the dominant Start Of Frame bit is not fed back
to RXD and forces an error frame due to the bit failure condition. The first bit of the error
frame again is not reflected at RXD and forces the next error frame (TX Error Counter
+8). Latest after 17 bit times, depending on the TX Error Counter Level before starting
this transmission, the CAN controller reaches the Error Passive limit (128) and stops
sending dominant bits. Now a sequence of 25 recessive bits follows (8 Bit Error Delimiter
+ 3 Bit Intermission + 8 Bit Suspend Transmission) and the VCC supply current becomes
reduced to the recessive one.
Assuming that the complete extra supply current during the 17 bit times has to be
buffered by the bypass capacitor, the worst-case bypass capacitor calculates to:
CBUFF 
I CC _ max_ sc  tdom _ max
Vmax
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
16 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
Example:
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Whereas ΔVmax is the maximum allowed voltage drop at pin VCC and tdom_max is the
dominant time of 17 bit times at 500kbit/s.
Table 5.
Average VCC supply current (assuming 500kbit/s)
Device
ΔICC_max_sc
tdom_max
ΔVmax
CBuFF
TJA1048
216mA
34µs
0,25V
 30µF
Of course, depending on the regulation capabilities of the used voltage regulator the
bypass capacitor may be much smaller.
3.5.2 VIO pin
Pin VIO is connected to the microcontroller supply voltage to provide the proper voltage
reference for the input threshold of digital input pins and for the HIGH voltage of digital
outputs. It defines the ratiometric digital input threshold from as 2.85V to 5.25V.for
interface pins like TXD1, TXD2, STB1 and STB2 and the HIGH-level output voltage for
RXD1 and RXD2.
Also for the TJA1059 the low-power differential receiver is supplied out of pin VIO. This
allows the bus lines to be monitored for activity even if there is no supply voltage on pin
VCC. This allows applications with even less quiescent current because the 5V regulator
can be switched off entirely keeping bus wake-ups still possible. If there is detected an
undervoltage condition the transceiver will switch into OFF mode and both CAN channels
will be invisible onto the bus.
The transceiver receives the digital bit stream to be transmitted onto the bus via the pin
TXD. When applied signals at TXD show very fast slopes, it may cause a degradation of
the EMC performance. Depending on the OEM an optinal series resistor of up to 1kΩ
within the TXD line between transceiver and microcontroller might be useful. Along with
pin capacitance this would help to smooth the edges for some degree. For high bus
speeds (close to 1 Mbit/s) the additional delay within TXD has to be taken into account.
Please consult the dedicated OEM specification regarding TXD connection to the host
microcontroller.
3.5.4 RXD pin
The analog bit stream received from the bus is output at pin RXD for further processing
within the CAN-controller. As with pin TXD a series resistor of up to 1 kΩ can be used to
smooth the edges at bit transitions. Again the additional delay within RXD has to be
taken into account, if high bus speeds close to 1 Mbit/s are used. Please consult the
dedicated OEM specification regarding TXD connection to the host microcontroller.
3.6 STB1 & STB2 pins
These input pins are mode pins and used for mode control. They are typically directly
connected to an output port pin of a microcontroller.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
17 of 26
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
3.5.3 TXD pin
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
3.7 Bus Pins CANH / CANL
The transceiver is connected to the bus via pin CANH/L. Nodes connected to the bus
end must show a differential termination, which is approximately equal to the
characteristic impedance of the bus line in order to suppress signal reflection. Instead of
a one-resistor termination it is highly recommended using the so-called Split Termination
(for details refer to [5]). EMC measurements have shown that the Split Termination is
able to improve significantly the signal symmetry between CANH and CANL, thus
reducing emission. Basically each of the two termination resistors is split into two
resistors of equal value, i.e. two resistors of 60 (or 62) instead of one resistor of
120. The special characteristic of this approach is that the common mode signal,
available at the centre tap of the termination, is terminated to ground via a capacitor. The
recommended value for this capacitor is in the range of 4,7nF to 47nF.
As the symmetry of the two signal lines is crucial for the emission performance of the
system, the matching tolerance of the two termination resistors should be as low as
possible (desired: <1%).
Additionally it is recommended to load the CANH and CANL pin each with a capacitor of
about 100pF close to the connector of the ECU. The main reason is to increase the
robustness to automotive transients and ESD. The matching tolerance of the two
capacitors should be as low as possible.
OEMs might have dedicated circuits prescribed in their specifications. Please refer to the
corresponding OEM specifications for individual details.
The TJA1059 – Dual high speed CAN transceiver with Standby Mode
Details about high speed CAN applications in general are explained in the NXP
application hints document [5] ― Rules and recommendations for in-vehicle CAN
networks.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
18 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
4. Appendix
4.1 Pin FMEA
This chapter provides an FMEA (Failure Mode and Effect Analysis) for typical failure
rd
situations, when dedicated pins of the 3 generation HS-CAN transceivers are shortcircuited to supply voltages like VBAT, VCC, GND or to neighbored pins or simply left open.
The individual failures are classified, due to their corresponding effects on the transceiver
and bus communication in Table 6.
Table 6.
Class
Classification of failure effects
Effects
- Damage to transceiver
- Bus may be affected
B
- No damage to transceiver
- No bus communication possible
C
- No damage to transceiver
- Bus communication possible
- Corrupted node excluded from communication
D
- No damage to transceiver
- Bus communication possible
- Reduced functionality of transceiver
Appendix / Pin FMEA TJA1059
A
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
19 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Table 7.
TJA1059 FMEA matrix for pin short-circuits to VBAT and VCC
Short to VBAT (12V … 40 V)
Pin
Class
Remark
Short to VCC (5V)
Class
Remark
(1) TXD1
A
Limiting value exceeded
C
TXD1 clamped recessive
(2) GNDA
C
Node is left unpowered
C
VCC undervoltage detected;
Both TRX enter Standby Mode
(3) VCC
A
Limiting value exceeded
-
(4) RXD1
A
Limiting value exceeded
C
RXD1 clamped recessive;
Channel 1 bus communication
may be disturbed
(5) GNDB
C
Node is left unpowered
C
VCC undervoltage detected;
Both TRX enter Standby Mode
(6) TXD2
A
Limiting value exceeded
C
TXD2 clamped recessive
(7) RXD2
A
Limiting value exceeded
C
RXD2 clamped recessive;
Channel 2 bus communication
may be disturbed
(8) STB2
A
Limiting value exceeded
D
Channel 2 Normal Mode not
selectable
(9) CANL2
B
No bus communication
B
Channel 2 no bus communication
(10) CANH2
D
Degration of EMC;
Bit timing violation possible
D
Channel 2 degration of EMC;
Bit timing violation possible
(11) VIO
A
Limiting value exceeded
C
uC may be damaged, if VCC > VIO
(12) CANL1
B
No bus communication
B
Channel 1 no bus communication
(13) CANH1
D
Degration of EMC;
Bit timing violation possible
D
Channel 1 degration of EMC;
Bit timing violation possible
(14) STB1
A
Limiting value exceeded
D
Channel 1 Normal Mode not
selectable
Appendix / Pin FMEA TJA1059
-
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
20 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Table 8.
TJA1059 FMEA matrix for pin short-circuits to GND and open
Pin
Short to GND
Class
C
(2) GNDA
-
(3) VCC
TXD1 dominant clamping;
Transmitter is disabled
Class
Remark
C
TXD1 clamped recessive
-
C
Undervoltage detected;
Both TRXs enter Off Mode and
behave passive to the bus
C
VCC undervoltage detected;
Both TRX enter Standby Mode
C
VCC undervoltage detected;
Both TRX enter Standby Mode
(4) RXD1
C
RXD1 clamped dominant
C
Node may produce error frames on
channel 1 until bus-off is entered
(5) GNDB
-
C
Undervoltage detected;
Both TRX enter Off Mode and
behave passive to the bus
(6) TXD2
C
TXD2 dominant clamping;
Transmitter is disabled
C
TXD2 clamped recessive
(7) RXD2
C
RXD2 clamped dominant
C
Node may produce error frames on
channel 2 until bus-off is entered
(8) STB2
C
Channel 2 Standby Mode not
selectable
C
Channel 2 Normal Mode not
selectable
(9) CANL2
D
Channel 2 degration of EMC;
Bit timing violation possible
C
Channel 2 transmission not
possible
(10) CANH2
B
Channel 2 no bus
communication
C
Channel 2 transmission not
possible
(11) VIO
C
VIO undervoltage detected;
Both TRX enter Off Mode and
behave passive to the bus
C
VIO undervoltage detected;
Both TRX enter Off Mode and
behave passive to the bus
(12) CANL1
D
Channel 1 degration of EMC;
Bit timing violation possible
C
Channel 1 transmission not
possible
(13) CANH1
B
Channel 1 no bus
communication
C
Channel 1 transmission not
possible
(14) STB1
C
Channel 1 Standby Mode not
selectable
C
Channel 1 Normal Mode not
selectable
-
Appendix / Pin FMEA TJA1059
(1) TXD1
Remark
Open
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
21 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Table 9.
TJA1059 FMEA matrix for pin short-circuits to neighbored pins
Pin
Short to neighbored pin
Class
Remark
C
Transmitter 1 disabled after TXD dominant timeout
GNDA - VCC
C
VCC undervoltage detected; Both TRX enter Standby Mode
VCC - RXD1
C
RXD 1 clamped recessive
RXD1 - GNDB
C
RXD 1 clamped dominant
GNDB - TXD2
C
Transmitter 2 disabled after TXD dominant timeout
TXD2 - RXD2
B
Temporary channel 2 bus blocking possible; Bus 2 is released after
TXD dominant timeout
STBN2 - CANL2
D
TRX 2 enters Standby Mode if the bus is recessive and enters
Normal mode if the bus is driven dominant
CANL2 - CANH2
B
No bus communication on channel 2
CANH2 - VIO
D
Degration of EMC;
Bit timing violation possible
VIO - CANL1
B
No bus communication on channel 1
CANL1 - CANH1
B
No bus communication on channel 1
CANH1 - STB1
D
TRX 1 is not able to enter Normal Mode if the bus is recessive or
driven dominant
Appendix / Pin FMEA TJA1059
TXD1 - GNDA
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
22 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
5. Abbreviations
Table 10.
Abbreviations
Description
CAN
Controller Area Network
Clamp-15
ECU architecture, Battery supply line after the ignition key, module is
temporarily supplied by the battery only (when ignition key is on)
Clamp-30
ECU architecture, direct battery supply line before the ignition key, module is
permanently supplied by the battery
DLC
Data Link Control
ECU
Electronic Control Unit
EMC
Electromagnetic Compatibility
EME
Electromagnetic Emission
EMI
Electromagnetic Immunity
ESD
Electrostatic Discharge
FMEA
Failure Mode and Effects Analysis
LIN
Local Interconnect Network
OEM
Original Equipment Manufacturer
PCB
Printed Circuit Board
Abbreviations
Acronym
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
23 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
6. References
Product data sheet TJA1059, Dual high-speed CAN transceiver with Standby Mode
– NXP Semiconductors, Rev. 0.7, 2013 Jan 3
[2]
Road Vehicles – Controller Area Network (CAN) – Part 2: High-speed medium
access unit, ISO 11898-2, International Standardization Organisation, 2003
[3]
Road Vehicles – Controller Area Network (CAN) – Part 5: High-speed medium
access unit with low power mode, ISO 11898-5, International Standardization
Organisation, 2007
[4]
High Speed CAN (HSC) for Vehicle Applications at 500kbps - SAE J2284, 2009
[5]
Application Hints, Rules and recommendations for in-vehicle CAN networks,
TR1135 – NXP Semiconductors, Rev. 00.01, 24 September 2012
References
[1]
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
24 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
7. Legal information
7.1 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
7.2 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations
or warranties, expressed or implied, as to the accuracy or completeness of
such information and shall have no liability for the consequences of use of
such information.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is for the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
DOC95810
© NXP B.V. 2014. All rights reserved.
Rev. 1.0 — 09 January 2014
25 of 26
AH1401
NXP Semiconductors
Systems & Applications, Automotive Innovation Center
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, email to: [email protected]
Date of release: 09 January 2014
Document identifier: DOC95810
Similar pages