INTEGRATED CIRCUITS DATA SHEET SAA1057 Radio tuning PLL frequency synthesizer Product specification File under Integrated Circuits, IC01 November 1983 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 • On-chip programmable current amplifier (charge pump) to adjust the loop gain. GENERAL DESCRIPTION The SAA1057 is a single chip frequency synthesizer IC in I2L technology, which performs all the tuning functions of a PLL radio tuning system. The IC is applicable to all types of radio receivers, e.g. car radios, hi-fi radios and portable radios. • Only one reference frequency for both AM and FM. • High signal purity due to a sample and hold phase detector for the in-lock condition. • High tuning speed due to a powerful digital memory phase detector during the out-lock condition. Features • On-chip prescaler with up to 120 MHz input frequency. • Tuning steps for AM are: 1 kHz or 1,25 kHz for a VCO frequency range of 512 kHz to 32 MHz. • On-chip AM and FM input amplifiers with high sensitivity (30 mV and 10 mV respectively). • Tuning steps for FM are: 10 kHz or 12,5 kHz for a VCO frequency range of 70 MHz to 120 MHz. • Low current drain (typically 16 mA for AM and 20 mA for FM) over a wide supply voltage range (3,6 V to 12 V). • Serial 3-line bus interface to a microcomputer. • Test/features. • On-chip amplifier for loop filter for both AM and FM (up to 30 V tuning voltage). QUICK REFERENCE DATA VCC1 3,6 to 12 V VCC2 3,6 to 12 V VCC3 VCC2 to 31 V ICC1 + ICC2 typ. 18 mA ICC3 typ. 0,8 mA fFAM 512 kHz to 32 MHz at pin FFM fFFM 70 to 120 MHz Maximum crystal input frequency fXTAL > MHz Operating ambient temperature range Tamb −25 to + 80 Supply voltage ranges Supply currents Input frequency ranges at pin FAM PACKAGE OUTLINE 18-lead DIL; plastic (SOT102H); SOT102-1; 1996 September 2. November 1983 2 4 °C Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 Fig.1 Block diagram. • A reference frequency oscillator followed by a reference divider. The frequency is generated by a 4 MHz quartz crystal. The reference frequency can be chosen either 32 kHz or 40 kHz for the digital phase detector (that means 1 kHz and 1,25 kHz for the sample and hold phase detector), which results in tuning steps of 1 kHz and 1,25 kHz for AM, and 10 kHz and 12,5 kHz for FM. GENERAL DESCRIPTION The SAA1057 performs the entire PLL synthesizer function (from frequency inputs to tuning voltage output) for all types of radios with the AM and FM frequency ranges. The circuit comprises the following: • A programmable current amplifier (charge pump), which controls the output current of both the digital and the sample/hold phase detector in a range of 40 dB. It also allows the loop gain of the tuning system to be adjusted by the microcomputer. • Separate input amplifiers for the AM and FM VCO-signals. • A divider-by-10 for the FM channel. • A multiplexer which selects the AM or FM input. • A 15-bit programmable divider for selecting the required frequency. • A tuning voltage amplifier, which can deliver a tuning voltage of up to 30 V. • A sample and hold phase detector for the in-lock condition, to achieve the high spectral purity of the VCO signal. • BUS; this circuitry consists of a format control part, a 16-bit shift register and two 15-bit latches. Latch A contains the to be tuned frequency information in a binary code. This binary-coded number, multiplied by the tuning spacing, is equal to the synthesized frequency. The programmable divider (without the fixed divide-by-10 prescaler for FM) can be programmed in a range between 512 and 32 767 (see Fig.3). Latch B contains the control information. • A digital memory frequency/phase detector, which operates at a 32 times higher frequency than the sample and hold phase detector, so fast tuning can be achieved. • An in-lock counter detects when the system is in-lock. The digital phase detector is switched-off automatically when an in-lock condition is detected. November 1983 3 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 OPERATION DESCRIPTION Control information The following functions can be controlled with the data word bits in latch B. For data word format and bit position see Fig.3. FM FM/AM selection; ‘1’ = FM, ‘0’ = AM REFH reference frequency selection; ‘1’ = 1,25 kHz, ‘0’ = 1 kHz (sample and hold phase detector) CP3 CP2 control bits for the programmable current amplifier (see section Characteristics) CP1 CP0 SB2 enables last 8 bits (SLA to T0) of data word B; ‘1’ = enables, ‘0’ = disables; when programmed ‘0’, the last 8 bits of data word B will be set to ‘0’ automatically SLA load mode of latch A; ‘1’ = synchronous, ‘0’ = asynchronous PDM1 PDM0 phase detector mode PDM1 PDM0 digital phase detector 0 X automatic on/off 1 0 on 1 1 off BRM bus receiver mode bit; in this mode the supply current of the BUS receiver will be switched-off automatically after a data transmission (current-draw is reduced); ‘1’ = current switched; ‘0’ = current always on T3 test bit; must be programmed always ‘0’ T2 test bit; selects the reference frequency (32 or 40 kHz) to the TEST pin T1 test bit; must be programmed always ‘0’ T0 test bit; selects the output of the programmable counter to the TEST pin T3 T2 T1 T0 0 0 0 0 1 0 1 0 0 reference frequency 0 0 0 1 output programmable counter 0 1 0 1 output in-lock counter ‘0’ = out-lock ‘1’ = in-lock November 1983 TEST (pin 18) 4 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 (1) During the zero set-up time (tLZsu) CLB can be LOW or HIGH, but no transient of the signal is permitted. This can be of use when an I2C bus is used for other devices on the same data and clock lines. Fig.2 BUS format. Fig.3 Bit organization of data words A and B. November 1983 5 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 PINNING 1 TR 2 TCA 3 TCB 4 DCS decoupling of supply 5 IN input of output amplifier 6 OUT output of output amplifier 7 VCC3 positive supply voltage of resistor/capacitors for sample and hold circuit output amplifier 8 FFM FM signal input 9 VCC1 positive supply voltage of high frequency logic part 10 DCA decoupling of input 11 FAM 12 DATA 13 DLEN 14 CLB 15 VEE ground 16 VCC2 positive supply voltage of low frequency logic part and analogue part 17 XTAL reference oscillator input 18 TEST test output amplifiers AM signal input BUS Fig.4 Pinning diagram. RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage; logic and analogue part VCC1; VCC2 −0,3 to 13,2 V Supply voltage; output amplifier VCC3 VCC2 to +32 V Total power dissipation Ptot max. 800 mW Operating ambient temperature range Tamb −30 to +85 °C Storage temperature range Tstg −65 to +150 °C November 1983 6 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 CHARACTERISTICS VEE = 0 V; VCC1 = VCC2 = 5 V; VCC3 = 30 V; Tamb = 25 °C; unless otherwise specified SYMBOL Supply voltages MIN. TYP. MAX. CONDITIONS VCC1 3,6 VCC2 3,6 5 12 V VCC3 VCC2 − 31 V AM mode Itot − 16 − mA FM mode Itot − 20 − mA Itot = ICC1 + ICC2 in-lock: BRM = ‘1’; PDM = ‘0’ ICC3 0,3 0,8 1,2 mA IOUT = 0 Tamb −25 − +80 °C AM input frequency fFAM 512 kHz − 32 MHz FM input frequency fFFM 70 − 120 MHz Input voltage at FAM Vi (rms) 30 − 500 mV Input voltage at FFM Vi (rms) 10 − 500 mV Input resistance at FAM Ri − 2 − kΩ Input resistance at FFM Ri − 135 − Ω Input capacitance at FAM Ci − 3,5 − pF Input capacitance at FFM Ci − 3 − pF Vs/Vns − −30 − dB 5 12 V Supply currents(6) Operating ambient temperature RF inputs (FAM, FFM) Voltage ratio allowed between selected and non-selected input see note 1 Crystal oscillator (XTAL) Maximum input frequency fXTAL 4 − − MHz Crystal series resistance Rs − − 150 Ω Input voltage LOW VIL 0 − 0,8 V Input voltage HIGH VIH 2,4 − VCC1 V Input current LOW −IIL − − 10 µA VIL = 0,8 V Input current HIGH IIH − − 10 µA VIH = 2,4 V BUS inputs (DLEN, CLB, DATA) see also Fig.2 and BUS inputs timing (DLEN, CLB, DATA) Lead time for CLB to DLEN note 2 tCLBlead 1 − − µs tTlead 0,5 − − µs Lead time for DATA to the first CLB pulse Set-up time for DLEN tCLBlag1 5 − − µs CLB pulse width HIGH tCLBH 5 − − µs CLB pulse width LOW tCLBL 5 − − µs to CLB November 1983 7 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SYMBOL MIN. SAA1057 TYP. MAX. CONDITIONS Set-up time for DATA tDATAlead 2 − − µs Hold time for DATA to CLB tDATAhold 0 − − µs Hold time for DLEN to CLB tDLENhold 2 − − µs tCLBlag2 2 − − µs tDIST 5 − − µs asynchronous mode tDIST 0,3 − − ms synchronous mode tDIST 1,3 − − ms to CLB Set-up time for DLEN to CLB load pulse Busy time from load pulse to next start of transmission Busy time next transmission after word ‘B’ to other device or next transmission to SAA1057 after word ‘A’ (see also note 5) Sample and hold circuit (TR, TCA, TCB) see also notes 3; 4 Minimum output voltage VTCA, VTCB − 1,3 − V Maximum output voltage VTCA, VTCB − − VCC2−0,7 V Capacitance at TCA CTCA − − 2,2 nF REFH = ‘1’ CTCA − − 2,7 nF REFH = ‘0’ tdis − − 5 µs REFH = ‘1’ tdis − − 6,25 µs REFH = ‘0’ RTR 100 − − Ω external VTR − 0,7 − V Capacitance at TCB CTCB − − 10 nF external Bias current into TCA, TCB Ibias − − 10 nA in-lock ± Idig − 0,4 − mA (external) Discharge time at TCA Resistance at TR Voltage at TR during discharge Programmable current amplifier (PCA) Output current of the dig. phase detector Current gain of PCA CP3 CP2 CP1 CP0 P1 0 0 0 0 GP1 − 0,023 − P2 0 0 0 1 GP2 − 0,07 − P3 0 0 1 0 GP3 − 0,23 − P4 0 1 1 0 GP4 − 0,7 − P5 1 1 1 0 GP5 − 2,3 − November 1983 8 VCC2 ≥ 5 V (only for P1) Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SYMBOL MIN. SAA1057 TYP. MAX. CONDITIONS Ratio between the output current of S/H into PCA and the voltage on STCB − 1,0 − µA/V ∆VTCB − − 1 V in-lock VIN − 1,3 − V in-lock; equal to internal reference voltage minimum VOUT − − 0,5 V −IOUT = 1 mA maximum VOUT VCC3−2 − − V IOUT = 1 mA CTCB Offset voltage on TCB Output amplifier (IN, OUT) Input voltage Output voltages VOUT VCC3−1 − − V IOUT = 0,1 mA ± IOUT 5 − − mA VOUT = 1⁄2 VCC3 Output voltage LOW VTL − − 0,5 V Output voltage HIGH VTH − − 12 V Output current OFF IToff − − 10 µA VTH Output current ON ITon 150 − − µA VTL ∆VCC1/∆VOUT − 77 − dB ∆VCC2/∆VOUT − 70 − dB ∆VCC3/∆VOUT − 60 − dB maximum Maximum output current Test output (TEST)(7) Ripple rejection(8) at fripple = 100 Hz November 1983 9 VOUT ≤ VCC3−3 V Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 Notes 1. Pin 17 (XTAL) can also be used as input for an external clock. The circuit for that is given in Fig.5. The values given in Fig.5 are a typical application example. 2. See BUS information in section ‘operation description’. 3. The output voltage at TCB and TCA is typically 1⁄2 VCC2+0,3 when the tuning system is in-lock via the sample and hold phase detector. The control voltage at TCB is defined as the difference between the actual voltage at TCB and the value calculated from the formula 1⁄2 VCC2+0,3 V. 4. Crystal oscillator frequency fXTAL = 4 MHz. 5. The busy-time after word “A” to another device which has more clock pulses than the SAA1057 (>17) must be the same as the busy-time for a next transmission to the SAA1057. When the other device has a separate DLEN or has less clock pulses than the SAA1057 it is not necessary to keep to this busy-time, 5 µs will be sufficient. 6. When the bus is in the active mode (see BRM in Control Information), 4,5 mA should be added to the figures given. 7. Open collector output. 8. Measured in Fig.6. Fig.5 Circuit configuration showing external 4 MHz clock. APPLICATION INFORMATION Initialize procedure Either a train of at least 10 clock pulses should be applied to the clock input (CLB) or word B should be transmitted, to achieve proper initialization of the device. For the complete initialization (defining all control bits) a transmission of word B should follow. This means that the IC is ready to accept word A. Synchronous/asynchronous operation Synchronous loading of the frequency word into the programmable counter can be achieved when bit ‘SLA’ of word B is set to ‘1’. This mode should be used for small frequency steps where low tuning noise is important (e.g. search and manual tuning). This mode should not be used for frequency changes of more than 31 tuning steps. In this case asynchronous loading is necessary. This is achieved by setting bit ‘SLA’ to ‘0’. The in-lock condition will then be reached more quickly, because the frequency information is loaded immediately into the divider. Restrictions to the use of the programmable current amplifier The lowest current gain (0,023) must not be used in the in-lock condition when the supply voltage VCC2 is below 5 V (CP3, CP2, CP1 and CP0 are all set to ‘0’). This is to avoid possible instability of the loop due to a too small range of the sample and hold phase detector in this condition (see also section ‘Characteristics’). November 1983 10 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 Transient times of the bus signals When the SAA1057 is operating in a system with continuous activity on the bus lines, the transient times at the bus inputs should not be less than 100 ns. Otherwise the signal-to-noise ratio of the tuning voltage is reduced. (1) Values depend on the tuner diode characteristics. Fig.6 Application example of the SAA1057PLL frequency synthesizer module. November 1983 11 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 PACKAGE OUTLINE DIP18: plastic dual in-line package; 18 leads (300 mil) SOT102-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 10 18 pin 1 index E 1 9 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 1.40 1.14 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 0.85 inches 0.19 0.020 0.15 0.055 0.044 0.021 0.015 0.055 0.044 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.033 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-10-14 95-01-23 SOT102-1 November 1983 EUROPEAN PROJECTION 12 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1983 13