INTEGRATED CIRCUITS DATA SHEET TDA9875A Digital TV Sound Processor (DTVSP) Product specification Supersedes data of 1998 Aug 13 File under Integrated Circuits, IC02 1999 Dec 20 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) CONTENTS TDA9875A 10 I2C-BUS CONTROL Introduction Power-up state Slave receiver mode Slave transmitter mode Expert mode 1 FEATURES 1.1 1.2 1.3 Demodulator and decoder section DSP section Analog audio section 10.1 10.2 10.3 10.4 10.5 2 GENERAL DESCRIPTION 11 I2S-BUS DESCRIPTION 2.1 Supported standards 12 APPLICATION INFORMATION 3 ORDERING INFORMATION 13 PACKAGE OUTLINES 4 BLOCK DIAGRAM 14 SOLDERING 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 Demodulator and decoder section Digital signal processing Analog audio section 14.1 14.2 14.3 14.4 Introduction Through-hole mount packages Surface mount packages Suitability of IC packages for wave, reflow and dipping soldering methods 7 LIMITING VALUES 15 DEFINITIONS 8 THERMAL CHARACTERISTICS 16 LIFE SUPPORT APPLICATIONS 9 CHARACTERISTICS 17 PURCHASE OF PHILIPS I2C COMPONENTS 1999 Dec 20 2 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 1 1.1 TDA9875A FEATURES Demodulator and decoder section • Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources • SIF AGC with 24 dB control range • Dual audio Digital-to-Analog Converter (DAC) from DSP to analog crossbar switch, bandwidth 15 kHz • SIF 8-bit Analog-to-Digital Converter (ADC) • Differential Quadrature Phase Shift Keying (DQPSK) demodulation for different standards, simultaneously with 1-channel FM demodulation • Dual audio ADC from analog inputs to DSP • Two dual audio DACs for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension. • Near Instantaneous Companded Audio Multiplex (NICAM) decoding (B/G, I and L standard) • Two-carrier multistandard FM demodulation (B/G, D/K and M standard) 2 • Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and digital multi-channel sound systems in TV sets and satellite receivers. • Optional AM demodulation for system L, simultaneously with NICAM • Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 2.1 DSP section • Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft mute • Plop-free volume control M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF and 8 MHz UHF) and monaural sound. • Automatic Volume Level (AVL) control • Adaptive de-emphasis for satellite • Programmable beeper The AM sound of L/L accent standard is normally demodulated in the first sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator stage, however this gives limited performance. • Monitor selection for FM/AM DC values and signals, with peak detection option • I2S-bus interface for a feature extension (e.g. Dolby Pro Logic) with matrix, level adjust and mute. Korea has a stereo sound system similar to Europe and is supported by the TDA9875A. The differences include deviation, modulation contents and identification. It is based on M standard. Analog audio section • Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output An overview of the supported standards and sound systems and their key parameters is given in Table 1. • User defined full-level/−3 dB scaling for SCART outputs • Output selection of mono, stereo, dual A/B, dual A or dual B The analog multi-channel sound systems (A2, A2+ and A2*) are 2-Carrier Systems (2CS). • 20 kHz bandwidth for SCART-to-SCART copies • Standby mode with function for SCART copies 1999 Dec 20 Supported standards The multistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standards. In other application areas there exists only subsets of these standard combinations otherwise only single standards are transmitted. • Digital crossbar switch for all digital signal sources and destinations 1.3 GENERAL DESCRIPTION 3 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 2.1.1 Table 1 TDA9875A ANALOG 2-CARRIER SYSTEMS Frequency modulation SOUND SYSTEM STANDARD CARRIER FM DEVIATION (kHz) FREQUENCY NOM. MAX. OVER (MHz) MODULATION SC1 BANDWIDTH/ DE-EMPHASIS (kHz/µs) SC2 M mono 4.5 15 25 50 mono − M A2+ 4.5/4.724 15 25 50 1⁄ 2(L + R) 1⁄ 1⁄ 2(L R 15/50 15/75 2(L − R) 15/75 (Korea) B/G A2 5.5/5.742 27 50 80 I mono 6.0 27 50 80 mono − 15/50 D/K A2 6.5/6.742 27 50 80 1⁄ 2(L + R) R 15/50 80 1⁄ 2(L R 15/50 D/K Table 2 A2* 6.5/6.258 27 50 + R) + R) Identification for A2 systems PARAMETER A2/A2* A2+ (KOREA) Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency Stereo identification frequency line frequency 117.5 Hz = ------------------------------------133 line frequency 149.9 Hz = ------------------------------------105 Dual identification frequency line frequency 274.1 Hz = ------------------------------------57 line frequency 276.0 Hz = ------------------------------------57 AM modulation depth 50% 50% 2.1.2 Table 3 2-CARRIER SYSTEMS WITH NICAM NICAM SC1 MODULATION STANDARD FREQUENCY TYPE (MHz) INDEX (%) DEVIATION (kHz) SC2 NICAM (MHz) DEEMPHASIS ROLLOFF (%) NICAM CODING NOM. MAX. NOM. MAX. B/G 5.5 FM − − 27 50 5.85 J17 40 note 1 I 6.0 FM − − 27 50 6.552 J17 100 note 1 D/K 6.5 FM − − 27 50 5.85 J17 40 note 2 L 6.5 AM 54 100 − − 5.85 J17 40 note 1 Notes 1. See “EBU specification” or equivalent specification. 2. Not yet defined. 1999 Dec 20 4 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 2.1.3 TDA9875A SATELLITE SYSTEMS An important specification for satellite TV reception is the ‘Astra specification’. The TDA9875A is suited for the reception of Astra and other satellite signals. Table 4 FM satellite sound CARRIER TYPE Main CARRIER FREQUENCY (MHz) MODULATION INDEX MAXIMUM FM DEVIATION (kHz) MODULATION BANDWIDTH/ DE-EMPHASIS (kHz/µs) 6.50(1) 0.26 85 mono 15/50(2) 50 m/st/d(3) 15/adaptive(4) Sub 7.02/7.20 Sub 7.38/7.56 Sub 7.74/7.92 Sub 8.10/8.28 0.15 Notes 1. For other satellite systems, frequencies of e.g. 5.80, 6.60 or 6.65 MHz can also be received. 2. A de-emphasis of 60 µs, or in accordance with J17, is available. 3. m/st/d = mono, stereo or dual language sound. 4. Adaptive de-emphasis is compatible to transmitter specification. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA9875A SDIP64 plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1 TDA9875AH QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm SOT393-1 1999 Dec 20 5 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 4 TDA9875A BLOCK DIAGRAM SIF2 handbook, full pagewidth SIF1 10 (2) P1 P2 ADDR1 ADDR2 SCL SDA 12 (4) 9 (1) (63) 7 20 (12) 3 (59) 13 (5) I2C-BUS INTERFACE SUPPLY SOUND IF (SIF) INPUT SWITCH AGC, ADC 4 (60) (62) 6 (3) 11 (64) 8 5 (61) (58) 2 IDENTIFICATION FM (AM) DEMODULATION NICAM DEMODULATION (57) 1 (25) 33 XTALI XTALO SYSCLK (26) 34 18 (10) 19 (11) CLOCK 21 (13) A2/SATELLITE DECODER (28) 36 NICAM DECODER (29) 37 (23) 31 (24) 32 ANALOG CROSSBAR SWITCH (21) 29 (39) 47 (40) 48 PEAK DETECTION LEVEL ADJUST (43) 51 LEVEL ADJUST (44) 52 (55) 63 (54) 62 SDI1 SDI2 SDO1 SDO2 SCK WS (33) 41 25 (17) 24 (16) ADC (2) I2S-BUS INTERFACE (34) 42 (36) 44 22 (14) 64 (56) VSSD1 14 (6) VSSD2 49 (41) VSSD3 35 (27) VSSD4 17 (9) (37) 45 DIGITAL SELECT 23 (15) 15 (7) DAC (2) (46) 54 (47) 55 (51) 59 16 (8) (30) 38 AUDIO PROCESSING TDA9875A (TDA9875AH) DAC (2) 28 (20) 30 (22) (32) 40 SUPPLY SCART, DAC, ADC DAC (2) TEST (38) 46 (45) 53 (35) 43 (48) 56 (42) 50 (53) 61 (52) 60 (50) 58 (49) 57 MHB598 MOL MOR AUXOL AUXOR The pin numbers given in parenthesis refer to the TDA9875AH version. Fig.1 Block diagram. 1999 Dec 20 Iref NICAM PCLK SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL i.c. i.c. i.c. i.c. PCAPR PCAPL DIGITAL SUPPLY (31) 39 TEST2 Vref1 26 (18) VDDD2 TEST1 VSSA1 27 (19) VDDD1 CRESET VDEC1 6 VDDA VDEC2 Vref(p) Vref(n) Vref2 Vref3 VSSA2 VSSA3 VSSA4 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 5 TDA9875A PINNING PIN SYMBOL TDA9875A PIN (1) TYPE TDA9875AH DESCRIPTION PCLK 1 57 O NICAM clock output at 728 kHz NICAM 2 58 O serial NICAM data output at 728 kHz ADDR1 3 59 I I2C-bus slave address input 1 SCL 4 60 I I2C-bus clock input SDA 5 61 I/O VSSA1 6 62 S supply ground 1; analog front-end circuitry VDEC1 7 63 − supply voltage decoupling 1; analog front-end circuitry Iref 8 64 − resistor for reference current generator; analog front-end circuitry P1 9 1 I/O SIF2 10 2 I sound IF input 2 Vref1 11 3 − reference voltage 1; analog front-end circuitry SIF1 12 4 I sound IF input 1 ADDR2 13 5 I I2C-bus slave address input 2 VSSD1 14 6 S supply ground 1; digital circuitry VDDD1 15 7 S digital supply voltage 1; digital circuitry CRESET 16 8 − capacitor for Power-on reset VSSD4 17 9 S supply ground 4; digital circuitry XTALI 18 10 I crystal oscillator input XTALO 19 11 O crystal oscillator output P2 20 12 I/O general purpose input/output pin 2 SYSCLK 21 13 O system clock output SCK 22 14 I/O I2S-bus clock input/output WS 23 15 I/O I2S-bus word select input/output SDO2 24 16 O I2S-bus data output 2 (I2S2 output) SDO1 25 17 O I2S-bus data output 1 (I2S1 output) SDI2 26 18 I I2S-bus data input 2 (I2S2 input) SDI1 27 19 I I2S-bus data input 1 (I2S1 input) I2C-bus data input/output general purpose input/output pin 1 TEST1 28 20 I test pin 1; connected to VSSD1 for normal operating mode MONOIN 29 21 I audio mono input TEST2 30 22 I test pin 2; connected to VSSD1 for normal operating mode EXTIR 31 23 I external audio input right channel EXTIL 32 24 I external audio input left channel SCIR1 33 25 I SCART 1 input right channel SCIL1 34 26 I SCART 1 input left channel VSSD3 35 27 S supply ground 3; digital circuitry SCIR2 36 28 I SCART 2 input right channel SCIL2 37 29 I SCART 2 input left channel VDEC2 38 30 − supply voltage decoupling 2; audio analog-to-digital converter circuitry 1999 Dec 20 7 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A PIN SYMBOL TDA9875A PIN (1) TDA9875AH TYPE DESCRIPTION Vref(p) 39 31 − positive reference voltage; audio analog-to-digital converter circuitry Vref(n) 40 32 − reference voltage ground; audio analog-to-digital converter circuitry i.c. 41 33 − internally connected; note 2 i.c. 42 34 − internally connected; note 3 VSSA2 43 35 S supply ground 2; audio analog-to-digital converter circuitry i.c. 44 36 − internally connected; note 3 i.c. 45 37 − internally connected; note 2 Vref2 46 38 − reference voltage 2; audio analog-to-digital converter circuitry SCOR1 47 39 O SCART 1 output right channel SCOL1 48 40 O SCART 1 output left channel VSSD2 49 41 S supply ground 2; digital circuitry VSSA4 50 42 S supply ground 4; audio operational amplifier circuitry SCOR2 51 43 O SCART 2 output right channel SCOL2 52 44 O SCART 2 output left channel Vref3 53 45 − reference voltage 3; audio digital-to-analog converter and operational amplifier circuitry PCAPR 54 46 − post-filter capacitor pin right channel; audio digital-to-analog converter PCAPL 55 47 − post-filter capacitor pin left channel; audio digital-to-analog converter VSSA3 56 48 S supply ground 3; audio digital-to-analog converter circuitry AUXOR 57 49 O headphone (Auxiliary) output right channel AUXOL 58 50 O headphone (Auxiliary) output left channel VDDA 59 51 S analog supply voltage; analog circuitry MOR 60 52 O loudspeaker (Main) output right channel MOL 61 53 O loudspeaker (Main) output left channel LOL 62 54 O line output left channel LOR 63 55 O line output right channel VDDD2 64 56 S digital supply voltage 2; digital circuitry Notes 1. Pin type: I = input, O = output, S = supply. 2. Test pin: CMOS level input; pull-up resistor; can be connected to VSS. 3. Test pin: CMOS 3-state stage; can be connected to VSS. 1999 Dec 20 8 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A handbook, halfpage PCLK 1 64 VDDD2 NICAM 2 63 LOR ADDR1 3 62 LOL SCL 4 61 MOL SDA 5 60 MOR VSSA1 6 59 VDDA VDEC1 7 58 AUXOL Iref 8 57 AUXOR P1 9 56 VSSA3 SIF2 10 55 PCAPL Vref1 11 54 PCAPR SIF1 12 53 Vref3 ADDR2 13 52 SCOL2 VSSD1 14 51 SCOR2 VDDD1 15 50 VSSA4 CRESET 16 VSSD4 17 49 VSSD2 TDA9875A XTALI 18 48 SCOL1 47 SCOR1 XTALO 19 46 Vref2 P2 20 45 i.c. SYSCLK 21 44 i.c. SCK 22 43 VSSA2 WS 23 42 i.c. SDO2 24 41 i.c. SDO1 25 40 Vref(n) SDI2 26 39 Vref(p) SDI1 27 38 VDEC2 TEST1 28 37 SCIL2 MONOIN 29 36 SCIR2 TEST2 30 35 VSSD3 EXTIR 31 34 SCIL1 EXTIL 32 33 SCIR1 MHB071 Fig.2 Pin configuration (TDA9875A). 1999 Dec 20 9 Philips Semiconductors Product specification 49 AUXOR 50 AUXOL 51 VDDA 52 MOR 53 MOL 54 LOL 55 LOR TDA9875A 56 VDDD2 57 PCLK 58 NICAM 59 ADDR1 60 SCL 61 SDA 62 VSSA1 64 Iref handbook, full pagewidth 63 VDEC1 Digital TV Sound Processor (DTVSP) P1 1 48 VSSA3 SIF2 2 47 PCAPL Vref1 3 46 PCAPR SIF1 4 45 Vref3 ADDR2 5 44 SCOL2 VSSD1 6 43 SCOR2 VDDD1 7 42 VSSA4 41 VSSD2 CRESET 8 TDA9875AH VSSD4 9 40 SCOL1 XTALI 10 39 SCOR1 38 Vref2 XTALO 11 P2 12 37 i.c. SYSCLK 13 36 i.c. 35 VSSA2 SCK 14 Fig.3 Pin configuration (TDA9875AH). 1999 Dec 20 10 Vref(n) 32 Vref(p) 31 VDEC2 30 SCIL2 29 SCIR2 28 VSSD3 27 SCIL1 26 SCIR1 25 EXTIL 24 EXTIR 23 TEST2 22 MONOIN 21 TEST1 20 33 i.c. SDI1 19 SDO2 16 SDI2 18 34 i.c. SDO1 17 WS 15 MHB599 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6 6.1.5 FUNCTIONAL DESCRIPTION 6.1 6.1.1 SIF INPUT 6.1.6 AGC A timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data. 6.1.7 MIXER The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. Bit VDSP (see Section 10.4.1) indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The status of the NICAM decoder can be read out from the NICAM status register by the user (see Section 10.4.2). Bit OSB indicates that the decoder has locked to the NICAM data. Bit C4 indicates that the sound conveyed by the FM mono channel is identical to the sound signal conveyed by the NICAM channel. FM AND AM DEMODULATION An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. 1999 Dec 20 NICAM DECODER The device performs all decoding functions in accordance with the “EBU NICAM 728 specification”. After locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence and the device will then synchronize to the periodic frame flag bit C0. The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10). 6.1.4 NICAM DEMODULATION The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock signal onto the NICAM decoder and, for evaluation purposes, to pins PCLK and NICAM. The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen (see Table 15). 6.1.3 FM IDENTIFICATION The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. Demodulator and decoder section Two input pins are provided: SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internal switchable −10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 TDA9875A The error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. The Bit Error Rate (BER) can be calculated using the following equation: bit errors –5 BER = ----------------------- ≈ error byte × 1.74 × 10 total bits 11 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.1.8 Bit CLRPOR (see Section 10.3.2) resets the Power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9875A has to be carried out to ensure reliable operation. NICAM AUTO-MUTE This function is enabled by setting bit AMUTE to logic 0 (see Section 10.3.11). Upper and lower error limits may be defined by writing appropriate values to two registers in the I2C-bus section (see Sections 10.3.13 and 10.3.14). When the number of errors in a 128 ms period exceeds the upper error limit the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM). When the error count is smaller than the lower error limit the NICAM sound is restored. 6.1.12 The reset is guaranteed to be active when: A decision to enable/disable the auto-muting is taken by the microcontroller based on an interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software. • The power supply is within the specified limits (4.75 and 5.5 V) • The crystal oscillator is functioning • The voltage at pin CRESET is below 0.3VDDD (1.5 V if VDDD = 5.0 V, typically below 1.8 V). For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A. By setting bit AMSEL (see Section 10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the first sound carrier. The ADC source selector (see Section 10.3.20) should be set to mono input, where the AM sound signal should be connected. The required capacitor value depends on the gradient of the rising power supply voltage. The time constant of the RC circuit should be clearly larger than the rise time of the power supply, to make sure that the reset condition is always satisfied (see Fig.4), even considering the tolerance spread. To avoid problems with a too slow discharging of the capacitor at power-down, it may be helpful to add a diode from pin CRESET to VDDD. It should be noted that the internal ESD protection diode does not help here as it only conducts at higher voltages. Under difficult power supply conditions (e.g. very slow or non-monotonic ramp-up), it is recommended to drive the reset line from a microcontroller port or the like. CRYSTAL OSCILLATOR The circuitry of the crystal oscillator is fully integrated, only the external 24.576 MHz crystal is needed (see Fig.10). 6.1.10 TEST PINS Test pins TEST1 and TEST2 are active HIGH and in the normal operating mode of the device they are connected to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pins are pulled down to a LOW level with internal resistors. 6.1.11 handbook, halfpage MHB595 VDDD > 4.75 V 5 voltage (V) POWER FAIL DETECTOR 1.5 VCRESET < 0.3VDDD reset active guaranteed The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the Power-on reset bit POR (see Section 10.4.1), will be set to logic 1. 1999 Dec 20 POWER-ON RESET The reset is active LOW. In order to perform a reset at power-up, a simple RC circuit may be used which consists of the integrated passive pull-up resistor and an external capacitor connected to ground. The pull-up resistor has a nominal value of 50 kΩ, which can easily be measured between pins CRESET and VDDD2. Before the supply voltage has reached a certain minimum, the state of the circuit is completely undefined, and it remains in this undefined state unless a reset is applied. The auto-mute function can be disabled by setting bit AMUTE to logic 1. In this condition clicks become audible when the error count increases; the user will hear a signal of degrading quality. 6.1.9 TDA9875A t Fig.4 Reset at power-on. 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 DC FILTER 2 2 2 2 MATRIX AUTOMATIC VOLUME LEVEL MATRIX VOLUME SOFT-MUTE BASS/TREBLE BEEPER 4 LEVEL ADJUST I2S1 2 2 LEVEL ADJUST I2S2 2 13 2 ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS LEVEL ADJUST AND MUTE 2 LEVEL ADJUST DC FILTER MATRIX 2 2 2 Main Auxiliary I2S1 8 FIXED DE-EMPHASIS FM 2 LEVEL ADJUST AND MUTE 2 LEVEL ADJUST NICAM 6 DIGITAL CROSSBAR SELECT SPATIAL PSEUDO VOLUME BASS/TREBLE BASS BOOST CONTOUR SOFT-MUTE BEEPER Philips Semiconductors from ADC Digital signal processing LEVEL ADJUST 2 Digital TV Sound Processor (DTVSP) 6.2 handbook, full pagewidth 1999 Dec 20 2 MATRIX 2 I2S2 10 LEVEL ADJUST 2 MATRIX MATRIX 2 DAC 12 2 4 16 1 I2C-bus MGK108 Product specification TDA9875A Fig.5 DSP data flow diagram. MONITOR SELECT PEAK DETECTION Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.2.1 Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection. LEVEL SCALING All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range from +15 to −15 dB (see Fig.5). It is recommended to scale all input channels to be 15 dB below full-scale (−15 dB full-scale) under nominal conditions. 6.2.2 6.2.6 LOUDSPEAKER (MAIN) CHANNEL The matrix provides the following functions: forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. NICAM PATH The NICAM path has a switchable J17 de-emphasis. 6.2.3 TDA9875A There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. FM (AM) PATH A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The Automatic Volume Level (AVL) function provides a constant output level of −23 dB (full-scale) for input levels between 0 and −29 dB (full-scale). There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s. The de-emphasis function offers fixed settings for the supported standards (50, 60 or 75 µs and J17). Pseudo stereo is based on a phase shift in one channel via a second-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. Volume is controlled individually for each channel ranging from +24 to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). A matrix performs the dematrixing of the A2 stereo, dual and mono signals. 6.2.4 NICAM AUTO-MUTE If NICAM B/G, I or D/K is received, the auto-mute is enabled and the signal quality becomes poor, the digital crossbar switch switches automatically to FM and switches the matrix to channel 1. The automatic switching depends on the NICAM bit error rate. Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. The auto-mute function can be disabled via the I2C-bus. For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A. By setting bit AMSEL (see Section 10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the first sound carrier. The ADC source selector bits (see Section 10.3.20) should be set to mono input, where the AM sound signal should be connected. 6.2.5 Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between +12 and −12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). MONITOR This function provides data words from a number of locations in the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the outputs of the ADC. Source selection and data read-out is performed via the I2C-bus. 1999 Dec 20 Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. 14 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A The beeper volume is adjustable with respect to full-scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. The I2S-bus output matrix provides the following functions: forced mono, stereo, channel swap, channel 1 and channel 2. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel. 6.2.7 HEADPHONE (AUXILIARY) CHANNEL The matrix provides the following functions: forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). 6.2.9 The signal level at the output of the ADC can be adjusted in a range from +15 to −15 dB with 1 dB resolution. The audio ADC itself is scaled to a gain of −6 dB. Balance can be realized by independent control of the left and right channel volume settings. 6.2.10 6.2.11 DIGITAL CROSSBAR SWITCH Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path, NICAM path and from the loudspeaker channel path after matrix and AVL (see Fig.8). Output channels comprise loudspeaker, headphone, I2S1, I2S2 and audio DACs for line output and SCART. I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full-scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. 6.2.12 SIGNAL GAIN There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full-scale (−15 dB full-scale). This means that a volume setting of, say, +15 dB would just produce a full-scale output signal and not cause clipping, if the signal level is nominal. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking. FEATURE INTERFACE The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a range from +15 to −15 dB with 1 dB resolution. Outputs can be disabled to improve EMC performance. 1999 Dec 20 CHANNEL TO THE ANALOG CROSSBAR PATH Level adjust with control positions 0, +3, +6 and +9 dB. Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between +12 and −12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). 6.2.8 CHANNEL FROM THE AUDIO ADC Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions. 15 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.2.13 TDA9875A More information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available on request. EXPERT MODE The TDA9875A provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. 6.2.14 Table 5 DSP FUNCTIONS Overview of DSP functions FUNCTION Bass control for loudspeaker and headphone output Treble control for loudspeaker and headphone output Contour for loudspeaker output Bass boost for loudspeaker output EXPERT MODE yes yes yes yes PARAMETER VALUE UNIT control range −12 to +15 dB resolution 1 dB resolution at frequency 40 Hz control range −12 to +12 dB resolution 1 dB resolution at frequency 14 kHz control range 0 to +18 dB resolution 1 dB resolution at frequency 40 Hz control range 0 to +20 dB resolution 2 dB resolution at frequency 20 Hz corner frequency 350 Hz control range −83 to +24 dB resolution 1 dB mute position at step 1010 1100 no processing time 32 ms Spatial effects yes anti-phase crosstalk positions 30, 40 and 52 % Pseudo stereo yes 90 degrees phase shift at frequency 150, 200 and 300 Hz Beeper additional to the signal in the loudspeaker and headphone channel yes beep frequencies see Section 10.3.38 control range 0 to −93 dB resolution 3 dB Automatic Volume Level (AVL) yes Volume control for each separate channel in loudspeaker and headphone output no Soft mute for loudspeaker and headphone output 1999 Dec 20 mute position at step 0010 0000 step width quasi continuously AVL output level for an input level between 0 and −29 dB (full-scale) −23 dB attack time 10 ms decay time constant 2, 4 and 8 s 16 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) EXPERT MODE FUNCTION General no Level adjust I2S1 and I2S2 inputs yes Level adjust I2S1 and I2S2 outputs yes Level adjust analog crossbar path no Level adjust audio ADC outputs yes TDA9875A PARAMETER VALUE UNIT −3 dB lower corner frequency of DSP 10 Hz −1 dB bandwidth of DSP 14.5 kHz control range −15 to +15 dB resolution 1 dB control range −15 to +15 dB resolution 1 dB mute position at step 0001 0000 control positions 0, 3, 6 and 9 dB control range +15 to −15 dB resolution 1 dB dB Level adjust NICAM path yes control range +15 to −15 resolution 1 dB Level adjust FM path yes control range +15 to −15 dB resolution 1 dB 6.3 Analog audio section handbook, full pagewidth SCART 1 2 −3 dB 2 2 2 SCART 2 external 2 −3 dB 2 2 ANALOG CROSSBAR SWITCH 2 ANALOG MATRIX 2 ANALOG MATRIX 2 ANALOG MATRIX 2 2 D 2 FM 3 dB 2 0 dB 3 dB 2 0 dB SCART 1 SCART 2 Line output 2 A D A NICAM 2 0 dB mono 2 3 dB 2 2 I2S1 2 I2S2 2 I2S1 2 I2S2 2 DSP AND DIGITAL CROSSBAR SWITCH 2 2 D A 2 2 D A Main Auxiliary MGK109 Fig.6 Block diagram for the audio section. 1999 Dec 20 17 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.3.1 TDA9875A 6.3.2 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX There are a number of analog input and output ports with the TDA9875A (see Figs 6 and 8). Analog source selector switches are employed to provide the desired analog signal routing capability. The analog signal routing is performed by the analog crossbar switch section. A dual audio ADC provides the connection to the DSP section and a dual audio DAC provides the connection from the DSP section to the analog crossbar switch. The digital signal routing is performed by a digital crossbar switch. The SCART specification allows for a signal level of up to 2 V (RMS). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9875A, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a −3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with a maximum input of 1.4 V), there are 0/3 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. The basic signal routing philosophy of the TDA9875A is that each switch handles two signal channels at the same time, e.g. left and right, language A and B, directly at the source. Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels (see Fig.7). 6.3.3 left input right input ANALOG MATRIX left output Fig.7 Analog matrix. The analog matrix provides the functions given in Table 6. Analog matrix functions MATRIX OUTPUT MODE LEFT OUTPUT RIGHT OUTPUT 1 left input right input 2 right input left input 3 left input left input 4 right input right input All switches and matrices are controlled via the I2C-bus. 1999 Dec 20 SCART OUTPUTS The SCART outputs employ amplifiers with two gain settings. The gain can be set to 3 or 0 dB via the I2C-bus. The 3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (RMS) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain. right output MGK110 Table 6 EXTERNAL AND MONO INPUTS The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (RMS). By adding external series resistors, the external inputs can be used as an additional SCART input. 6.3.4 handbook, halfpage SCART INPUTS 18 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 6.3.5 6.3.8 LINE OUTPUT The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The 3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4). 6.3.6 6.3.9 STANDBY MODE The standby mode, selected by setting bit STDBY to logic 1 (see Section 10.3.2) disables most functions and reduces power dissipation. The analog crossbar switch and the SCART section remain operational and can be controlled by the I2C-bus to support copying of analog signals from SCART-to-SCART. LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS Unused internal registers may lose their information in the standby mode. Therefore, the device needs to be initialized on returning to the normal operating mode. This can be accomplished in the same way as after a Power-on reset. DUAL AUDIO DAC The TDA9875A contains three dual audio DACs, one for the connection from the DSP to the analog crossbar switch section and two for the loudspeaker and headphone outputs. Each of the three dual low-noise high-dynamic range DACs consists of two 15-bit DACs with current outputs, followed by a buffer operational amplifier. The audio DACs operate with four-fold oversampling and noise shaping. 1999 Dec 20 DUAL AUDIO ADC There is one dual audio ADC in the TDA9875A for the connection of the analog crossbar switch section to the DSP. The dual audio ADC consists of two bitstream third-order sigma-delta audio ADCs and a high-order decimation filter. Signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the DSP. 6.3.7 TDA9875A 6.3.10 SUPPLY GROUND The different supply grounds VSS are internally connected via the substrate. It is recommended to connect all ground pins by means of a copper plane close to the pins. 19 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DIGITAL MATRIX SCART 2 ADC −6 dB AUTOMATIC VOLUME LEVEL DIGITAL MATRIX mono DIGITAL MATRIX 20 FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS STEREO DECODER FM LEVEL ADJUST DIGITAL MATRIX NICAM part I2S1 DE-EMPHASIS HEADPHONE CHANNEL PROCESSING DAC Main NICAM LEVEL ADJUST I2S1 INPUT LEVEL ADJUST DIGITAL MATRIX Fig.8 Audio signal flow diagram. I2S1 OUTPUT LEVEL ADJUST I2S1 I2S2 I2S2 OUTPUT LEVEL ADJUST DAC GAIN ANALOG MATRIX BUFFER 0/+3 dB ANALOG MATRIX BUFFER 0/+3 dB ANALOG MATRIX BUFFER 0/+3 dB Line SCART 1 DAC SCART 2 MHB600 Product specification I2S2 INPUT LEVEL ADJUST Auxiliary TDA9875A I2S2 NICAM DECODER DAC ADC LEVEL ADJUST external FM/AM part LOUDSPEAKER CHANNEL PROCESSING Philips Semiconductors Digital TV Sound Processor (DTVSP) handbook, full pagewidth 1999 Dec 20 SCART 1 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD DC supply voltage −0.5 +6.0 V ∆VDD voltage differences between two VDD pins − 550 mV Vn voltage on any other pin −0.5 VDD + 0.5 V IDDD, ISSD DC current per digital supply pin − ±180 mA Ilu(prot) latch-up protection current 100 − mA Ptot total power dissipation − 1.0 W Tstg storage temperature −55 +125 °C Tamb ambient temperature −20 +70 °C Ves electrostatic handling voltage note 1 −2000 +2000 V note 2 −200 +200 V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ. 2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω. 8 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Dec 20 PARAMETER CONDITIONS VALUE UNIT TDA9875A (SDIP64) 40 K/W TDA9875AH (QFP64) 50 K/W thermal resistance from junction to ambient 21 in free air Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 9 CHARACTERISTICS VSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain settings in accordance with note 1; VDD = 5 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with “EBU specification”; 1 kΩ measurement source resistance for AF inputs; with external components of Fig.10; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD1 digital supply voltage 1 4.75 5.0 5.5 V VSSD1 digital supply ground 1 note 2 − 0.0 − V IDDD1 digital supply current 1 VDDD2 digital supply voltage 2 VDDD1 = 5.0 V 58 73 88 mA 4.75 5.0 5.5 V VSSD2 digital supply ground 2 note 2 − 0.0 − V IDDD2 digital supply current 2 VDDD2 = 5.0 V; system clock output disabled 0.1 0.4 2 mA VSSD3 digital supply ground 3 note 2 − 0.0 − V VSSD4 digital supply ground 4 note 2 − 0.0 − V VDDA analog supply voltage 4.75 5.0 5.5 V IDDA analog supply current for DAC part VDDA = 5.0 V; digital silence 44 56 68 mA VSSA1 analog ground for analog front-end note 2 − 0.0 − V VSSA2 analog ground for audio ADC part note 2 − 0.0 − V VSSA3 analog ground for audio DAC part note 2 − 0.0 − V VSSA4 analog ground for SCART − 0.0 − V Demodulator supply decoupling and references VDEC1 analog supply decoupling voltage for demodulator part 3.0 3.3 3.6 V Vref1 analog reference voltage for demodulator part − 2 − V Iref1(sink) sink current at pin Vref1 − 200 − µA 3.0 3.3 3.6 V − 50 − % Audio supply decoupling and references VDEC2 analog supply decoupling voltage for audio ADC part Vref2 reference voltage ratio for audio ADCs ZVref2-VDEC2 impedance pins Vref2 to VDEC2 − 20 − kΩ ZVref2-VSSA2 impedance pins Vref2 to VSSA2 − 20 − kΩ Vref3 reference voltage ratio for audio DAC and operational amplifier − 50 − % ZVref3-VDDA impedance pins Vref3 to VDDA − 20 − kΩ ZVref3-VSSA3 impedance pins Vref3 to VSSA3 − 20 − kΩ 1999 Dec 20 referenced to VDEC2 and VSSA2 referenced to VDDA and VSSA3 22 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875A CONDITIONS MIN. TYP. MAX. UNIT Power fail detector Vth(pf) power fail threshold voltage − 3.9 − − V Digital inputs and outputs INPUTS CMOS level input, pull-down (pins TEST1 and TEST2) VIL LOW-level input voltage − VIH HIGH-level input voltage 0.7VDDD − − V Ci input capacitance − − 10 pF Zi input impedance − 50 − kΩ − − 0.3VDDD V 0.3VDDD V CMOS level input, hysteresis, pull-up (pin CRESET) VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDDD − − V Vhys hysteresis voltage − 1.3 − V Ci input capacitance − − 10 pF Zi input impedance 30 50 − kΩ INPUTS/OUTPUTS I2C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I2C-bus operation (pins SCL and SDA) VIL LOW-level input voltage − − VIH HIGH-level input voltage 0.7VDDD − 0.3VDDD V − V Vhys hysteresis voltage − 0.05VDDD − V ILI input leakage current − − ±10 µA Ci input capacitance − − 10 pF VOL LOW-level output voltage − − 0.6 V CL load capacitance − − 400 pF TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1 and SDI2) VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V Ci input capacitance − − 10 pF VOL LOW-level output voltage − − 0.4 V VOH HIGH-level output voltage 2.4 − − V CL load capacitance − − 100 pF Zi input impedance − 50 − kΩ − 0.3VDDD V OUTPUTS CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK) VOL LOW-level output voltage − VOH HIGH-level output voltage 0.7VDDD − CL load capacitance ILIZ 3-state leakage current 1999 Dec 20 Vi = 0 to VDDD 23 − V − − 100 pF − − ±10 µA Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875A CONDITIONS MIN. TYP. MAX. UNIT SIF1 and SIF2 analog inputs VSIF(max)(p-p) VSIF(min)(p-p) maximum composite SIF input SIF input level adjust 0 dB − voltage for clipping SIF input level adjust −10 dB − (peak-to-peak value) minimum composite SIF input voltage for lower limit of AGC (peak-to-peak value) SIF input level adjust 0 dB − SIF input level adjust −10 dB − 941 − mV 2976 − mV 59 − mV 188 − mV AGC AGC range − 24 − dB fi input frequency 4 − 9.2 MHz Ri input resistance 10 − − kΩ AGCLEV = 0 Ci input capacitance − 7.5 11 pF ∆fFM FM deviation B/G standard; THD < 1% ±100 − − kHz ∆fFM(FS) FM deviation full-scale level terrestrial FM; level adjust 0 dB ±150 − − kHz C/NFM FM carrier-to-noise ratio NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; “CCIR468”; quasi peak − 77 − C/NN NICAM carrier-to-noise ratio NN bandwidth = 6 MHz; bit error rate = 10−3; white noise − 66 − αct crosstalk attenuation SIF1 to SIF2 fi = 4 to 9.2 MHz; note 3 50 − − dB from FM source to any output; Vo = 1 V (RMS) with low-pass filter − 0.3 0.5 % from NICAM source to any output; Vo = 1 V (RMS) with low-pass filter − 0.1 0.3 % SC1 from FM source to any output; Vo = 1 V (RMS); “CCIR468”; quasi peak 64 70 − dB SC2 from FM source to any output; Vo = 1 V (RMS); “CCIR468”; quasi peak 60 66 − dB NICAM source; Vo = 1 V (RMS); note 4 − − − from FM source to any output 14.5 15 − kHz from NICAM source to any output 14.5 15 − kHz from FM or NICAM to any output; fref = 1 kHz; inclusive pre-emphasis and de-emphasis − ±2 − dB dB ------Hz dB ------Hz Demodulator performance THD + N S/N B−3dB fres 1999 Dec 20 total harmonic distortion plus noise signal-to-noise ratio −3 dB bandwidth frequency response 20 Hz to 14 kHz 24 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875A CONDITIONS MIN. αcs(dual) dual signal channel separation note 5 65 αcs(stereo) stereo channel separation note 6 40 αAM AM suppression for FM AM: 1 kHz, 30% modulation; 50 reference: 1 kHz, 50 kHz deviation S/NAM AM demodulation SIF level 100 mV (RMS); 54% AM; 1 kHz AF; “CCIR468”; quasi peak 36 TYP. MAX. UNIT − dB 45 − dB − − dB 45 − dB % 70 IDENTIFICATION FOR FM SYSTEMS modp pilot modulation for identification 25 50 75 C/Np pilot sideband carrier-to-noise ratio for identification start − 27 − fident identification window 116.85 − 118.12 dB ------Hz B/G stereo slow mode Hz medium mode 116.11 − 118.89 Hz fast mode 114.65 − 120.46 Hz B/G dual tident(on) tident(off) total identification time ON total identification time OFF slow mode 273.44 − 274.81 Hz medium mode 272.07 − 276.20 Hz fast mode 270.73 − 277.60 Hz slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s − 500 − mV Analog audio inputs MONO INPUT AND EXTERNAL INPUT Vi(nom)(rms) nominal level input voltage (RMS value) Vi(clip)(rms) clipping level input voltage (RMS value) THD < 3%; note 7 1250 1400 − mV Ri input resistance note 7 28 35 42 kΩ Vi(nom)(rms) nominal level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; note 8 − 350 − mV Vi(clip)(rms) clipping level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; THD < 3%; notes 7 and 8 1250 1400 − mV Ri input resistance note 7 28 35 42 kΩ SCART INPUTS 1999 Dec 20 25 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875A CONDITIONS MIN. TYP. MAX. UNIT Analog audio outputs LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS Vo(clip)(rms) clipping level output voltage (RMS value) THD < 3% 1250 Ro output resistance 150 RL(AC) AC load resistance 10 RL(DC) DC load resistance 10 − mV 250 375 Ω − − kΩ − − kΩ 1400 CL load capacitance − 10 12 nF Voffset(DC) static DC offset voltage − 30 70 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz 80 − − dB Gro(main,aux) roll-off gain at 14.5 kHz for Main and Auxiliary channels from any source −3 −2 − dB fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB PSRRmain,aux power supply ripple rejection for Main and Auxiliary channels SCART OUTPUTS AND LINE OUTPUT Vo(nom)(rms) nominal level output voltage (RMS value) 3 dB amplification − 500 − mV Vo(clip)(rms) clipping level output voltage (RMS value) THD < 3% 1250 1400 − mV Ro output resistance 150 250 375 Ω RL(AC) AC load resistance 10 − − kΩ RL(DC) DC load resistance 10 − − kΩ CL load capacitance − − 2.5 nF Voffset(DC) static DC offset voltage output amplifiers at 3 dB position − 30 50 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz 80 − − dB B bandwidth from SCART, external and mono sources; −3 dB bandwidth 20 − − kHz from DSP sources; −3 dB bandwidth 14.5 − − kHz fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB PSRR 1999 Dec 20 power supply ripple rejection 26 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875A CONDITIONS MIN. TYP. MAX. UNIT Audio performance THD + N total harmonic distortion plus noise Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 15 kHz; note 9 − 0.1 0.3 % from I2S-bus to any analog − audio output 0.1 0.3 % SCART-to-SCART copy − 0.1 0.3 % SCART-to-Main copy − 0.2 0.5 % 73 77 − dB from I2S-bus to any analog 78 audio output 85 − dB SCART-to-SCART copy 78 85 − dB SCART-to-Main copy 73 77 − dB between any analog input pairs; fi = 1 kHz 70 − − dB between any analog output pairs; fi = 10 kHz 65 − − dB between left and right of any input pair 65 − − dB between left and right of any output pair 60 − − dB output amplifier in 3 dB position; Rext = 15 kΩ ±10% −1.5 0 +1.1 dB output amplifier in 0 dB position; Rext = 15 kΩ ±10% −4.5 −3.0 −1.9 dB from any analog audio input to I2S-bus S/N signal-to-noise ratio reference voltage Vo = 1.4 V (RMS); fi = 1 kHz; “CCIR468”; quasi peak; note 9 from any analog audio input to I2S-bus αct αcs GA crosstalk attenuation channel separation gain from SCART-to-SCART with −3 dB input voltage divider Crystal specification (fundamental mode) fxtal crystal frequency − 24.576 − MHz CL load capacitance − 20 − pF C1 series capacitance − 20 − fF C0 parallel capacitance − − 7 pF Φpull pulling sensitivity CL changed from 18 to 16 pF − 25 − RR equivalent series resistance at nominal frequency − − 30 Ω RN equivalent series resistance of unwanted mode 2RR − − Ω ∆T temperature range −20 +25 +70 °C 1999 Dec 20 27 –6 10 ----------pF Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER XJ adjustment tolerance XD drift XA ageing TDA9875A CONDITIONS across temperature range MIN. TYP. MAX. UNIT − − ±30 10−6 − − ±30 10−6 − − ±5 –6 10 ----------year Notes 1. Definitions of levels and level setting: a) The full-scale level for analog audio signals is 1.4 V (RMS). b) The nominal level at the digital crossbar switch is defined at −15 dB (full-scale). c) Nominal audio input levels for external and mono: 500 mV (RMS) at −9 dB (full-scale). d) See also Tables 7 and 8. 2. All analog and digital supply ground pins are connected internally. 3. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference. Switch to the other SIF input to which no signal is connected and which is terminated with 50 Ω. Now measure the 1 kHz crosstalk signal level. The SIF source resistance should be low (50 Ω). 4. NICAM in accordance with “EBU specification”. Audio performance is limited by the dynamic range of the NICAM728 system. Due to compansion, the quantization noise is never lower than −62 dB (unweighted RMS) with respect to the input level. 5. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output; Vo = 1 V (RMS) of modulated channel. 6. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output; Vo = 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of the transmitter. 7. If the supply voltage for the TDA9875A is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used. 8. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the 5 V supply voltage for the TDA9875A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve SCART-to-SCART copies with 0 dB gain, there are 3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is larger than 1.4 V (RMS). 9. ADC level adjust is 6 dB, all other level adjusts are 0 dB. If an external −3 dB divider is used set output buffer gain to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB. 1999 Dec 20 28 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... STANDARD M B/G I D/K MODE 2 channel 15 kHz deviation 2 channel 27 kHz deviation NOMINAL LEVEL AT FM/NICAM DEMODULATOR CARRIER FREQUENCY MODE IDENT DE-EMPHASIS LEVEL OUTPUT ADJUST −24 dB (full-scale); note 2 −19 dB (full-scale) NICAM −11.2 dB (full-scale) −18 dB (full-scale) NICAM −15.8 dB (full-scale) −23 dB (full-scale) 2 channel 27 kHz deviation −19 dB (full-scale) 29 2 channel 27 kHz deviation −19 dB (full-scale) 2 channel 27 kHz deviation −19 dB (full-scale) NICAM L/L accent TRANSMITTER NOMINAL MODULATION DEPTH NICAM −11.2 dB (full-scale) −18 dB (full-scale) 54% AM −19 dB (full-scale) 1 4.5 MHz FM − 75 µs +9 dB 2 4.724 MHz FM on 75 µs +9 dB 1 5.5 MHz FM − 50 µs +4 dB 2 5.742 MHz FM on 50 µs +4 dB 1 5.5 MHz FM − 50 µs +4 dB 2 5.85 MHz NICAM off 1 6.0 MHz FM 2 6.552 MHz NICAM off − J17 +3 dB 50 µs +4 dB J17 +8 dB 1 6.5 MHz FM − 50 µs +4 dB 2 6.742 MHz FM on 50 µs +4 dB 1 6.5 MHz FM − 50 µs +4 dB 2 6.25 MHz FM on 50 µs +4 dB 1 6.5 MHz FM − 50 µs +4 dB 2 5.742 MHz FM on 50 µs +4 dB − 50 µs +4 dB J17 +3 dB 50 µs +5 dB J17 +3 dB 1 6.5 MHz FM 2 5.85 MHz NICAM off 1 6.5 MHz AM 2 5.85 MHz NICAM off − Philips Semiconductors Level setting FM, AM and NICAM at 0 dB (full-scale) = 1.4 V (RMS); note 1 Digital TV Sound Processor (DTVSP) 1999 Dec 20 Table 7 Notes 1. Nominal level at digital crossbar is defined at −15 dB (full-scale). DAC gain setting 6 dB. Output buffer setting 0 dB. Nominal SCART output level 500 mV (RMS). 2. For stereo signals the output level is 6 dB lower. The level adjust has to be increased by 6 dB. Product specification TDA9875A This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SOURCE TRANSMITTER MAXIMUM MODULATION DEPTH NOMINAL LEVEL AT DEMODULATOR OUTPUT FM LEVEL ADJUST SETTING SAT FM, stereo 50 kHz deviation −13 dB (full-scale) +4 dB SAT FM, mono 85 kHz deviation −9 dB (full-scale) 0 dB MAXIMUM LEVEL AT CROSSBAR −9 dB (full-scale) DAC GAIN SETTING +6 dB OUTPUT BUFFER 0 dB NOMINAL SCART OUTPUT VOLTAGE 1 V (RMS) Philips Semiconductors Level setting SAT FM at 0 dB (full-scale) = 1.4 V (RMS) 30 Digital TV Sound Processor (DTVSP) 1999 Dec 20 Table 8 Product specification TDA9875A Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10 I2C-BUS CONTROL 10.2 10.1 At power-up the device is in the following state: Introduction • All outputs muted The TDA9875A is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to enable the controlling microcontroller to determine whether any action is required. • No sound carrier frequency loaded • General-purpose I/O pins ready for input (HIGH) • Input SIF1 selected with: – AGC on The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins ADDR1 and ADDR2 (see Table 9). Table 9 – Small hysteresis – SIF input level shift 0 dB. • Demodulators for both sound carriers set to FM with: – Identification for B/G and D/K, response time 1 s – Level adjust set to 0 dB – De-emphasis 50 µs – Matrix set to mono. • Main channel set to FM input with: Possible slave addresses – Spatial off SLAVE ADDRESS ADDR2 ADDR1 – Pseudo off A6 A5 A4 A3 A2 A1 A0 LOW LOW 1 0 1 1 0 0 0 LOW HIGH 1 0 1 1 0 0 1 HIGH LOW 1 0 1 1 0 1 0 HIGH HIGH 1 0 1 1 0 1 1 – AVL off – Volume mute – Bass flat – Treble flat – Contour off – Bass boost flat. The I2C-bus interface remains operational in the standby mode of the TDA9875A to allow control of the analog source selectors with regard to SCART-to-SCART copying. • Auxiliary channel set to FM input with: – Volume mute – Bass flat The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. – Treble flat. • Feature interface all outputs off • Beeper off The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed when the supply voltage of the TDA9875A is not connected. 1999 Dec 20 Power-up state • Monitoring of carrier 1 FM demodulator DC output. After power-up a device initialization has to be performed via the I2C-bus to put the TDA9875A into the proper mode of operation, in accordance with the desired TV standard, audio control settings, etc. 31 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3 TDA9875A Slave receiver mode As a slave receiver, the TDA9875A provides 46 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. Table 10 I2C-bus; slave address, subaddress and data format S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA ACK P Table 11 Explanation of Table 10 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge by slave SUBADDRESS address of register to write to DATA data byte to be written into register P STOP condition It is allowed to send more than one data byte per transmission to the TDA9875A. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with ACK (acknowledge). There is no ‘wrap-around’ of subaddresses. Commands and data are processed as soon as they have been completely received. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function are ignored. Table 12 Format for a transmission employing auto-increment of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA BYTE A(1) DATA ACK P Note 1. n data bytes with auto-increment of subaddresses. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will then not be executed. 1999 Dec 20 32 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 13 Overview of the slave receiver registers DATA SUBADDRESS (DECIMAL) MSB 0 0 0 s g g g g g AGC level shift, AGC gain selection 1 c c c c c c c c general configuration 2 p 0 0 m m s s s monitor select, peak detector on/off 3 f f f f f f f f carrier 1 frequency; most significant part 4 f f f f f f f f carrier 1 frequency 5 f f f f f f f f carrier 1 frequency; least significant part 6 f f f f f f f f carrier 2 frequency; most significant part 7 f f f f f f f f carrier 2 frequency 8 f f f f f f f f carrier 2 frequency; least significant part 9 c c c c c c c c demodulator configuration 10 d d d d d d d d FM de-emphasis 11 0 0 0 0 0 m m m FM matrix 12 0 0 0 l l l l l channel 1 output level adjust 13 0 0 0 l l l l l channel 2 output level adjust 14 t t 0 c 0 c c c NICAM configuration 15 0 0 0 l l l l l NICAM output level adjust FUNCTION LSB 16 l l l l l l l l NICAM lower error limit 17 u u u u u u u u NICAM upper error limit 18 m m m m m m m m audio mute control 19 g m m m g s s s DAC output select 20 0 g m m 0 s s s SCART 1 output select 21 0 g m m 0 s s s SCART 2 output select 22 0 g m m 0 0 0 s line output select 23 s s s l l l l l ADC output select 24 0 m m m 0 s s s Main channel select 25 0 0 s s p p a a audio effects (AVL, pseudo and spatial) 26 v v v v v v v v volume control, Main left 27 v v v v v v v v volume control, Main right 28 0 0 0 c c c c c contour control, Main 29 0 0 0 b b b b b bass control, Main 30 0 0 0 t t t t t treble control, Main 31 0 m m m 0 s s s Auxiliary channel select 32 v v v v v v v v volume control, Auxiliary left 33 v v v v v v v v volume control, Auxiliary right 34 0 0 0 b b b b b bass control, Auxiliary 35 0 0 0 t t t t t treble control, Auxiliary 36 0 0 0 c c c c c feature interface configuration 37 0 m m m 0 s s s I2S1 output select 1999 Dec 20 33 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A DATA SUBADDRESS (DECIMAL) MSB 38 0 0 0 i i i i i I2S1 input level adjust 39 0 0 0 o o o o o I2S1 output level adjust 40 0 m m m 0 s s s I2S2 output select 41 0 0 0 i i i i i I2S2 input level adjust 42 0 0 0 o o o o o I2S2 output level adjust 43 0 0 0 0 0 f f f beeper frequency FUNCTION LSB 44 0 0 v v v v v v beeper volume, Main and Auxiliary 45 b b b b b b b b bass boost, Main left and right The following sub-sections provide a detailed description of the slave receiver registers. 10.3.1 AGC GAIN REGISTER If the automatic gain control function is switched off in the general configuration register, the contents of this register will define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control function, the latest gain control setting is copied to the AGC gain register. If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with −10 dB. The AGCLEV bit is also active if the automatic gain function is enabled. It should be noted that the input voltages should be considered as approximate target values. Table 14 Subaddress 0 (note 1) BIT NAME VALUE 7 (MSB) B7 0 set to logic 0 6 B6 0 set to logic 0 5 AGCLEV 1 input signal scaled with −10 dB 0 input signal not scaled − gain control bits (see Table 15) 4 AGCGAIN DESCRIPTION 3 2 1 0 (LSB) Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 34 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 15 Gain control bits MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 AGC GAIN (dB) SIF INPUT VOLTAGE [mV (p-p)] 0 0 0/1 1 1 1 1 1 0.0 941/2976 0 0 0/1 1 1 1 1 0 0.8 861/2723 0 0 0/1 1 1 1 0 1 1.5 788/2490 0 0 0/1 1 1 1 0 0 2.3 720/2278 0 0 0/1 1 1 0 1 1 3.1 659/2084 0 0 0/1 1 1 0 1 0 3.9 603/1906 0 0 0/1 1 1 0 0 1 4.6 551/1744 0 0 0/1 1 1 0 0 0 5.4 504/1595 0 0 0/1 1 0 1 1 1 6.2 461/1459 0 0 0/1 1 0 1 1 0 7.0 422/1334 0 0 0/1 1 0 1 0 1 7.7 386/1221 0 0 0/1 1 0 1 0 0 8.5 353/1117 0 0 0/1 1 0 0 1 1 9.3 323/1021 0 0 0/1 1 0 0 1 0 10.1 295/934 0 0 0/1 1 0 0 0 1 10.8 270/855 0 0 0/1 1 0 0 0 0 11.6 247/782 0 0 0/1 0 1 1 1 1 12.4 226/715 0 0 0/1 0 1 1 1 0 13.2 207/654 0 0 0/1 0 1 1 0 1 13.9 189/598 0 0 0/1 0 1 1 0 0 14.7 173/547 0 0 0/1 0 1 0 1 1 15.5 158/501 0 0 0/1 0 1 0 1 0 16.3 145/458 0 0 0/1 0 1 0 0 1 17.0 132/419 0 0 0/1 0 1 0 0 0 17.8 121/383 0 0 0/1 0 0 1 1 1 18.6 111/350 0 0 0/1 0 0 1 1 0 19.4 101/321 0 0 0/1 0 0 1 0 1 20.1 93/293 0 0 0/1 0 0 1 0 0 20.9 85/268 0 0 0/1 0 0 0 1 1 21.7 78/245 0 0 0/1 0 0 0 1 0 22.5 71/224 0 0 0/1 0 0 0 0 1 23.2 65/205 0 0 0/1 0 0 0 0 0 24.0 59/188 (note 1) Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 35 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.2 TDA9875A GENERAL CONFIGURATION REGISTER Table 16 Subaddress 1 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) P2OUT − 6 P1OUT − 5 STDBY 1 This bit controls the general purpose input/output pin P2. The contents of this bit is written directly to the corresponding pin. If input is desired, the bit must be set to logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected in the device status register (see Section 10.4.1). This bit controls the general purpose input/output pin P1. The contents of this bit is written directly to the corresponding pin. If input is desired, the bit must be set to logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected in the device status register (see Section 10.4.1). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. The IC is in the standby mode. Most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from SCART-to-SCART. The IC is in the normal operating mode. On return from standby mode, the device is in its Power-on reset mode and needs to be re-initialized. Causes initialization of the TDA9875A to its default settings. This has the same effect as a Power-on reset. If there is a conflict between the default settings and any bit set to logic 1 in this register, the bits of this register have priority over the corresponding default setting. Automatically reset to logic 0 after initialization. When set to logic 0, the TDA9875A is in its normal operating mode. Resets the power fail detector to LOW. This bit is automatically reset to logic 0 after bit POR in the device status register has been reset. A longer decay time is selected for input signals with strong video modulation (intercarrier). This bit only has an effect when bit AGCOFF = 0. Selects normal attack and decay times for the AGC. Forces the AGC block to a fixed gain as defined in the AGC gain register. The automatic gain control function is enabled and the contents of the AGC gain register is ignored. Selects pin SIF2 for input (recommended for satellite tuner). Selects pin SIF1 for input (terrestrial TV). 0 4 INIT 1 0 3 CLRPOR 1 0 2 AGCSLOW 1 1 AGCOFF 0 1 0 0 (LSB) SIFSEL 1 0 Note 1. The default setting at power-up is 1100 0000. 1999 Dec 20 36 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.3 TDA9875A MONITOR SELECT REGISTER This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in FM mode, while magnitude is supplied in AM mode. Data can be read-out in the I2C-bus slave transmitter mode. By reading out level read-out registers (see Section 10.4) the current peak level will be reset. Table 17 Subaddress 2 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) PEAKMON 1 selects the peak level of a source to be monitored 0 the last sample will be supplied 6 B6 0 default value 5 B5 0 default value 4 B4 − monitor output (see Table 18) 3 B3 2 B2 − signal source (see Table 19) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 18 Monitor output B4 B3 MONITOR OUTPUT 0 0 L input + R input ------------------------------------------2 0 1 L input (channel 1, respectively) 1 0 R input (channel 2, respectively) Table 19 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 DC output of FM demodulator 0 0 1 audio magnitude/phase, FM demodulator output 0 1 0 crossbar input from FM/AM channel 0 1 1 crossbar input from NICAM channel 1 0 0 crossbar input from I2S1 channel 1 0 1 crossbar input from I2S2 channel 1 1 0 crossbar input from audio ADC channel 1 1 1 input to Main channel DAC (without beeper) Note 1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available. 1999 Dec 20 37 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.4 TDA9875A Table 20 Subaddresses 3 to 5 CARRIER 1 FREQUENCY REGISTER The three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: f mix 24 data = --------- × 2 f clk SUBADDRESS BIT 3 7 (MSB) 6 carrier 1 frequency; most significant part 5 where: 4 data = 24-bit frequency control word 3 fmix = desired sound carrier frequency 2 fclk = 12.288 MHz (clock frequency of mixer) 1 224 = 16777216 (number of steps in a 24-bit word size). 0 4 Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9875A (data = 7509333 in decimal notation or 72555 in hexadecimal): 01110010 10010101 01010101. 7 carrier 1 frequency 6 5 4 3 As three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. 2 1 0 5 The default setting at power-up is 0000 0000 for all three bytes. 7 6 5 Most significant part at subaddress 3 and least significant part at subaddress 5 (see Table 20). 4 3 2 1 0 (LSB) 1999 Dec 20 DESCRIPTION 38 carrier 1 frequency; least significant part Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.5 TDA9875A CARRIER 2 FREQUENCY REGISTER Same as for sound carrier 1, except for subaddresses (subaddresses 6 to 8). If the carrier 2 frequency register is used, it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier. 10.3.6 DEMODULATOR CONFIGURATION REGISTER It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. Switching the identification off will reset the associated hardware to a defined state. Table 21 Subaddress 9 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) IDMOD1 − 6 IDMOD0 these bits define the response time after which a FM sound mode identification result may be expected; the longer the time, the more reliable the identification (see Table 22) 5 IDAREA 1 selects FM identification frequencies in accordance with the specification for Korea 0 selects frequencies for Europe (B/G and D/K standard) 4 FILTBW1 − selects filter bandwidth (see Table 23) 3 CH2MOD1 − 2 CH2MOD0 channel 2 receive mode: these bits control the hardware for the second sound carrier (see Table 24); the NICAM mode employs a wider bandwidth of the decimation filters than the FM mode 1 FILTBW0 − selects the filter bandwidth (see Table 23) 0 (LSB) CH1MODE 1 selects the hardware for the first sound carrier to operate in AM mode 0 FM mode is assumed; this applies to both terrestrial and satellite FM reception Notes 1. The default setting at power-up is 0000 0000. Table 22 Identification mode B7 B6 IDENT MODE 0 0 slow 0 1 medium 1 0 fast 1 1 off/reset Table 23 Filter bandwidth channel 1 and channel 2 B4 B1 FILTER BANDWIDTH CH1 CH2 FILTER MODES 0 0 narrow narrow recommended for nominal terrestrial broadcast conditions and SAT with 2 carriers 0 1 extra wide narrow recommended only for high-deviation SAT mono carriers (e.g. obsolete Main channel on Astra) 1 0 medium medium recommended for moderately overmodulated broadcast conditions 1 1 wide wide 1999 Dec 20 recommended for strongly overmodulated broadcast conditions 39 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 24 Channel 2 receive mode B3 B2 CHANNEL 2 0 0 FM 0 1 AM 1 0 NICAM 10.3.7 FM DE-EMPHASIS REGISTER This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of A2 reception, both groups must be set to the same characteristics. Table 25 Subaddress 10 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) ADEEM2 1 Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2). 0 The adaptive de-emphasis is off. − Time constant selection for FM de-emphasis (see Table 26). 1 Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2). 0 The adaptive de-emphasis is off. − Time constant selection for FM de-emphasis (see Table 27). 6 B6 5 B5 4 B4 3 ADEEM1 2 B2 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. 2. The FM de-emphasis gain is 0 dB at 40 Hz. Table 26 De-emphasis sound carrier 2 B6 B5 B4 DE-EMPHASIS 0 0 0 50 µs (Europe) 0 0 1 60 µs 0 1 0 75 µs (M standard) 0 1 1 J17 1 0 0 off Table 27 De-emphasis sound carrier 1 B2 B1 B0 DE-EMPHASIS 0 0 0 50 µs (Europe) 0 0 1 60 µs 1999 Dec 20 40 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A B2 B1 B0 DE-EMPHASIS 0 1 0 75 µs (M standard) 0 1 1 J17 1 0 0 off 10.3.8 FM MATRIX REGISTER This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. Table 28 Subaddress 11 (note 1) BIT NAME VALUE 7 (MSB) B7 0 default value 6 B6 0 default value 5 B5 0 default value 4 B4 0 default value 3 B3 0 default value − dematrixing characteristics (see Table 29) 2 B2 1 B1 0 (LSB) B0 DESCRIPTION Note 1. The default setting at power-up is 0000 0000. Table 29 Dematrixing characteristics B2 B1 B0 L OUTPUT R OUTPUT 0 0 0 CH1 input; note 1 CH1 input; note 1 mono 1 0 0 1 CH2 input; note 2 CH2 input; note 2 mono 2 0 1 0 CH1 input; note 1 CH2 input; note 2 dual 0 1 1 CH2 input; note 2 CH1 input; note 1 dual swapped 1 0 0 2CH1 input − CH2 input CH2 input; note 2 stereo Europe 1 0 1 CH1 input + CH2 input ----------------------------------------------------------2 CH1 input – CH2 input ----------------------------------------------------------2 stereo Korea; note 3 Notes 1. CH1 input: audio signal from FM channel 1. 2. CH2 input: audio signal from FM channel 2. 3. For stereo Korea the dematrix applies 6 dB attenuation (see Table 7). 1999 Dec 20 41 MODE Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.9 TDA9875A FM CHANNEL 1 LEVEL ADJUST REGISTER This register is used to correct for standard and station-dependent differences of signal levels. Table 30 applies to sound carrier 1. Table 30 Subaddress 12 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 42 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER This register is used to correct for standard and station-dependent differences of signal levels. Table 31 applies to sound carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level. Table 31 Subaddress 13 MSB LSB GAIN SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 0 0 0 1 0 0 1 1 −13 0 0 0 1 0 0 1 0 −14 0 0 0 1 0 0 0 1 −15 0 0 0 1 0 0 0 0 mute Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 43 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.11 NICAM CONFIGURATION REGISTER The decision of whether auto-muting is permitted shall be taken by the controlling microcontroller based on information contained in the TDA9875A’s status registers. Thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with “NICAM 728 ETS Revised for Data Applications” or any other preference. The NICAM de-emphasis gain is 0 dB at 40 Hz. Table 32 Subaddress 14 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) DCXOPULL 1 Set to lower DCXO frequency during DCXO test mode. 0 Set to higher DCXO frequency during DCXO test mode. 6 DCXOTEST 1 DCXO test mode on (available only during FM mode); note 2 0 DCXO normal mode on 5 B5 0 Set logic to 0. 4 DOUTEN 1 Enables the output of the NICAM serial data stream from the DQPSK demodulator on pin NICAM and of the associated clock on pin PCLK 0 Both outputs will be 3-stated. 0 Set logic to 0. 1 The auto-mute function will switch the output sound from NICAM L to the ADC output select register. With the ADC output select register the wanted signal source, e.g. the mono input, can be pre-set (see Section 10.3.20). This is useful, if the AM sound NICAM L system is demodulated externally. 0 The auto-mute function will switch the output sound from NICAM L to the AM program on the internal first sound carrier. 3 2 1 0 (LSB) AMSEL NDEEM AMUTE 1 Switches the NICAM J17 de-emphasis off. 0 Switches the NICAM J17 de-emphasis on. 1 Automatic muting is disabled. This bit has only an effect when the second sound carrier is set to NICAM. 0 Enables the automatic switching between NICAM and the program on the first sound carrier (i.e. FM mono or AM), dependent on the NICAM bit error rate. Notes 1. The default setting at power-up is 0000 0000. 2. The DCXO test mode is intended for checking the DCXO control range with the actually used PCB layout and crystal type. During the normal operating mode, the DCXO test mode should not be used. 1999 Dec 20 44 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.12 NICAM LEVEL ADJUST REGISTER This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to both NICAM sound outputs. Table 33 Subaddress 15 (note 1) MSB LSB GAIN SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 0 0 0 1 0 0 1 1 −13 0 0 0 1 0 0 1 0 −14 0 0 0 1 0 0 0 1 −15 0 0 0 1 0 0 0 0 mute Note 1. The default setting at power-up is 000 00000. 1999 Dec 20 45 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.3.13 NICAM LOWER ERROR LIMIT REGISTER Table 35 Subaddress 17 (notes 1 and 2) When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is lower than the value contained in this register, the NICAM signal is selected (again) for reproduction (see Section 10.3.14). Table 34 Subaddress 16 (notes 1 and 2) BIT NAME VALUE 7 (MSB) B7 − 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 (LSB) B0 DESCRIPTION lower error limit value BIT NAME VALUE 7 (MSB) B7 − 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 (LSB) B0 DESCRIPTION upper error limit value Notes 1. The default setting at power-up is 0101 0000. 2. The upper bit error rate limit ≅ subaddress 17 × 1.74 × 10−5. Notes 1. The default setting at power-up is 0001 0100. 2. The lower bit error rate limit ≅ subaddress 16 × 1.74 × 10−5. 10.3.14 NICAM UPPER ERROR LIMIT REGISTER When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. FM mono or AM sound) or the external mono input (depending on bit AMSEL and ADC output selection) is selected for reproduction. The difference between upper and lower error limit constitutes a hysteresis to avoid frequent switching between NICAM and the program on the first sound carrier. 1999 Dec 20 TDA9875A 46 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.15 AUDIO MUTE CONTROL REGISTER When any of these bits are set to logic 1, the corresponding pair of output channels will be muted. A bit set to logic 0 allows normal signal output. There is a soft mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the volume control. This is switched on/off by bits MUTMAIN and MUTAUX. Table 36 Subaddress 18 (note 1) BIT NAME 7 (MSB) MUTI2S2 6 5 MUTI2S1 MUTDAC VALUE 1 DESCRIPTION mute I2S2 output I2S2 0 normal 1 mute I2S1 output 0 normal I2S1 output output 1 mute internal DAC 0 normal internal DAC mute line outputs 4 MUTLINE 1 0 normal line outputs 3 MUTSC2 1 mute SCART 2 outputs 0 normal SCART 2 outputs mute SCART 1 outputs 2 MUTSC1 1 0 normal SCART 1 outputs 1 MUTAUX 1 mute Auxiliary outputs 0 normal Auxiliary outputs 0 (LSB) MUTMAIN 1 mute Main outputs 0 normal Main outputs Note 1. The default setting at power-up is 1111 1111. 10.3.16 DAC OUTPUT SELECT REGISTER This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for signal selection. The DAC is used for signal output from digital sources at analog outputs. The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC; DACGAIN1 adds 3 dB and DACGAIN2 adds 6 dB of gain, respectively. The two combinations of FM and NICAM apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for external use, such as recording. 1999 Dec 20 47 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 37 Subaddress 19 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) DACGAIN2 − extra gain setting (see Table 38) 6 B6 − DAC output selection (see Table 39) 5 B5 4 B4 3 DACGAIN1 − extra gain setting (see Table 38) 2 B2 − signal source selection (see Table 40) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 38 Extra gain setting B7 B3 GAIN (dB) 0 0 0 0 1 3 1 0 6 1 1 9 Table 39 DAC output selection B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 40 Signal source selection SIGNAL SOURCE B2 B1 B0 LEFT RIGHT 0 0 0 FM left FM right 0 0 1 NICAM left NICAM right 0 1 0 I2S1 left I2S1 right 0 1 1 I2S2 left I2S2 right 1 0 0 ADC left ADC right 1 0 1 AVL left AVL right 1 1 0 FM mono NICAM M1 1 1 1 FM mono NICAM M2 1999 Dec 20 48 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.17 SCART 1 OUTPUT SELECT REGISTER This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode. Table 41 Subaddress 20 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 default value 6 SC1GAIN 1 Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. 0 the audio signal output will be unchanged (0 dB gain) 5 B5 − output channel selection (see Table 42) 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 43) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0001. Table 42 Output channel selection B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input Table 43 Signal source selection B2 B1 B0 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input 1999 Dec 20 49 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.18 SCART 2 OUTPUT SELECT REGISTER This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode. Table 44 Subaddress 21 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 6 SC2GAIN 1 Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. 0 the audio signal output will be output (0 dB gain) 5 B5 − output channel selection (see Table 45) 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 46) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 45 Output channel selection B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input Table 46 Signal source selection B2 B1 B0 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input 1999 Dec 20 50 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.19 LINE OUTPUT SELECT REGISTER By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form. This register is used to characterize the signal to be output at the line output and define the output channel selector mode. Table 47 Subaddress 22 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 set to logic 0 6 LINGAIN 1 activates the 3 dB gain stage at the line output buffers 0 audio signal will be output unchanged (0 dB gain) − output channel selection (see Table 48) 5 B5 4 B4 3 B3 0 set to logic 0 2 B2 0 set to logic 0 1 B1 0 set to logic 0 0 (LSB) LINSEL 1 A signal from an analog source is being processed in the Main channel for line output. Analog signal sources comprise SCART 1 input, SCART 2 input, external input and mono input, i.e. any input to the ADC. 0 A signal from a digital source is being processed in the Main channel for line output. Digital signal sources comprise FM, NICAM, I2S1 input and I2S2 input. Note 1. The default setting at power-up is 0000 0000. Table 48 Output channel selection B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input 1999 Dec 20 51 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.20 ADC OUTPUT SELECT REGISTER This register is used to define the signal source for the ADC. There is no output channel selector, because all digital signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided. Table 49 Subaddress 23 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 − signal source selection (see Table 50) 6 B6 5 B5 4 B4 − ADC level adjust (see Table 51) 3 B3 2 B2 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 50 Signal source selection B7 B6 B5 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1999 Dec 20 52 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 51 ADC level adjust (note 1) B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 1 1 1 1 1 1 1 0 +15 +14 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 +13 +12 +11 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 +10 +9 +8 +7 +6 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +5 +4 +3 +2 +1 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 1 1 0 0 1 0 0 1 0 1 −12 −13 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 −14 −15 mute Note 1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a full-scale level of −6 dB at the digital crossbar. 1999 Dec 20 53 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.21 MAIN CHANNEL SELECT REGISTER This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode of the digital matrix for signal selection. Table 52 Subaddress 24 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 default value 6 B6 − output channel selection (see Table 53) 5 B5 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 54) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 53 Output channel selection B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 54 Signal source selection B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 NICAM input 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input 1999 Dec 20 54 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.22 AUDIO EFFECTS REGISTER (MAIN) Switching the AVL off will reset the associated hardware to a defined state. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved by switching the AVL off and on again. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in Table 57. There is a gain of 3 dB in the left audio channel. Table 55 Subaddress 25 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 Default value. 6 B6 0 Default value. 5 SPATIAL1 − 4 SPATIAL0 These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the Main channel (see Table 56). This function should be activated only in accordance with the result of the sound mode identification. 3 PSEUDO1 − 2 PSEUDO0 These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel (see Table 57). This function should be activated only in accordance with the result of the sound mode identification. 1 AVL1 − 0 (LSB) AVL0 These bits set the mode of operation of the automatic volume level control function at the entrance to the Main (loudspeaker) channel (see Table 58). Note 1. The default setting at power-up is 0000 0000. Table 56 Spatial control setting B5 B4 SPATIAL SETTING (%) 0 0 off 0 1 30 1 0 40 1 1 52 Table 57 Pseudo control setting B3 B2 PSEUDO SETTING (Hz) 0 0 off 0 1 300 1 0 200 1 1 150 B1 B0 AVL MODE 0 0 off/reset 0 1 short decay 1 0 medium decay 1 1 long decay Table 58 AVL control mode 1999 Dec 20 55 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.23 VOLUME CONTROL REGISTERS (MAIN) These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. Table 59 Subaddresses 26 and 27 MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 1 0 0 0 +24 0 0 0 1 0 1 1 1 +23 0 0 0 1 0 1 1 0 +22 0 0 0 1 0 1 0 1 +21 0 0 0 1 0 1 0 0 +20 0 0 0 1 0 0 1 1 +19 0 0 0 1 0 0 1 0 +18 0 0 0 1 0 0 0 1 +17 0 0 0 1 0 0 0 0 +16 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −1 1 1 1 1 1 1 1 0 −2 1 1 1 1 1 1 0 1 −3 1 1 1 1 1 1 0 0 −4 1 1 1 1 1 0 1 1 −5 1 1 1 1 1 0 1 0 −6 1 1 1 1 1 0 0 1 −7 1 1 1 1 1 0 0 0 −8 1 1 1 1 0 1 1 1 −9 1999 Dec 20 56 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 1 0 1 1 0 −10 1 1 1 1 0 1 0 1 −11 1 1 1 1 0 1 0 0 −12 1 1 1 1 0 0 1 1 −13 1 1 1 1 0 0 1 0 −14 1 1 1 1 0 0 0 1 −15 1 1 1 1 0 0 0 0 −16 1 1 1 0 1 1 1 1 −17 1 1 1 0 1 1 1 0 −18 1 1 1 0 1 1 0 1 −19 1 1 1 0 1 1 0 0 −20 1 1 1 0 1 0 1 1 −21 1 1 1 0 1 0 1 0 −22 1 1 1 0 1 0 0 1 −23 1 1 1 0 1 0 0 0 −24 1 1 1 0 0 1 1 1 −25 1 1 1 0 0 1 1 0 −26 1 1 1 0 0 1 0 1 −27 1 1 1 0 0 1 0 0 −28 1 1 1 0 0 0 1 1 −29 1 1 1 0 0 0 1 0 −30 1 1 1 0 0 0 0 1 −31 1 1 1 0 0 0 0 0 −32 1 1 0 1 1 1 1 1 −33 1 1 0 1 1 1 1 0 −34 1 1 0 1 1 1 0 1 −35 1 1 0 1 1 1 0 0 −36 1 1 0 1 1 0 1 1 −37 1 1 0 1 1 0 1 0 −38 1 1 0 1 1 0 0 1 −39 1 1 0 1 1 0 0 0 −40 1 1 0 1 0 1 1 1 −41 1 1 0 1 0 1 1 0 −42 1 1 0 1 0 1 0 1 −43 1 1 0 1 0 1 0 0 −44 1 1 0 1 0 0 1 1 −45 1 1 0 1 0 0 1 0 −46 1 1 0 1 0 0 0 1 −47 1 1 0 1 0 0 0 0 −48 1999 Dec 20 57 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 0 0 1 1 1 1 −49 1 1 0 0 1 1 1 0 −50 1 1 0 0 1 1 0 1 −51 1 1 0 0 1 1 0 0 −52 1 1 0 0 1 0 1 1 −53 1 1 0 0 1 0 1 0 −54 1 1 0 0 1 0 0 1 −55 1 1 0 0 1 0 0 0 −56 1 1 0 0 0 1 1 1 −57 1 1 0 0 0 1 1 0 −58 1 1 0 0 0 1 0 1 −59 1 1 0 0 0 1 0 0 −60 1 1 0 0 0 0 1 1 −61 1 1 0 0 0 0 1 0 −62 1 1 0 0 0 0 0 1 −63 1 1 0 0 0 0 0 0 −64 1 0 1 1 1 1 1 1 −65 1 0 1 1 1 1 1 0 −66 1 0 1 1 1 1 0 1 −67 1 0 1 1 1 1 0 0 −68 1 0 1 1 1 0 1 1 −69 1 0 1 1 1 0 1 0 −70 1 0 1 1 1 0 0 1 −71 1 0 1 1 1 0 0 0 −72 1 0 1 1 0 1 1 1 −73 1 0 1 1 0 1 1 0 −74 1 0 1 1 0 1 0 1 −75 1 0 1 1 0 1 0 0 −76 1 0 1 1 0 0 1 1 −77 1 0 1 1 0 0 1 0 −78 1 0 1 1 0 0 0 1 −79 1 0 1 1 0 0 0 0 −80 1 0 1 0 1 1 1 1 −81 1 0 1 0 1 1 1 0 −82 1 0 1 0 1 1 0 1 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 1010 1100. 1999 Dec 20 58 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.24 CONTOUR CONTROL REGISTER (MAIN) This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so, of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to contour off. Table 60 Subaddress 28 MSB LSB CONTOUR GAIN (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 0 0 1 0 18 0 0 0 1 0 0 0 1 17 0 0 0 1 0 0 0 0 16 0 0 0 0 1 1 1 1 15 0 0 0 0 1 1 1 0 14 0 0 0 0 1 1 0 1 13 0 0 0 0 1 1 0 0 12 0 0 0 0 1 0 1 1 11 0 0 0 0 1 0 1 0 10 0 0 0 0 1 0 0 1 9 0 0 0 0 1 0 0 0 8 0 0 0 0 0 1 1 1 7 0 0 0 0 0 1 1 0 6 0 0 0 0 0 1 0 1 5 0 0 0 0 0 1 0 0 4 0 0 0 0 0 0 1 1 3 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 (note 1) Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 59 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.25 BASS CONTROL REGISTER (MAIN) This register is used to apply bass control to the left and right signal channels of the Main channel. Table 61 Subaddress 29 MSB LSB BASS SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 60 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.26 TREBLE CONTROL REGISTER (MAIN) This register is used to apply treble control to the left and right signal channels of the Main channel. Table 62 Subaddress 30 MSB LSB TREBLE SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 61 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.27 AUXILIARY CHANNEL SELECT REGISTER This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode of the digital matrix for signal selection. Table 63 Subaddress 31 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 default value 6 B6 − output channel selection (see Table 64) 5 B5 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 65) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 64 Output channel selection B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 65 Signal source selection B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 NICAM input 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input 1 0 1 AVL input 1999 Dec 20 62 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY) These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. Table 66 Subaddresses 32 and 33 MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 1 1 0 0 0 +24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 +4 +3 +2 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 +1 0 −1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 −2 −3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 −4 −5 −6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 −7 −8 −9 1 1 1 1 0 1 1 0 −10 1999 Dec 20 63 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 −11 −12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 −13 −14 −15 −16 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 −17 −18 −19 −20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 −21 −22 −23 −24 −25 −26 −27 −28 −29 −30 −31 −32 −33 −34 −35 −36 −37 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 −38 −39 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 0 −40 −41 −42 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 −43 −44 −45 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 −46 −47 −48 −49 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 −50 −51 1999 Dec 20 64 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A MSB LSB VOLUME SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 0 1 −52 −53 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 −54 −55 −56 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 −57 −58 −59 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 −60 −61 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 −62 −63 −64 −65 −66 −67 −68 −69 −70 −71 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 −72 −73 −74 −75 −76 −77 −78 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 1 −79 −80 −81 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 −82 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 1010 1100. 1999 Dec 20 65 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.29 BASS CONTROL REGISTER (AUXILIARY) This register is used to apply bass control to the left and right signal channels of the Auxiliary channel. Table 67 Subaddress 34 MSB LSB BASS SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 (note 1) 0 0 0 1 1 1 1 1 −1 0 0 0 1 1 1 1 0 −2 0 0 0 1 1 1 0 1 −3 0 0 0 1 1 1 0 0 −4 0 0 0 1 1 0 1 1 −5 0 0 0 1 1 0 1 0 −6 0 0 0 1 1 0 0 1 −7 0 0 0 1 1 0 0 0 −8 0 0 0 1 0 1 1 1 −9 0 0 0 1 0 1 1 0 −10 0 0 0 1 0 1 0 1 −11 0 0 0 1 0 1 0 0 −12 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 66 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.30 TREBLE CONTROL REGISTER (AUXILIARY) This register is used to apply treble control to the left and right signal channels of the Auxiliary channel. Table 68 Subaddress 35 MSB LSB TREBLE SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 1) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 67 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER Table 69 Subaddress 36 (note 1) BIT NAME VALUE 7 (MSB) B7 0 default value 6 B6 0 default value 5 B5 0 default value 4 SYSCL1 − system clock frequency selection (see Table 70) 3 SYSCL0 2 SYSOUT 1 enables the output of a system (or master) clock signal at pin SYSCLK 0 the output will be off, thereby improving the EMC performance 1 I2SFORM 1 an MSB-aligned (MSB-first) serial output format is selected, i.e. a level change at pin WS indicates the beginning of a new audio sample 0 the standard I2S-bus output format is selected 1 enables the I2S-bus outputs (both serial data outputs plus serial bit clock and word select) in a format determined by bit I2SFORM; the TDA9875A is then an I2S-bus master 0 the outputs mentioned will be 3-stated, thereby improving the EMC performance 0 (LSB) I2SOUT DESCRIPTION Note 1. The default setting at power-up is 0000 0000. Table 70 System clock frequency selection B4 B3 SYSCLK OUTPUT FREQUENCY (MHz) 0 0 256fs 8.192 0 1 384fs 12.288 1 0 512fs 16.384(1) 1 1 768fs 24.576 Note 1. With 16.384 MHz the duty cycle is 33%. 1999 Dec 20 68 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.32 I2S1 OUTPUT SELECT REGISTER This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal selection. Table 71 Subaddress 37 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 default value 6 B6 − output selection (see Table 72) 5 B5 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 73) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 72 Output selection B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 73 Signal source selection (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 NICAM output 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. 1999 Dec 20 69 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically. Table 74 Subaddress 38 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 70 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically. Table 75 Subaddress 39 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 71 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.35 I2S2 OUTPUT SELECT REGISTER This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal selection. Table 76 Subaddress 40 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 0 default value 6 B6 − output selection (see Table 77) 5 B5 4 B4 3 B3 0 default value 2 B2 − signal source selection (see Table 78) 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 77 Output selection B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 0 0 L+R -------------2 L+R -------------2 Table 78 Signal source selection (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 NICAM output 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. 1999 Dec 20 72 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically. Table 79 Subaddress 41 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 73 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically. Table 80 Subaddress 42 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1. The default setting at power-up is 0000 0000. 1999 Dec 20 74 GAIN SETTING (dB) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 1) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.38 BEEPER FREQUENCY CONTROL REGISTER This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main and Auxiliary channel output DAC. Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than the 390 Hz beep. Table 81 Subaddress 43 (note 1) MSB LSB GENERATED FREQUENCY (Hz) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 1 1 1 25000 0 0 0 0 0 1 1 0 7040 0 0 0 0 0 1 0 1 3580 0 0 0 0 0 1 0 0 1770 0 0 0 0 0 0 1 1 1270 0 0 0 0 0 0 1 0 900 0 0 0 0 0 0 0 1 640 0 0 0 0 0 0 0 0 390 Note 1. The default setting at power-up is 0000 0000. 10.3.39 BEEPER VOLUME CONTROL REGISTER This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and Auxiliary channel output DACs. The beeper volume is independent of any other volume setting. The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × fs domain. The beeper volume should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload. 1999 Dec 20 75 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 82 Subaddress 44 MSB LSB GAIN SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 −3 0 0 1 1 1 1 1 0 −6 0 0 1 1 1 1 0 1 −9 0 0 1 1 1 1 0 0 −12 0 0 1 1 1 0 1 1 −15 0 0 1 1 1 0 1 0 −18 0 0 1 1 1 0 0 1 −21 0 0 1 1 1 0 0 0 −24 0 0 1 1 0 1 1 1 −27 0 0 1 1 0 1 1 0 −30 0 0 1 1 0 1 0 1 −33 0 0 1 1 0 1 0 0 −36 0 0 1 1 0 0 1 1 −39 0 0 1 1 0 0 1 0 −42 0 0 1 1 0 0 0 1 −45 0 0 1 1 0 0 0 0 −48 0 0 1 0 1 1 1 1 −51 0 0 1 0 1 1 1 0 −54 0 0 1 0 1 1 0 1 −57 0 0 1 0 1 1 0 0 −60 0 0 1 0 1 0 1 1 −63 0 0 1 0 1 0 1 0 −66 0 0 1 0 1 0 0 1 −69 0 0 1 0 1 0 0 0 −72 0 0 1 0 0 1 1 1 −75 0 0 1 0 0 1 1 0 −78 0 0 1 0 0 1 0 1 −81 0 0 1 0 0 1 0 0 −84 0 0 1 0 0 0 1 1 −87 0 0 1 0 0 0 1 0 −90 0 0 1 0 0 0 0 1 −93 0 0 1 0 0 0 0 0 mute (note 1) Note 1. The default setting at power-up is 0010 0000. 1999 Dec 20 76 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 10.3.40 BASS BOOST CONTROL REGISTER This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function must be used with care in order to avoid clipping distortion at high volume settings. More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then has full control over this second-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, Q factors and boost/cut settings. Table 83 Subaddress 45 (note 1) BIT NAME VALUE DESCRIPTION 7 (MSB) B7 − gain setting of right channel (see Table 84) 6 B6 5 B5 4 B4 3 B3 − gain setting of left channel (see Table 85) 2 B2 1 B1 0 (LSB) B0 Note 1. The default setting at power-up is 0000 0000. Table 84 Gain setting right channel B7 B6 B5 B4 GAIN SETTING (dB) CORNER FREQUENCY (Hz) 1 0 1 0 20 350 1 0 0 1 18 350 1 0 0 0 16 350 0 1 1 1 14 350 0 1 1 0 12 350 0 1 0 1 10 350 0 1 0 0 8 350 0 0 1 1 6 350 0 0 1 0 4 350 0 0 0 1 2 350 0 0 0 0 0 350 1999 Dec 20 77 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 85 Gain setting left channel B3 B2 B1 B0 GAIN SETTING (dB) CORNER FREQUENCY (Hz) 1 0 1 0 20 350 1 0 0 1 18 350 1 0 0 0 16 350 0 1 1 1 14 350 0 1 1 0 12 350 0 1 0 1 10 350 0 1 0 0 8 350 0 0 1 1 6 350 0 0 1 0 4 350 0 0 0 1 2 350 0 0 0 0 0 350 1999 Dec 20 78 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4 TDA9875A Slave transmitter mode As a slave transmitter, the TDA9875A provides 13 registers with status information and data, a part of which is for Philips internal purposes only. These registers can be accessed by means of subaddresses. Table 86 General format for reading data from the TDA9875A S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P Table 87 Explanation of Tables 86 and 88 BIT S FUNCTION START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge (by the slave) SUBADDRESS address of register to read from Sr repeated START condition 1 data direction bit (read from device) DATA data byte read from register NAm not acknowledge (by the master) Am acknowledge (by the master) P STOP condition Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9875A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 88 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE 1 ACK ADDRESS DATA BYTE Am(1) DATA NAm P Note 1. n data bytes with auto-increment of subaddresses. Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master). The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation. 1999 Dec 20 79 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 89 Overview of the slave transmitter registers (note 1) DATA SUBADDRESS (DECIMAL) MSB FUNCTION LSB 0 s s s s s s s s device status (power-on, identification, etc.) 1 s s s s s s s s NICAM status 2 e e e e e e e e NICAM error count 3 d d d d d d d d additional data (LSB) 4 c c X c c d d d additional data (MSB) 5 l l l l l l l l level read-out (MSB) 6 l l l l l l l l level read-out (LSB) 7 X X X c c c c c SIF level 251 a a a a a a a a test register 3; note 2 252 a a a a a a a a test register 2; note 2 253 a a a a a a a a test register 1; note 2 254 d d d d d d d d device identification code 255 s s s s s s s s software identification code Notes 1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions. 2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. The following sub-sections provide a detailed description of the slave transmitter registers. 1999 Dec 20 80 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.1 TDA9875A DEVICE STATUS REGISTER Table 90 Subaddress 0 BIT NAME VALUE 7 (MSB) P2IN − This bit reflects the status of the corresponding general purpose port of pin P2 (see Section 10.3.2). 6 P1IN − This bit reflects the status of the corresponding general purpose port of pin P1 (see Section 10.3.2). 5 RSSF 1 Reserve sound switching flag: this bit is a copy of the C4 bit in the NICAM status register. It indicates that the FM (or AM for standard L) sound matches the digital transmission and auto-muting should be enabled. 0 Auto-muting should be disabled, as analog and digital sound are different. 4 AMSTAT 1 Auto-mute status: it indicates that the auto-muting function has switched from NICAM to the program of the first sound carrier (i.e. FM mono or AM in the NICAM L system) or to the ADC (depending on bit AMSEL). 0 Auto-muting function has not switched. 3 VDSP DESCRIPTION 1 Indicates that digital transmission is a sound source (NICAM). 0 The transmission is either data or currently undefined format (NICAM). 2 IDDUA − This bit is logic 1 if an FM dual-language signal has been identified. When neither IDSTE nor IDDUA are set, the received signal has to be assumed to be FM mono. 1 IDSTE − This bit is logic 1 if an FM stereo signal has been identified. 0 (LSB) POR − Power fail bit: the power supply for the digital part of the device, VDDD2, has temporarily been lower than the specified lower limit. If this is detected an initialization of the TDA9875A has to be carried out to ensure a reliable operation. 1999 Dec 20 81 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.2 TDA9875A NICAM STATUS REGISTER The TDA9875A does not support the Extended Control Modes. Therefore, the program of the first sound carrier (i.e. FM mono or AM) is selected for reproduction in case bit C3 is set to logic 1, independent of bit AMUTE in the NICAM configuration register being set or not. When a NICAM transmitter is switched off, the device will lose synchronization. In this situation the program of the first sound carrier is selected for reproduction, independent of bit AMUTE being set or not. Table 91 Subaddress 1 BIT NAME VALUE 7 (MSB) C4 − 6 C3 5 C2 4 C1 3 OSB 2 CFC 1 S/MB 0 (LSB) 10.4.3 D/SB DESCRIPTION application control bits (C1 to C4 in the NICAM transmission) 1 indication that the device has both frame and C0 (16 frame) synchronization 0 the audio output from the NICAM part should be digital silence 1 indication of a configuration change at the 16 frame (C0) boundary 0 no configuration change 1 indication of NICAM stereo mode 0 no NICAM stereo mode 1 indication NICAM dual mono mode 0 no NICAM dual mono mode NICAN ERROR COUNT REGISTER Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms. Table 92 Subaddress 2 BIT NAME VALUE 7 (MSB) B7 − 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 (LSB) B0 1999 Dec 20 DESCRIPTION number of errors 82 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.4 TDA9875A ADDITIONAL DATA REGISTERS These two bytes provide information on the additional data bits. Table 93 Subaddress 3 BIT NAME VALUE 7 (MSB) AD7 − 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 (LSB) AD0 DESCRIPTION comprise the additional data word Table 94 Subaddress 4 BIT NAME VALUE DESCRIPTION 7 (MSB) OVW 1 new additional data bits are written to the IC without the previous bits being read 0 no bits are written 1 new additional data is written into the IC 0 this bit is set to logic 0 when the additional data bits are read 6 SAD 5 X − don’t care 4 CI1 − 3 CI2 these are CI bits decoded by majority logic from the parity checks of the last ten samples in a frame 2 AD10 − comprise the additional data word 1 AD9 0 (LSB) AD8 1999 Dec 20 83 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.5 TDA9875A Table 96 Subaddress 7 LEVEL READ-OUT REGISTERS These two bytes constitute a word that provides data from a location that has been specified with the monitor select register. The most significant byte of the data is stored at subaddress 5. BIT NAME VALUE 7 (MSB) B7 X bit not assigned 6 B6 X bit not assigned 5 B5 X bit not assigned 4 B4 − 3 B3 indication of SIF input level 2 B2 1 B1 0 (LSB) B0 If peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes. Table 95 Subaddresses 5 and 6 SUBADDRESS 5 BIT DESCRIPTION 10.4.7 7 (MSB) most significant bit or sign bit 6 4 3 Table 97 Subaddress 251 2 MSB 1 B7 B6 B5 B4 B3 B2 B1 B0 7 (MSB) 0 1 1 1 1 1 1 1 10.4.8 5 TEST REGISTER 2 This register contains, as a binary number, the highest subaddress used for slave receiver registers. 4 3 2 Table 98 Subaddress 252 1 MSB 0 (LSB) least significant bit SIF LEVEL REGISTER When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number corresponds to the AGC gain register setting (see Section 10.3.1). When the SIF AGC is off, this register returns the contents of the AGC gain register. 1999 Dec 20 LSB 0 (LSB) 6 10.4.6 TEST REGISTER 3 This register contains, as a binary number, the highest memory address used for the Coefficient RAM (CRAM, expert mode). 5 6 DESCRIPTION 84 LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 1 0 1 1 0 1 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 10.4.9 As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 104). The most significant bit is transferred first. TEST REGISTER 1 This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. The general format described in Table 104 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. Table 99 Subaddress 253 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 1 1 1 Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they are arranged as shown in Table 105. 10.4.10 DEVICE IDENTIFICATION CODE There will be several devices in the digital TV sound processor family. This byte is used to identify the individual family members. With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing don’t care data. Table 100 Subaddress 254 MSB As the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. The receive buffer is designed to store up to 8 coefficients in addition to the CRAM address. Each byte that fits into the buffer is acknowledged with ACK (acknowledge). If an attempt is made to write more coefficients than the buffer can store, the device acknowledges with NACK (not acknowledge) and any further coefficients are ignored. Coefficients that are already in the receive buffer remain intact. LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 1 0 10.4.11 SOFTWARE IDENTIFICATION CODE It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases. An expert mode transfer ends when the I2C-bus STOP condition or a repeated START condition has been detected. Only those coefficients that have been received during the last transmission will then be copied from the buffer to the CRAM. Table 101 Subaddress 255 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 1 0 10.5 TDA9875A To make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. Expert mode In addition to the slave receiver and slave transmitter modes previously described, there is a special ‘expert’ mode that gives direct write access to the internal CRAM of the DSP. There is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used CRAM address. The user of this expert mode must be fully acquainted with the relevant procedures. In this mode, transferred data contain 12-bit coefficients. As these coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the DSP. More information concerning the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. This mode must be used with great care. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses. 1999 Dec 20 85 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A Table 102 General format for entering the expert mode and writing coefficients into the TDA9875A S SLAVE ADDRESS 0 ACK 10000000 ACK CRAM ADDRESS ACK DATA ACK DATA ACK P Table 103 Explanation of Table 102 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge 10000000 pattern to enter the expert mode CRAM ADDRESS start address of coefficient RAM to write to DATA data byte containing part of a coefficient P STOP condition Table 104 General format (notes 1, 2 and 3) BYTE DATA DESCRIPTION 1 data byte a a a a a a a a 2 MST of 1st coefficient 2 data byte a a a a X X X X 1 LST of 1st coefficient Notes 1. X = don’t care. 2. MST = most significant third. 3. LST = least significant third. Table 105 Transfer of two coefficients BYTE DATA DESCRIPTION 1 data byte a a a a a a a a 2 MST of 1st coefficient 2 data byte a a a a b b b b 1 LST of 1st coefficient + 1 MST of 2nd coefficient 3 data byte b b b b b b b b 2 LST of 2nd coefficient 1999 Dec 20 86 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) Apart from just feeding a digital audio device, such as a DAC or an AES/EBU transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature DSP such as the SAA7710 and then back to the serial inputs. In all of these configurations, the SCK and WS clocks will be generated by the TDA9875A, which then is the I2S-bus master. 11 I2S-BUS DESCRIPTION The feature interface of the TDA9875A contains two serial audio inputs and outputs and associated clock signals. It can be used to supply, for example, audio signals from received TV programs to a digital audio output device (AES/EBU format), or import serial audio signals from other sources for reproduction through the TV set’s loudspeaker and/or headphone channels. Apart from such simple data input or output, it is also possible to run audio signals through an external DSP, which performs some additional functions, such as room simulation, Dolby Surround Pro Logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the TDA9875A. The serial data inputs, SDI1 and SDI2, are active at all times, independent of the serial data outputs being on or off. When the serial data outputs are off (either after power-up or via the appropriate I2C-bus command) serial data and clocks WS and SCK from a separate digital audio source can be fed into the TDA9875A, be processed and output in accordance with internal selector positions, provided that the following criteria are met: Two serial audio formats are supported at the feature interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.9. • 32 kHz audio sample frequency • 32 clock bits per sample In both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (SDI for input, SDO for output) when the Word Select line (WS) is LOW. Data is written at the trailing edge of SCK and read at the leading edge of SCK. The most significant bit is sent first. • External timing and data synchronized to TDA9875A. In such cases, the external source is the I2S-bus master and the TDA9875A is the I2S-bus slave. To support synchronization of external devices or as a master clock for them, a system clock output, SYSCLK, is available from the TDA9875A. At power-up it is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz. At power-up, the outputs of the feature interface are 3-stated to reduce EMC and allow for combinations with other ICs. If output is desired, it has to be activated by means of an I2C-bus command. When the output is enabled, the serial audio data can be taken from pins SDO1 and SDO2. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. The word select output is clocked with the audio sample frequency at 32 kHz. The serial clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. Depending again on the signal source, the number of significant bits on the serial data outputs, SDO1 and SDO2, is between 14 and 18. 1999 Dec 20 TDA9875A 87 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK112 one sample a. I2S-bus format. handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK113 one sample b. MSB-aligned format. Fig.9 Serial audio interface formats. 1999 Dec 20 88 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 12 APPLICATION INFORMATION handbook, full pagewidth PCLK 1 (57) (56) 64 VDDD2 R19 NICAM ADDR1 SCL SDA VSSA1 VDEC1 C1 4.7 µF Iref R1 2 (58) (55) 63 3 (59) (54) 62 4 (60) (53) 61 5 (61) (52) 60 6 (62) (51) 59 7 (63) (50) 58 8 (64) (49) 57 10 kΩ P1 C2 SIF2 SIFSAT 47 pF C3 Vref1 9 (1) (48) 56 10 (2) (47) 55 11 (3) (46) 54 12 (4) (45) 53 13 (5) (44) 52 100 nF C4 SIF1 SIFTV 47 pF ADDR2 VSSD1 +5 V R2 VDDD1 1.5 Ω C5 47 µF C6 1 µF CRESET VSSD4 XTALI 24.576 MHz (43) 51 15 (7) 16 (8) 17 (9) (42) 50 TDA9875A (TDA9875AH) (41) 49 (40) 48 18 (10) (39) 47 XTALO 19 (11) (38) 46 P2 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 (12) (37) 45 21 (13) (36) 44 22 (14) (35) 43 23 (15) (34) 42 24 (16) (33) 41 25 (17) (32) 40 26 (18) (31) 39 27 (19) (30) 38 28 (20) (29) 37 MONOIN 470 nF TEST2 C8 EXTIR C9 EXTIL (28) 36 30 (22) (27) 35 31 (23) (26) 34 32 (24) (25) 33 2.2 µF C32 MOL C31 10 nF C29 10 nF 2.2 µF C28 47 µF C26 10 nF 2.2 µF C24 10 nF MOR VDDA AUXOL AUXOR VSSA3 Vref3 C25 2.2 µF 10 nF C22 C21 10 nF 47 µF SCOL2 C20 C19 SCOR2 2.2 µF 2.2 µF VSSA4 VSSD2 C18 SCOL1 C17 SCOR1 2.2 µF 2.2 µF C16 Vref2 47 µF i.c. i.c. VSSA2 i.c. i.c. Vref(n) C15 47 µF R7 270 Ω VDEC2 SCIR2 VSSD3 R5 R4 Fig.10 Schematic for measurements. 330 nF C12 15 kΩ SCIL1 SCIR1 R3 C14 4.7 µF C13 R6 SCIL2 The pin numbers given in parenthesis refer to the TDA9875AH version. 89 R8 2.2 Ω C27 PCAPR MHB601 1999 Dec 20 C30 2.2 µF C23 PCAPL 330 nF C11 15 kΩ 330 nF C10 15 kΩ 470 nF 2.2 µF C33 LOL Vref(p) 29 (21) C34 LOR 15 kΩ C7 470 nF 14 (6) +5 V 47 µF 1.5 Ω C35 330 nF +5 V Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) +5 V handbook, full pagewidth POWER PCLK 47 µF C1 NICAM ADDR1 L1 100 Ω R2 SCL L2 SDA 100 Ω VSSA1 VDEC1 C2 470 nF Iref R3 R4 2.2 kΩ P1 SIF2 SIFSAT 47 pF C4 (55) 63 3 (59) (54) 62 4 (60) (53) 61 5 (61) (52) 60 6 (62) (51) 59 7 (63) (50) 58 8 (64) (49) 57 9 (1) (48) 56 10 (2) (47) 55 Vref1 11 (3) (46) 54 SIF1 SIFTV 12 (4) (45) 53 13 (5) (44) 52 47 pF ADDR2 VSSD1 +5 V L5 R5 1Ω C6 470 nF VDDD1 C7 1 µF CRESET VSSD4 XTALI 24.576 MHz R6 (43) 51 15 (7) (42) 50 16 (8) 17 (9) TDA9875A (TDA9875AH) (41) 49 (40) 48 (39) 47 XTALO 19 (11) (38) 46 SYSCLK SCK WS SDO2 SDO1 SDI2 SDI1 TEST1 20 (12) (37) 45 21 (13) (36) 44 22 (14) (35) 43 23 (15) (34) 42 24 (16) (33) 41 25 (17) (32) 40 26 (18) (31) 39 C38 470 pF 2.2 µF C37 C36 10 nF C34 10 nF 2.2 µF C32 470 nF C31 10 nF 2.2 µF C29 C30 10 nF MOL MONOIN TEST2 VDDA 27 (19) (30) 38 28 (20) (29) 37 29 (21) (28) 36 30 (22) (27) 35 31 (23) (26) 34 L8 EXTIL C33 AUXOL AUXOR VSSA3 (25) 33 32 (24) R12 2.2 Ω 2.2 µF C27 PCAPR 10 nF C26 Vref3 47 µF SCOL2 C25 C24 470 pF C22 470 pF 2.2 µF C20 470 pF C18 470 pF 2.2 µF C17 SCOR2 VSSA4 C23 2.2 µF VSSD2 C21 SCOL1 SCOR1 Vref2 C19 2.2 µF 47 µF i.c. i.c. VSSA2 i.c. i.c. Vref(n) C16 47 µF R11 270 Ω VDEC2 SCIR2 VSSD3 Fig.11 Schematic for application. 330 nF C13 R8 330 nF C12 15 kΩ 330 nF C11 15 kΩ L1 to L9 are ferrite beads. The pin numbers given in parenthesis refer to the TDA9875AH version. R9 15 kΩ SCIL1 SCIR1 R7 C15 470 nF C14 SCIL2 R10 MHB602 90 2.2 µF C28 PCAPL L7 EXTIR C35 MOR 470 nF 1999 Dec 20 470 pF C39 +5 V 2.2 µF C40 LOL Vref(p) L6 470 nF C10 R13 470 1 Ω C41 nF LOR 15 kΩ 470 nF C9 14 (6) 18 (10) P2 2.2 kΩ C8 L9 VDDD2 10 nF 100 nF L4 C5 2 (58) 10 kΩ L3 C3 (56) 64 C42 0V R1 1 (57) TDA9875A 330 nF +5 V Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 13 PACKAGE OUTLINES seating plane SDIP64: plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1 ME D A2 A L A1 c e Z b1 (e 1) w M MH b 33 64 pin 1 index E 1 32 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.84 0.51 4.57 1.3 0.8 0.53 0.40 0.32 0.23 58.67 57.70 17.2 16.9 1.778 19.05 3.2 2.8 19.61 19.05 20.96 19.71 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT274-1 1999 Dec 20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MS-021 91 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 θ wM Lp bp pin 1 index L 17 64 detail X 16 1 w M bp e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 3.00 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 14.1 13.9 0.8 HD HE L 17.45 17.45 1.60 16.95 16.95 Lp v w y 1.03 0.73 0.16 0.16 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 1999 Dec 20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-08-04 99-12-27 MS-022 92 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 14 SOLDERING 14.1 Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). 14.3.2 14.2.1 To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE • For packages with leads on two sides and a pitch (e): The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.2.2 The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. 14.3 14.3.1 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Surface mount packages REFLOW SOLDERING 14.3.3 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. MANUAL SOLDERING Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 1999 Dec 20 WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 TDA9875A When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 93 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) 14.4 TDA9875A Suitability of IC packages for wave, reflow and dipping soldering methods SOLDERING METHOD MOUNTING PACKAGE WAVE suitable(2) Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount REFLOW(1) DIPPING − suitable BGA, SQFP not suitable suitable − HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(3) suitable − PLCC(4), SO, SOJ suitable suitable − suitable − suitable − recommended(4)(5) LQFP, QFP, TQFP not SSOP, TSSOP, VSO not recommended(6) Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 Dec 20 94 Philips Semiconductors Product specification Digital TV Sound Processor (DTVSP) TDA9875A 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Dec 20 95 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/02/pp96 Date of release: 1999 Dec 20 Document order number: 9397 750 06065