INFINEON HYS64D64020GDL

D a t a S h e e t , R e v . 1 . 1 , M ay . 2 00 4
HYS64D64020[H/G]DL–5–B
HYS64D64020[H/G]DL–6–B
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
D a t a S h e e t , R e v . 1 . 1 , M ay . 2 00 4
HYS64D64020[H/G]DL–5–B
HYS64D64020[H/G]DL–6–B
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
HYS64D64020[H/G]DL–5–B, HYS64D64020[H/G]DL–6–B
Revision History:
Rev. 1.1
2004-05
Previous Version:
Rev. 1.0
2003-03
Page
Subjects (major changes since last revision)
17
Updated IDD values
7
added Black TSOP DDR333 and DDR400
8
editorial change
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Template: mp_a4_v2.0_2003-06-06.fm
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Sheet
5
14
14
16
18
Rev. 1.0, 2004-05
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HYS64D64020[H/G]DL–5–B
HYS64D64020[H/G]DL–6–B
Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
Two ranks 64M × 64 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
Single +2.5 V (± 0.2 V) power supply and +2.6 V (± 0.1 V) for DDR400
Built with 512 Mbit DDR SDRAMs organised as ×16 in P–TSOPII–66 packages
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
Jedec standard form factor: 67.60 mm × 31.75 mm × 3.80 mm
Jedec standard reference layout Raw Cards A
DDR400 speed grade supported
Gold plated contacts
Table 1
Performance
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
DDR400B
DDR333B
—
Module
PC3200–3033
PC2700–2533
—
200
166
MHz
166
166
MHz
133
133
MHz
max. Clock
Frequency
@CL3
@CL2.5
@CL2
1.2
fCK3
fCK2.5
fCK2
Description
The HYS64D64020[H/G]DL–5–B and HYS64D64020[H/G]DL–6–B are industry standard 200-Pin Small Outline
Dual-In-Line Memory Modules (SO-DIMMs) organized as 64M ×64. The memory array is designed with Double
Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board.
The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Overview
Table 2
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
PC32100S–3033–1–A1
two ranks 512MB SO-DIMM
512 MB (×16)
PC2700S–2533–0–A1
two ranks 512MB SO-DIMM
512 MB(×16)
PC32100S–3033–1–A1
two ranks 512MB SO-DIMM
512 MB (×16)
PC2700S–2533-0–A1
two ranks 512MB SO-DIMM
512 MB(×16)
PC3200 (CL=3.0)
HYS64D64020GDL–5–B
PC2700 (CL=2.5)
HYS64D64020GDL–6–B
PC3200 (CL=3.0)
HYS64D64020HDL–5–B
PC2700 (CL=2.5)
HYS64D64020HDL–6–B
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D64020[H/G]DL–5–B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 3
The pin configuration of the Unbuffered Small Outline
DDR SDRAM DIMM is listed by function in Table 3
(184 pins). The abbreviations used in columns Pin and
Buffer Type are explained in Table 4 and Table 5
respectively. The pin numbering is depicted in
Figure 1.
Table 3
Pin#
Pin Configuration of SO-DIMM
Name
Pin
Buffer Function
Type Type
Clock Signals
35
CK0
I
SSTL
Clock Signal
160
CK1
I
SSTL
Clock Signal
89
CK2
I
SSTL
Clock Signal
NC
NC
–
Note: ECC
module
type
Note: non-ECC
module
type
37
CK0
I
SSTL
Complement Clock
158
CK1
I
SSTL
Complement Clock
91
CK2
I
SSTL
Complement Clock
Note: ECC
module
type
type
NC
NC
–
Note: non-ECC
module
96
CKE0
I
SSTL
Clock Enable Rank 0
95
CKE1
I
SSTL
Clock Enable Rank 1
Pin#
Name
Pin
Buffer Function
Type Type
112
A0
I
SSTL
111
A1
I
SSTL
110
A2
I
SSTL
109
A3
I
SSTL
108
A4
I
SSTL
107
A5
I
SSTL
106
A6
I
SSTL
105
A7
I
SSTL
102
A8
I
SSTL
101
A9
I
SSTL
115
A10
I
SSTL
AP
I
SSTL
100
A11
I
SSTL
99
A12
I
SSTL
NC
–
123
Address Signal 12
NC
NC
–
Note: 128 Mbit based
module
A13
I
SSTL
Address Signal 13
Note: 1 Gbit
module
NC
based
NC
–
Note: Module based
on 512 Mbit or
smaller dies
Data Bus 63:0
Note: 1-rank module
Data Signals
Control Signals
121
S0
I
SSTL
Chip Select Rank 0
5
DQ0
I/O
SSTL
122
S1
I
SSTL
Chip Select Rank 1
7
DQ1
I/O
SSTL
Note: 2-ranks module
13
DQ2
I/O
SSTL
NC
NC
–
Note: 1-rank module
17
DQ3
I/O
SSTL
118
RAS
I
SSTL
Row Address
Strobe
6
DQ4
I/O
SSTL
8
DQ5
I/O
SSTL
120
CAS
I
SSTL
Column Address
Strobe
14
DQ6
I/O
SSTL
119
WE
I
SSTL
Write Enable
18
DQ7
I/O
SSTL
19
DQ8
I/O
SSTL
Bank Address Bus
1:0
23
DQ9
I/O
SSTL
29
DQ10
I/O
SSTL
31
DQ11
I/O
SSTL
20
DQ12
I/O
SSTL
24
DQ13
I/O
SSTL
Address Signals
117
BA0
I
SSTL
116
BA1
I
SSTL
Data Sheet
Address Bus 11:0
Note: Module based
on 256 Mbit or
larger dies
Note: 2-rank module
NC
Pin Configuration of SO-DIMM (cont’d)
8
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
Table 3
Table 3
Pin Configuration of SO-DIMM (cont’d)
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Buffer Function
Type Type
Pin#
Name
Pin
Buffer Function
Type Type
30
DQ14
I/O
SSTL
172
DQ54
I/O
SSTL
32
DQ15
I/O
SSTL
176
DQ55
I/O
SSTL
41
DQ16
I/O
SSTL
177
DQ56
I/O
SSTL
43
DQ17
I/O
SSTL
181
DQ57
I/O
SSTL
49
DQ18
I/O
SSTL
187
DQ58
I/O
SSTL
53
DQ19
I/O
SSTL
189
DQ59
I/O
SSTL
42
DQ20
I/O
SSTL
178
DQ60
I/O
SSTL
44
DQ21
I/O
SSTL
182
DQ61
I/O
SSTL
50
DQ22
I/O
SSTL
188
DQ62
I/O
SSTL
54
DQ23
I/O
SSTL
190
DQ63
I/O
SSTL
55
DQ24
I/O
SSTL
71
CB0
I/O
SSTL
59
DQ25
I/O
SSTL
65
DQ26
I/O
SSTL
67
DQ27
I/O
SSTL
56
DQ28
I/O
SSTL
60
DQ29
I/O
SSTL
66
DQ30
I/O
SSTL
68
DQ31
I/O
SSTL
127
DQ32
I/O
SSTL
129
DQ33
I/O
SSTL
135
DQ34
I/O
SSTL
139
DQ35
I/O
SSTL
128
DQ36
I/O
SSTL
130
DQ37
I/O
SSTL
136
DQ38
I/O
SSTL
140
DQ39
I/O
SSTL
141
DQ40
I/O
SSTL
145
DQ41
I/O
SSTL
151
DQ42
I/O
SSTL
153
DQ43
I/O
SSTL
142
DQ44
I/O
SSTL
146
DQ45
I/O
SSTL
152
DQ46
I/O
SSTL
154
DQ47
I/O
SSTL
163
DQ48
I/O
SSTL
165
DQ49
I/O
SSTL
171
DQ50
I/O
SSTL
175
DQ51
I/O
SSTL
164
DQ52
I/O
SSTL
166
DQ53
I/O
SSTL
Data Sheet
Data Bus 63:0
Data Bus 63:0
Check Bit 0
Note: ECC
module
73
NC
NC
–
Note: Non-ECC
module
CB1
I/O
SSTL
Check Bit 1
Note: ECC
module
79
NC
NC
–
Note: Non-ECC
module
CB2
I/O
SSTL
Check Bit 2
Note: ECC
module
83
NC
NC
–
Note: Non-ECC
module
CB3
I/O
SSTL
Check Bit 3
Note: ECC
module
72
NC
NC
–
Note: Non-ECC
module
CB4
I/O
SSTL
Check Bit 4
Note: ECC
module
74
NC
NC
–
Note: Non-ECC
module
CB5
I/O
SSTL
Check Bit 5
Note: ECC
module
NC
9
NC
–
type
type
type
type
type
type
Note: Non-ECC
module
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of SO-DIMM (cont’d)
Table 3
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Buffer Function
Type Type
Pin#
80
CB6
I/O
Power Supplies
SSTL
Check Bit 6
Note: ECC
module
84
NC
NC
–
Note: Non-ECC
module
CB7
I/O
SSTL
Check Bit 7
Note: ECC
module
type
type
NC
NC
–
Note: Non-ECC
module
11
DQS0
I/O
SSTL
Data Strobes 7:0
25
DQS1
I/O
SSTL
47
DQS2
I/O
SSTL
61
DQS3
I/O
SSTL
Note: See
block
diagram
for
corresponding
DQ signals
133
DQS4
I/O
SSTL
147
DQS5
I/O
SSTL
169
DQS6
I/O
SSTL
183
DQS7
I/O
SSTL
77
DQS8
I/O
SSTL
Data Strobe 8
Note: ECC
module
NC
NC
–
Note: Non-ECC
module
12
DM0
I
SSTL
Data Mask 7:0
26
DM1
I
SSTL
48
DM2
I
SSTL
62
DM3
I
SSTL
134
DM4
I
SSTL
148
DM5
I
SSTL
170
DM6
I
SSTL
184
DM7
I
SSTL
78
DM8
I
SSTL
NC
–
Pin
Buffer Function
Type Type
1,2
VREF
197
VDDSPD PWR –
EEPROM Power
Supply
9,10,
21,
22,
33,
34,
36,
45,
46,
57,
58,
69,
70,
81,
82,
92,
93,
94,
113,
114,
131,
132,
143,
144,
155,
156,
157,
167,
168,
179,
180,
191,
192
VDD
Power Supply
AI
–
PWR –
I/O Reference
Voltage
Data Mask 8
Note: ECC
module
NC
type
Name
type
Note: Non-ECC
module
EEPROM
195
SCL
I
CMOS Serial Bus Clock
193
SDA
I/O
OD
194
SA0
I
196
SA1
I
CMOS Slave Address
CMOS Select Bus 2:0
198
SA2
I
CMOS
Data Sheet
Serial Bus Data
10
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of SO-DIMM (cont’d)
Table 3
Pin Configuration of SO-DIMM (cont’d)
Pin#
Name
Pin
Buffer Function
Type Type
Pin#
Name
Pin
Buffer Function
Type Type
3,4,
15,
16,
27,
28,
38,
39,
40,
51,
52,
63,
64,
75,
76,
87,
88,
90,
103,
104,
125,
126,
137,
138,
149,
150,
159,
161,
162,
173,
174,
185,
186
VSS
GND –
85,
86,
97,
98,
124,
200
NC
NC
Ground Plane
Table 4
–
Not connected
Note: Pins
connected
Infineon
DIMMs
not
on
SO
Abbreviations for Pin Type
Abbreviation Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 5
Abbreviations for Buffer Type
Abbreviation Description
SSTL
Serial Stub Terminated Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Other Pins
199
VDDID
O
OD
VDD Identification
Note: Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB
Data Sheet
11
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
DQ16 VDD DQ18 DQ19 VDD DQS3 DQ26 VDD CB1/NC DQS8/NC VDD NC CK2/NC VDD NC A9 A7 A3 VDD BA0 S0 VSS DQ33 DQS4 VSS DQ40 DQ41 VSS DQ43 VDD VSS DQ49 DQS6 VSS DQ56 DQ57 VSS DQ59 SDA VDDSPD -
Pin 041
Pin 045
Pin 049
Pin 053
Pin 057
Pin 061
Pin 065
Pin 069
Pin 073
Pin 077
Pin 081
Pin 085
Pin 089
Pin 093
Pin 097
Pin 101
Pin 105
Pin 109
Pin 113
Pin 117
Pin 121
Pin 125
Pin 129
Pin 133
Pin 137
Pin 141
Pin 145
Pin 149
Pin 153
Pin 157
Pin 161
Pin 165
Pin 169
Pin 173
Pin 177
Pin 181
Pin 185
Pin 189
Pin 193
Pin 197
VSS DQ1 DQS0 VSS DQ8 DQ09 VSS DQ11 CK0 VSS -
Pin 003
Pin 007
Pin 011
Pin 015
Pin 019
Pin 023
Pin 027
Pin 031
Pin 035
Pin 039
DQ17 - Pin 043
DQS2 - Pin 047
VSS - Pin 051
DQ33 - Pin 055
DQ25 - Pin 059
VSS - Pin 063
DQ27 - Pin 067
CB0/NC - Pin 071
VSS - Pin 075
CB2/NC - Pin 079
CB3/NC - Pin 083
VSS - Pin 087
CK2/NC - Pin 091
CKE1/NC - Pin 095
A12/NC - Pin 099
VSS - Pin 103
A5 - Pin 107
A1 - Pin 111
A10/AP - Pin 115
WE - Pin 119
A13/NC - Pin 123
DQ32 - Pin 127
VDD - Pin 131
DQ34 - Pin 135
DQ35 - Pin 139
VDD - Pin 143
DQS5 - Pin 147
DQ42 - Pin 151
VDD - Pin 155
VSS - Pin 159
DQ48 - Pin 163
VDD - Pin 167
DQ50 - Pin 171
DQ51 - Pin 175
VDD - Pin 179
DQS7 - Pin 183
DQ58 - Pin 187
VDD - Pin 191
SCL - Pin 195
VDDID - Pin 199
Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040
- VSS
- DQ6
- DM0
- VSS
- DQ12
- DQ13
- VSS
- DQ15
- VDD
- VSS
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 Pin 188 Pin 192 Pin 196 Pin 200 -
BACKSIDE
Pin 001
Pin 005
Pin 009
Pin 013
Pin 017
Pin 021
Pin 025
Pin 029
Pin 033
Pin 037
FRONTSIDE
VREF DQ0 VDD DQ2 DQ3 VDD DQS1 DQ10 VDD CK0 -
DQ21
DM2
VSS
DQ28
DQ29
VSS
DQ31
CB4/NC
VSS
CB6/NC
CB7/NC
VSS
VDD
CKE0
A11
VSS
A4
A0
BA1
CAS
NC
DQ36
VDD
DQ38
DQ39
VDD
DM5
DQ46
VDD
CK1
DQ52
VDD
DQ54
DQ55
VDD
DM7
DQ62
VDD
SA1
NC
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 -
VREF
DQ4
VDD
DQ6
DQ7
VDD
DM1
DQ14
VDD
VSS
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 Pin 186 Pin 190 Pin 194 Pin 198 -
DQ20
VDD
DQ22
DQ23
VDD
DM3
DQ30
VDD
CB5/NC
DM8/NC
VDD
NC
VSS
VDD
NC
A8
A6
A2
VDD
RAS
S1/NC
VSS
DQ37
DM4
VSS
DQ44
DQ45
VSS
DQ47
CK1
VSS
DQ53
DM6
VSS
DQ60
DQ61
VSS
DQ63
SA0
SA2
MPPD0040
Figure 1
Pin Configuration Diagram 200-Pin SO-DIMM
Table 6
Address Format
Density
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh
Period
Interval
512MB
64M ×64
2
32M ×16
8
13/2/10
8K
64 ms
7.8 µs
Data Sheet
12
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Pin Configuration
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Figure 2
Block Diagram Raw Card A ×64 2 Ranks ×16
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5%
Data Sheet
13
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Voltage on I/O pins relative to VSS
VIN, VOUT –0.5
min.
typ.
max.
Unit Note/ Test
Condition
–
VDDQ +
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
VIN
VDD
VDDQ
TA
TSTG
PD
IOUT
–1
–
+3.6
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
–
1
–
W
–
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
V
—
0.51 ×
V
4)
VDDQ
VDDQ
VREF – 0.04
VDDQ
VREF + 0.04 V
5)
Input High (Logic1) Voltage VIH(DC)
VREF + 0.15
8)
Input Low (Logic0) Voltage VIL(DC)
–0.3
Input Voltage Level,
CK and CK Inputs
VIN(DC)
–0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
VDDQ + 0.6 V
8)6)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
7)
VDD
VDD
Device Supply Voltage
Output Supply Voltage
VDDQ
Output Supply Voltage
VDDQ
EEPROM supply voltage
VDDSPD
Supply Voltage, I/O Supply VSS,
Voltage
VSSQ
Input Reference Voltage
VREF
Device Supply Voltage
I/O Termination Voltage
(System)
Data Sheet
VTT
0
0.49 ×
0.5 ×
14
—
8)
8)
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 8
Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter
Symbol
Unit Note/Test Condition 1)
Values
Min.
Typ.
Max.
Input Leakage Current
II
–2
2
µA
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 8)9)
Output Leakage Current
IOZ
–5
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ 8)
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V 8)
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V 8)
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD.
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Data Sheet
15
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2
Current Specification and Conditions
>
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2N
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
16
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
Product Type
Organization
HYS64D64020GDL–6–B
HYS64D64020HDL–6–B
IDD Specification for HYS64D64020[H/G]DL–[5/6]–B
HYS64D64020GDL–5–B
HYS64D64020HDL–5–B
Table 9
512MB
512MB
×64
×64
2 Ranks
2 Ranks
–5
Unit
Note 1)2)
–6
Symbol
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
570
680
510
620
mA
3)
630
760
570
680
mA
3)4)
20
40
20
30
mA
5)
240
288
200
240
mA
5)
150
208
140
192
mA
5)
100
128
90
120
mA
5)
340
400
300
352
mA
5)
650
780
570
676
mA
3)4)
670
800
590
696
mA
3)
1130
1360
1010
1196
mA
3)
13.6
13.6
13.6
13.6
mA
5)
1410
1660
1250
1480
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
17
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.3
AC Characteristics
Table 10
AC Timing - Absolute Specifications –6/–5
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
–6
–5
DDR333
DDR400B
Unit
Note/ Test
Condition 1)
Min.
Max.
Min.
Max.
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)
–0.6
+0.6
–0.5
+0.5
ns
2)3)4)5)
0.45
0.55
0.45
0.55
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
ns
2)3)4)5)
min. (tCL, tCH)
6
12
min. (tCL, tCH)
5
12
ns
2)3)4)5)
CL = 3.0
2)3)4)5)
6
12
6
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
tDH
tDS
tIPW
0.45
—
0.4
—
ns
2)3)4)5)
0.45
—
0.4
—
ns
2)3)4)5)
2.2
—
2.2
—
ns
2)3)4)5)6)
DQ and DM input pulse width (each
input)
tDIPW
1.75
—
1.75
—
ns
2)3)4)5)6)
Data-out high-impedance time from
CK/CK
tHZ
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
Data-out low-impedance time from CK/ tLZ
CK
–0.7
+0.7
–0.6
+0.6
ns
2)3)4)5)7)
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated
DQ signals)
tDQSQ
—
+0.45
—
+0.40
ns
Data hold skew factor
tQHS
—
tQH
tHP –
tQHS
—
tHP –
tQHS
—
ns
2)3)4)5)
0.35
—
0.35
—
tCK
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ/DQS output hold time
DQS input low (high) pulse width (write tDQSL,H
cycle)
TSOPII
2)3)4)5)
+0.55
—
+0.50
ns
TSOPII
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
2)3)4)5)
2
—
2
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)8)
0.40
0.60
0.40
0.60
2)3)4)5)9)
0.25
—
0.25
—
tCK
tCK
Mode register set command cycle time tMRD
Write preamble setup time
Write postamble
Write preamble
Data Sheet
tWPRES
tWPST
tWPRE
18
2)3)4)5)
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 10
AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Address and control input setup time
Symbol
tIS
–6
–5
DDR333
DDR400B
Min.
Max.
Min.
Max.
0.75
—
0.6
—
Unit
ns
Note/ Test
Condition 1)
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
0.7
—
ns
slow slew
rate
3)4)5)6)10)
tRPRE
Read postamble
tRPST
Active to Precharge command
tRAS
Active to Active/Auto-refresh command tRC
Read preamble
2)3)4)5)
0.60
tCK
tCK
40
70E+3
ns
2)3)4)5)
—
55
—
ns
2)3)4)5)
0.9
1.1
0.9
1.1
0.40
0.60
0.40
42
70E+3
60
2)3)4)5)
period
Auto-refresh to Active/Auto-refresh
command period
tRFC
72
—
65
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tRP
tRAP
tRRD
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
18
—
15
—
ns
2)3)4)5)
12
—
10
—
ns
2)3)4)5)
tWR
tDAL
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)11)
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
tWTR
Exit self-refresh to non-read command tXSNR
Exit self-refresh to read command
tXSRD
Average Periodic Refresh Interval
tREFI
Internal write to read command delay
1
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
200
—
200
—
tCK
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
Data Sheet
19
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VOH(ac) and VOL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 11
SPD Codes for HYS64D64020[H/G]DL-5-B
Product Type
HYS64D64020GDL–5–B
HYS64D64020HDL–5–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC3200S–3033–1
PC3200S–3033–1
Label Code
JEDEC SPD Revision
Rev 1.0
Rev 1.0
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
0A
0A
5
Number of DIMM Ranks
02
02
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
50
50
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
10
10
14
Error Checking SDRAM Width
00
00
15
tCCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device
04
04
18
CAS Latency
1C
1C
19
CS Latency
01
01
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
60
60
50
50
75
75
50
50
3C
3C
28
28
3C
3C
30
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
28
31
Module Density per Rank
40
40
32
tAS, tCS [ns]
tAH, tCH [ns]
60
60
60
60
24
25
26
27
28
29
33
Data Sheet
21
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
SPD Contents
Table 11
SPD Codes for HYS64D64020[H/G]DL-5-B
Product Type
HYS64D64020GDL–5–B
HYS64D64020HDL–5–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC3200S–3033–1
PC3200S–3033–1
Label Code
JEDEC SPD Revision
Rev 1.0
Rev 1.0
Byte#
Description
HEX
HEX
34
40
40
35
tDS [ns]
tDH [ns]
40
40
36 - 40
not used
00
00
41
37
37
41
41
28
28
28
28
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
50
50
46
not used
00
00
47
DIMM PCB Height
01
01
48 - 61
not used
00
00
62
SPD Revision
10
10
63
Checksum of Byte 0-62
17
17
64
JEDEC ID Code of Infineon (1)
C1
C1
42
43
44
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
73
Part Number, Char 1
36
36
74
Part Number, Char 2
34
34
75
Part Number, Char 3
44
44
76
Part Number, Char 4
36
36
77
Part Number, Char 5
34
34
78
Part Number, Char 6
30
30
79
Part Number, Char 7
32
32
80
Part Number, Char 8
30
30
81
Part Number, Char 9
47
48
82
Part Number, Char 10
44
44
83
Part Number, Char 11
4C
4C
84
Part Number, Char 12
35
35
85
Part Number, Char 13
42
42
86
Part Number, Char 14
20
20
87
Part Number, Char 15
20
20
88
Part Number, Char 16
20
20
89
Part Number, Char 17
20
20
90
Part Number, Char 18
20
20
91
Module Revision Code
0x
0x
Data Sheet
22
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
SPD Contents
Table 11
SPD Codes for HYS64D64020[H/G]DL-5-B
Product Type
HYS64D64020GDL–5–B
HYS64D64020HDL–5–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC3200S–3033–1
PC3200S–3033–1
Label Code
JEDEC SPD Revision
Rev 1.0
Rev 1.0
Byte#
Description
HEX
HEX
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
99 -127
not used
00
00
Table 12
SPD Codes for HYS64D64020[H/G]DL-6-B
Product Type
HYS64D64020GDL–6–B
HYS64D64020HDL–6–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC2700S–2533–0
PC2700S–2533–0
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Description
HEX
HEX
Label Code
Byte#
0
Programmed SPD Bytes in E2PROM
80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
0A
0A
5
Number of DIMM Ranks
02
02
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
60
60
10
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
10
10
14
Error Checking SDRAM Width
00
00
15
tCCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device
04
04
18
CAS Latency
0C
0C
19
CS Latency
01
01
Data Sheet
23
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
SPD Contents
Table 12
SPD Codes for HYS64D64020[H/G]DL-6-B
Product Type
HYS64D64020GDL–6–B
HYS64D64020HDL–6–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC2700S–2533–0
PC2700S–2533–0
Label Code
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
75
75
70
70
00
00
30
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
31
32
24
25
26
00
00
48
48
30
30
48
48
2A
2A
Module Density per Rank
40
40
75
75
75
75
45
45
35
tAS, tCS [ns]
tAH, tCH [ns]
tDS [ns]
tDH [ns]
45
45
36
not used
00
00
37
not used
00
00
38
not used
00
00
39
not used
00
00
40
not used
00
00
41
3C
3C
48
48
30
30
2D
2D
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
55
55
46
not used
00
00
47
DIMM PCB Height
00
00
48 - 61
not used
00
00
62
SPD Revision
00
00
63
Checksum of Byte 0-62
0A
0A
64
JEDEC ID Code of Infineon (1)
C1
C1
65 - 71
JEDEC ID Code of Infineon (2 - 8)
00
00
72
Module Manufacturer Location
xx
xx
73
Part Number, Char 1
36
36
27
28
29
33
34
42
43
44
Data Sheet
24
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
SPD Contents
Table 12
SPD Codes for HYS64D64020[H/G]DL-6-B
Product Type
HYS64D64020GDL–6–B
HYS64D64020HDL–6–B
Organization
512 MB
512 MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
PC2700S–2533–0
PC2700S–2533–0
Label Code
JEDEC SPD Revision
Rev 0.0
Rev 0.0
Byte#
Description
HEX
HEX
74
Part Number, Char 2
34
34
75
Part Number, Char 3
44
44
76
Part Number, Char 4
36
36
77
Part Number, Char 5
34
34
78
Part Number, Char 6
30
30
79
Part Number, Char 7
32
32
80
Part Number, Char 8
30
30
81
Part Number, Char 9
47
48
82
Part Number, Char 10
44
44
83
Part Number, Char 11
4C
4C
84
Part Number, Char 12
36
36
85
Part Number, Char 13
42
42
86
Part Number, Char 14
20
20
87
Part Number, Char 15
20
20
88
Part Number, Char 16
20
20
89
Part Number, Char 17
20
20
90
Part Number, Char 18
20
20
91
Module Revision Code
0x
0x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95 - 98
Module Serial Number (1 - 4)
xx
xx
99 - 127
not used
00
00
Data Sheet
25
Rev. 1.0, 2004-05
HYS64D64020[H/G]DL–[5/6]–B
Small Outline DDR SDRAM Modules
Package Outlines
5
Package Outlines
67.6
3.8 MAX.
31.75
4 ±0.1
1.8 ±0.05
63.6 ±0.1
(2.15)
1
(2.45)
18.45 ±0.1
100
1±0.1
1.8 ±0.1
0.15
(2.4)
11.4 ±0.1
47.4 ±0.1
(2.7)
(2.15)
1.5 ±0.1
4 ±0.1
1±0.1
200
20 ±0.1
101
6 ±0.1
(2.45)
2 MIN.
2.55
0.25 -0.18
Detail of contacts
0.45 ±0.03
0.6 ±0.1
Burnished, no burr allowed
L-DIM-200-006
Figure 3
Data Sheet
Package Outlines – Raw Card A DDR-SDRAM SO-DIMM HYS64D64020[H/G]DL–[5/6]–B
26
Rev. 1.0, 2004-05
www.infineon.com
Published by Infineon Technologies AG