PHILIPS 74LVC16244A

INTEGRATED CIRCUITS
DATA SHEET
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V
input/output tolerant; 3-state
Product specification
Supersedes data of 2003 Jan 30
2003 Dec 08
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
FEATURES
DESCRIPTION
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
The 74LVC(H)16244A is a high-performance, low power,
low voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 Volt. These features allow the use of
these devices as a mixed 3.3 and 5 V environment.
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out
architecture
• Low inductance multiple power and ground pins for
minimum noise and ground bounce
The 74LVC(H)16244A is a 16-bit non-inverting buffer/line
driver with 3-state outputs. The device can be used as four
4-bit buffers, two 8-bit buffers or one 16-bit buffer. The
device features four Output Enables (1OE, 2OE, 3OE and
4OE), each controlling four of the 3-state outputs. A HIGH
on nOE causes the outputs to assume a high-impedance
OFF-state.
• Direct interface with TTL levels
• All data inputs have bushold (74LVCH16244A only).
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The 74LVC(H)16244A is identical to the 74LVC16240A
but has non-inverting outputs.
• Specified from −40 to +85 °C and −40 to +125 °C.
The 74LVCH16244A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nAn to nYn
CL = 50 pF; VCC = 3.3 V
3.0
ns
tPZH/tPZL
3-state output enable time nOE to nYn
CL = 50 pF; VCC = 3.3 V
3.5
ns
tPHZ/tPLZ
3-state output disable time nOE to nYn
CL = 50 pF; VCC = 3.3 V
3.7
ns
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per gate
outputs enabled
12
pF
outputs disabled
4.0
pF
VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2003 Dec 08
2
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nOE
nAn
nYn
L
L
L
L
H
H
H
X
Z
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE MATERIAL
CODE
74LVC16244ADL
−40 to +125 °C
48
SSOP48
plastic
SOT370-1
74LVCH16244ADL
−40 to +125 °C
48
SSOP48
plastic
SOT370-1
74LVC16244ADGG
−40 to +125 °C
48
TSSOP48
plastic
SOT362-1
74LVCH16244ADGG
−40 to +125 °C
48
TSSOP48
plastic
SOT362-1
74LVC16244AEV
−40 to +125 °C
56
VFBGA56
plastic
SOT702-1
74LVCH16244AEV
−40 to +125 °C
56
VFBGA56
plastic
SOT702-1
2003 Dec 08
3
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
PINNING
SYMBOL
PIN
BALL
DESCRIPTION
1OE
1
A1
output enable input (active LOW)
n.c.
−
A2, A3, A4, A5, K2, K3, K4, K5
not connected
1Y0
2
B2
data output
1Y1
3
B1
data output
GND
4, 10, 15, 21, 28, 34, 39, 45
B3, B4, D3, D4, G3, G4, J3, J4
ground (0 V)
1Y2
5
C2
data output
1Y3
6
C1
data output
VCC
7, 18, 31, 42
C3, H3, C4, H4
supply voltage
2Y0
8
D2
data output
2Y1
9
D1
data output
2Y2
11
E2
data output
2Y3
12
E1
data output
3Y0
13
F1
data output
3Y1
14
F2
data output
3Y2
16
G1
data output
3Y3
17
G2
data output
4Y0
19
H1
data output
4Y1
20
H2
data output
4Y2
22
J1
data output
4Y3
23
J2
data output
4OE
24
K1
output enable input (active LOW)
3OE
25
K6
output enable input (active LOW)
4A3
26
J5
data input
4A2
27
J6
data input
4A1
29
H5
data input
4A0
30
H6
data input
3A3
32
G5
data input
3A2
33
G6
data input
3A1
35
F5
data input
3A0
36
F6
data input
2A3
37
E6
data input
2A2
38
E5
data input
2A1
40
D6
data input
2A0
41
D5
data input
1A3
43
C6
data input
1A2
44
C5
data input
1A1
46
B6
data input
1A0
47
B5
data input
2OE
48
A6
output enable input (active LOW)
2003 Dec 08
4
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
1OE
1
48 2OE
1Y0
2
47 1A0
1Y1
3
46 1A1
GND
4
45 GND
1Y2
5
44 1A2
1Y3
6
43 1A3
VCC
7
42 VCC
2Y0
8
41 2A0
2Y1
9
40 2A1
GND 10
39 GND
2Y2 11
38 2A2
2Y3 12
3Y0 13
16244
16244
K
J
H
G
F
E
D
C
B
A
37 2A3
36 3A0
3Y1 14
35 3A1
GND 15
34 GND
3Y2 16
33 3A2
3Y3 17
32 3A3
VCC 18
31 VCC
4Y0 19
30 4A0
4Y1 20
29 4A1
GND 21
28 GND
4Y2 22
27 4A2
4Y3 23
26 4A3
4OE 24
25 3OE
74LVC16244A;
74LVCH16244A
ball A1
1 2 3 4 5 6
index area
001aaa196
mna706
Fig.1 Pin configuration SSOP48 and TSSOP48.
2003 Dec 08
Fig.2 Pin configuration VFBGA56.
5
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
handbook,47
halfpage
2
1A0
13
36
1Y0
74LVC16244A;
74LVCH16244A
3A0
3Y0
1OE
46
35
3
1A1
1Y1
2OE
14
3A1
3Y1
3OE
4OE
1A2
1A3
1OE
44
5
1Y2
43
3A2
6
1Y3
1
3A3
3OE
41
8
3Y2
1A0
1A1
17
32
3Y3
1A2
1A3
25
2A0
40
4A0
4Y0
29
9
2A1
2Y1
2A2
19
30
2Y0
2A3
3A0
20
4A1
4Y1
3A1
3A2
2A2
38
11
2Y2
4A2
22
27
3A3
4Y2
4A0
2A3
37
12
2Y3
4A3
23
26
4A1
4Y3
4A2
2OE
48
4OE
25
24
24
4A3
47
3EN
4EN
1
2
3
44
5
43
6
41
1 2
8
40
9
38
11
37
12
36
1 3
13
35
14
33
16
32
17
30
1 4
19
29
20
27
22
26
23
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
mna704
Fig.3 Logic symbol.
handbook, halfpage
1
46
MNA996
Fig.4 Logic symbol (IEEE/IEC).
VCC
to internal circuit
data input
MNA705
Fig.5 Bushold circuit.
2003 Dec 08
1EN
2EN
16
33
2A1
2A0
1
48
6
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
supply voltage
VI
input voltage
VO
output voltage
Tamb
operating ambient
temperature
tr, tf
input rise and fall times
CONDITIONS
MIN.
MAX.
UNIT
for maximum speed
performance
2.7
3.6
V
for low voltage applications
1.2
3.6
V
0
5.5
V
output HIGH or LOW state
0
VCC
V
output 3-state
0
5.5
V
in free air
−40
+125
°C
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
−0.5
+6.5
V
IIK
input diode current
VI < 0
−
−50
mA
VI
input voltage
note 1
−0.5
+6.5
V
IOK
output diode current
VO > VCC or VO < 0
−
±50
mA
VO
output voltage
output HIGH or LOW state;
note 1
−0.5
VCC + 0.5
V
output 3-state; note 1
−0.5
+6.5
V
VO = 0 to VCC
IO
output source or sink current
−
±50
mA
ICC, IGND
VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation
SSOP and TSSOP package Tamb = −40 to +125 °C; note 2
−
500
mW
Tamb = −40 to +125 °C; note 3
−
1000
mW
VFBGA package
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
2003 Dec 08
7
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCC (V)
OTHER
Tamb = −40 to +85 °C; note 1
VIH
VIL
LOW-level input voltage
VOH
HIGH-level output voltage
VOL
1.2
VCC
−
−
V
2.7 to 3.6
2.0
−
−
V
1.2
−
−
0
V
2.7 to 3.6
−
−
0.8
V
IO = −100 µA
2.7 to 3.6
VCC − 0.2
VCC
−
V
IO = −12 mA
2.7
VCC − 0.5
−
−
V
IO = −18 mA
3.0
VCC − 0.6
−
−
V
IO = −24 mA
3.0
VCC − 0.8
−
−
V
IO = 100 µA
2.7 to 3.6
−
0
0.20
V
IO = 12 mA
2.7
−
−
0.40
V
IO = 24 mA
3.0
−
−
0.55
V
HIGH-level input voltage
LOW-level output voltage
VI = VIH or VIL
VI = VIH or VIL
ILI
input leakage current
VI = 5.5 V or GND;
note 2
3.6
−
±0.1
±5
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND;
note 2
3.6
−
0.1
±5
µA
Ioff
power-off leakage supply
current
VI or VO = 5.5 V
0.0
−
0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
3.6
−
0.1
20
µA
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin
IO = 0
2.7 to 3.6
−
5
500
µA
IBH
bushold LOW sustaining
current
VI = 0.8 V;
notes 3 and 4
3.0
75
−
−
µA
IBHH
bushold HIGH sustaining
current
VI = 2.0 V;
notes 3 and 4
3.0
−75
−
−
µA
IBHLO
bushold LOW overdrive
current
notes 3 and 5
3.6
500
−
−
µA
IBHHO
bushold HIGH overdrive
current
notes 3 and 5
3.6
−500
−
−
µA
2003 Dec 08
8
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +125 °C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
1.2
VCC
−
−
V
2.7 to 3.6
2.0
−
−
V
1.2
−
−
0
V
2.7 to 3.6
−
−
0.8
V
VI = VIH or VIL
IO = −100 µA
2.7 to 3.6
VCC − 0.3
−
−
V
IO = −12 mA
2.7
VCC − 0.65
−
−
V
IO = −18 mA
3.0
VCC − 0.75
−
−
V
IO = −24 mA
3.0
VCC − 1
−
−
V
IO = 100 µA
2.7 to 3.6
−
−
0.3
V
IO = 12 mA
2.7
−
−
0.6
V
IO = 24 mA
3.0
−
−
0.8
V
VI = VIH or VIL
ILI
input leakage current
VI = 5.5 V or GND;
note 2
3.6
−
−
±20
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND;
note 2
3.6
−
−
±20
µA
Ioff
power-off leakage supply
current
VI or VO = 5.5 V
0.0
−
−
±20
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
3.6
−
−
80
µA
∆ICC
additional quiescent supply VI = VCC − 0.6 V;
current per input pin
IO = 0
2.7 to 3.6
−
−
5000
µA
IBH
bushold LOW sustaining
current
VI = 0.8 V;
notes 3 and 4
3.0
60
−
−
µA
IBHH
bushold HIGH sustaining
current
VI = 2.0 V;
notes 3 and 4
3.0
−60
−
−
µA
IBHLO
bushold LOW overdrive
current
notes 3 and 5
3.6
500
−
−
µA
IBHHO
bushold HIGH overdrive
current
notes 3 and 5
3.6
−500
−
−
µA
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin.
3. Valid for data inputs of bushold parts (74LVCH16244A) only. For data inputs only, control inputs do not have a
bushold circuit.
4. The specified sustaining current at the data inputs holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2003 Dec 08
9
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
CONDITIONS
SYMBOL
PARAMETER
MIN.
WAVEFORMS
TYP.
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C; note1
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay nAn to nYn
3-state output enable time nOE to nYn
see Figs 6 and 8
see Figs 7 and 8
3-state output disable time nOE to nYn see Figs 7 and 8
1.2
−
11.0
−
ns
2.7
1.0
−
4.7
ns
3.0 to 3.6
1.1
3.0(2)
4.1
ns
1.2
−
15.0
−
ns
2.7
1.0
−
5.8
ns
3.0 to 3.6
1.0
3.5(2)
4.6
ns
1.2
−
10.0
−
ns
2.7
1.0
−
6.2
ns
3.0 to 3.6
1.8
3.7(2)
5.2
ns
Tamb = −40 to +125 °C
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay nAn to nYn
3-state output enable time nOE to nYn
see Figs 6 and 8
see Figs 7 and 8
3-state output disable time nOE to nYn see Figs 7 and 8
Notes
1. All typical values are measured at Tamb = 25 °C.
2. These typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2003 Dec 08
10
1.2
−
−
−
ns
2.7
1.0
−
6.0
ns
3.0 to 3.6
1.1
−
5.5
ns
1.2
−
−
−
ns
2.7
1.0
−
7.5
ns
3.0 to 3.6
1.0
−
6.0
ns
1.2
−
−
−
ns
2.7
1.0
−
8.0
ns
3.0 to 3.6
1.8
−
6.5
ns
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
AC WAVEFORMS
handbook, halfpage VI
nAn input
VM
VM
GND
tPLH
tPHL
VOH
VM
nYn output
VOL
VM
MNA171
INPUT
VCC
VM
VI
tr = tf
1.2 V
0.5 × VCC
VCC
≤ 2.5 ns
2.7 V
1.5 V
2.7 V
≤ 2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 The input nAn to output nYn propagation delays.
2003 Dec 08
11
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
VI
handbook, full pagewidth
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
tPZH
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
disabled
outputs
enabled
MNA362
INPUT
VCC
VM
VI
tr = tf
1.2 V
0.5 × VCC
VCC
≤ 2.5 ns
2.7 V
1.5 V
2.7 V
≤ 2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 V at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 V at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 3-state enable and disable times.
2003 Dec 08
12
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
VEXT
handbook, full pagewidth
VCC
VI
PULSE
GENERATOR
RL
VO
D.U.T.
CL
RT
RL
MNA616
VCC
VI
CL
RL
Ω(1)
VEXT
tPLH/tPHL tPZH/tPHZ
tPZL/tPLZ
open
GND
2 × VCC
1.2 V
VCC
50 pF
500
2.7 V
2.7 V
50 pF
500 Ω
open
GND
2 × VCC
3.0 to 3.6 V
2.7 V
50 pF
500 Ω
open
GND
2 × VCC
Note
1. The circuit performs better when RL = 1000 Ω.
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
2003 Dec 08
13
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
2003 Dec 08
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-118
14
o
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
2003 Dec 08
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
15
o
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
B
D
SOT702-1
A
ball A1
index area
A
E
A2
A1
detail X
e1
C
∅v M C A B
b
e
∅w M C
y1 C
1/2 e
y
K
J
H
e
G
F
e2
E
D
1/2 e
C
X
B
A
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
A1
A2
b
D
E
1
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
OUTLINE
VERSION
SOT702-1
2003 Dec 08
e
e1
0.65
3.25
v
e2
5.85
0.15
REFERENCES
IEC
JEDEC
JEITA
w
0.08
y
0.08
y1
0.1
0
2.5
5 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
02-08-08
03-07-01
MO-225
16
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Dec 08
17
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected]
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/07/pp18
Date of release: 2003
Dec 08
Document order number:
9397 750 12369