INTEGRATED CIRCUITS 74LVC10A Triple 3-input NAND gate Product specification 1998 Apr 28 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A FEATURES DESCRIPTION • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • ICC category: SSI The 74LVC10A is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10A provides the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay nA, nB, nC to nY CI Input capacitance CPD CONDITIONS CL = 50 pF; VCC = 3.3 V Power dissipation capacitance per gate VI = GND to VCC1 TYPICAL UNIT 3.9 ns 5.0 pF 26 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO PACKAGES –40°C to +85°C 74LVC10A D 74LVC10A D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC10A DB 74LVC10A DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC10A PW 74LVC10APW DH SOT402-1 PIN CONFIGURATION 1A LOGIC SYMBOL 14 VCC 1 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 2Y 6 9 3A GND 7 8 3Y 1 1A 2 1B 13 1C 3 2A 4 2B 5 2C 9 3A 10 3B 11 3C 1Y 12 2Y 6 3Y 8 SV00416 SV00417 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 3, 9 1A – 3A Data inputs 2, 4, 10 1B – 3B Data inputs 7 GND Ground (0 V) 12, 6, 8 1Y – 3Y Data outputs 13, 5, 11 1C – 3C Data inputs 14 1998 Apr 28 VCC Positive supply voltage 2 853-1973 19308 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A LOGIC SYMBOL (IEEE/IEC) 1 2 13 FUNCTION TABLE INPUTS & 12 3 4 5 & 9 10 11 & 6 8 SV00418 LOGIC DIAGRAM (ONE GATE) OUTPUTS nA nB nC nY L L L L L L H H L H L H H H H H H H H H L L H H L H L H H H H L NOTES: H = HIGH voltage level L = LOW voltage level A B Y C SV00419 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VCC DC supply voltage (for max. speed performance) 2.7 3.6 V VCC DC supply voltage (for low-voltage applications) 1.2 3.6 V 0 5.5 V –40 +85 °C 0 0 20 10 ns/V VI Tamb tr, tf DC input voltage range Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC PARAMETER CONDITIONS DC supply voltage RATING UNIT –0.5 to +6.5 V IIK DC input diode current VI 0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO VCC or VO 0 50 mA DC output voltage; output HIGH or LOW Note 2 –0.5 to VCC +0.5 DC input voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VI/O IO IGND, ICC Tstg PTOT DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K V 50 mA 100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 28 3 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C TYP1 MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O II ∆ICC 2.0 V GND VCC = 2.7 to 3.6V LOW level output voltage ICC VCC VCC = 2.7 to 3.6V VCC = 1.2V HIGH level output voltage VOL VCC = 1.2V UNIT MAX V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*1.0 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.55 Input leakage current VCC = 3.6V; VI = 5.5V or GND Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 V "0.1 "5 µA 0.1 10 µA 5 500 µA NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF LIMITS SYMBOL PARAMETER tPHL/ tPLH VCC = 3.3V ±0.3V WAVEFORM Propagation delay nA, nB, nC to nY Figures 1, 2 VCC = 2.7V MIN TYP1 MAX MIN MAX 1.5 3.9 5.7 1.5 6.7 UNIT ns NOTE: 1. These typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS TEST CIRCUIT VM = 1.5 V at VCC w 2.7 V VM = 0.5 VCC at VCC < 2.7 V VOL and VOH are the typical output voltage drop that occur with the output load. S1 VCC 2 * VCC Open GND 500Ω VI VI nA, nB, nC INPUT VO PULSE GENERATOR VM D.U.T. 50pF RT GND t PHL CL 500Ω t PLH VOH nY OUTPUT VM SWITCH POSITION VOL TEST SV00420 tPLH/tPHL Figure 1. Input (nA, nB, nC) to output (nY) propagation delays. S1 Open VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV00903 Figure 2. Load circuitry for switching times. 1998 Apr 28 4 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Apr 28 5 SOT108-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Apr 28 6 SOT337-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Apr 28 7 SOT402-1 Philips Semiconductors Product specification Triple 3-input NAND gate 74LVC10A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 8 Date of release: 07-98 9397-750-04482