Philips Semiconductors Product specification Call progress decoder NE5900 DESCRIPTION PIN CONFIGURATION The NE5900 call progress decoder (CPD) is a low cost, low power CMOS integrated circuit designed to interface with a microprocessor-controlled smart telephone capable of making preprogrammed telephone calls. The call progress decoder information to permit microprocessor decisions whether to initiate, continue, or terminate calls. A tri-state, 3-bit output code indicates the presence of dial tone, audible ring-back, busy signal, or re-order tones. D1 and N Packages A front-end bandpass filter is accomplished with switched capacitors. The bandshaped signal is detected and the cadence is measured prior to output decoding. In addition to the three data bits, a buffered bandpass output and envelope output are available. All logic inputs and outputs can interface with LSTTL, CMOS and NMOS. INPUT 1 16 5V VREF 2 15 ANALOG OUT EXT CLOCK IN/XTAL1 3 14 TRI-STATE ENABLE XTAL2 4 13 ENVELOPE TEST IN 5 12 BIT 1 CLEAR IN 6 11 BIT 2 COUNT IN PROGRESS 7 10 BIT 3 0V 8 9 DATA VALID TOP VIEW NOTE: 1. SOL — Released in large SO package only. Circuit features include low power consumption and easy application. Few and inexpensive external components are required. A typical application requires a 3.58MHz crystal or clock, 470kΩ resistor, and two bypass capacitors. The NE5900 is effective where traditional call progress tones, PBX tones, and precision call progress tones must be correctly interpreted with a single circuit. SR01142 Figure 1. Pin Configuration APPLICATIONS • Modems • PBXs • Security equipment • Auto dialers • Answering machines • Remote diagnostics • Pay telephones FEATURES • Fully decoded tri-state call progress status output • Works with traditional, precision, or PBX call progress tones • Low power consumption • Low cost 3.58MHz crystal or clock • No calibration or adjustment • Interfaces with LSTLL, CMOS, NMOS • Easy application ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 16-Pin Plastic Small Outline (SOL) Package 0 to +70°C NE5900DK SOT162-1 16-Pin Plastic Dual In-Line (DIP) Package 0 to +70°C NE5900N SOT38-4 1986 May 8 1 853-0842 83667 Philips Semiconductors Product specification Call progress decoder NE5900 BLOCK DIAGRAM ANALOG OUT 0V 10kΩ INPUT FILTER 5V VREF 10kΩ TRI-STATE ENABLE DETECTOR ENVELOPE BIT 1 EXT CLOCK IN/XTAL1 TIMING DECODER BIT 2 TRI-STATE XTAL2 BIT 3 TEST IN CLEAR IN COUNT IN PROGRESS DATA VALID SR01143 Figure 2. NE5900 Block Diagram ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VDD Supply voltage VIN Logic control input voltages VIN All other input voltages1 VOUT Output voltages TSTG Storage temperature range RATING UNITS 9 V -0.3 to +16 V -0.3 to VCC + 0.3 V -0.3 to VCC + 0.3 V -65 to +150 °C 0 to +70 °C TSOLD Lead soldering temperature (10s) +300 °C TJMAX Junction temperature +150 °C TA Operating temperature range NOTE: 1. Includes Pin 3 — Ext Clock In 1986 May 8 2 Philips Semiconductors Product specification Call progress decoder NE5900 DC ELECTRICAL CHARACTERISTICS VCC = +3.3V, TA = 25°C; unless otherwise stated. SYMBOL VDD PARAMETER TEST CONDITIONS LIMITS UNITS MIN TYP MAX 4.5 5.0 5.5 V As above with no output loads 2.0 4.0 mA Input threshold Pin 1 level, frequency = 460Hz, VDD = VREF Output Pin 13 = VDD -39 -35 dB1 Signal rejection Pin 1 level, frequency = 300Hz, VDD = VREF Output Pin 13 = 0V -50 dB1 Low frequency2 rejection Pin 1 frequency, 0dB max., VDC = VREF Output Pin 13 = 0V 180 Hz High frequency2 rejection Pin 1 frequency, 0dB max., VDC = VREF Output Pin 13 = 0V 800 Pin 16 Pin 14 = VDD Pin 5, 6 = 0V Power supply voltage Quiescent current Hz VIH Logic 1 level Pins 6, 14 2.0 15 V VIL Logic 0 level Pins 6, 14 0 0.8 V IIH Logic 1 input current Pins 3, 6, 14 = VDD -1.0 1.0 µA IIL Logic 0 input current Pins 3, 6, 14 = 0V -1.0 1.0 µA VIH Logic 1 input voltage Pin 3 External Clock In/XTAL VDD – 1 VDD V VIL Logic 0 input voltage Pin 3 External Clock In/XTAL 0 1.0 V 0 0.4 V VOL Logic 0 output voltage ISINK = 1.6mA Pins 7, 9, 10, 11, 12, 13 VOH Logic 1 output voltage ISOURCE = 0.5mA Pins 7, 9, 10, 11, 12, 13 VDD – 0.4 VDD V IOZ Tri-state leakage VOUT = VDD or 0V Pins 10, 11, 12, 13, Pin 14 = 0V -3.0 3.0 µA Filter output gain Input Pin 1, 460Hz – 20dB, VDC = VREF Output Pin 15, RLOAD = 1MΩ 6.5 10.5 dB As above from 300Hz to 630Hz, referenced to 460Hz -1.0 1.0 dBmo Filter frequency response Input impedance VREF Reference voltage RREF Reference resistance Envelope response time Pin 1, frequency = 460MHz 1 Pin 2, VDD = 5V 2.4 8.5 MΩ 2.5 2.6 V Pin 2 5 Ω Time from removal or application of 460Hz – 20dB (VDC = VREF on Pin 1) to response of Pin 13 38 ms NOTE: 1. 0dB = 0.775VRMS 2. By design; not tested. input clock frequency of 3.58MHz. An on-board inverter between Pins 3 and 4 can be used either as a crystal oscillator or as a buffer for an external 3.58MHz clock signal. The switched capacitor filters provide typical rejection of greater than 40dB for frequencies below 120Hz and above 1.6kHz. The NE5900 uses the signal in the call progress tone passband and the cadence of interrupt rate of the signal to determine which call progress tone is present. Figure 3 shows a detailed block diagram of the NE5900. The signal input from the phone line is coupled through a 470kΩ resistor which, together with two internal capacitors and an internal resistor, form an anti-aliasing filter. This passive low pass filter strongly rejects AM radio interference. Insertion loss is typically 1.5dB at 460Hz. The 470kΩ resistor also provides protection from the transients. The input (Pin 1) DC voltage can be derived from VREF (Pin 2) or allowed to self-bias through a series coupling capacitor (10nF minimum). The decoder responds to signals between 300Hz and 630Hz with a threshold of -39dB typical (0dB = 0.775VRMS). The decoder will not respond to any signal below -50dB or to tones up to 0dB which are below 180Hz or above 800Hz. Dropouts of 20ms or bursts of only 20ms duration are ignored. A gap of 40ms or a valid tone of 40ms is detected. The buffered output of the switched capacitor filter is available at the analog output, Pin 15. A logic output representing the detected envelope of this signal is available at the envelope output, Pin 13. Following this is a switched capacitor bandpass filter which accepts call progress tones and inhibits tones not in the call progress band of 300Hz to 630Hz. The bandpass limits are determined by the 1986 May 8 3 Philips Semiconductors Product specification Call progress decoder NE5900 post-dialing interval. Note that the end of dial tone in interpreted as a valid ringing signal. At the start of an in-band tone (envelope output goes high), a 2.3 second interval is timed out. Transitions of the envelope during this interval are counted to determine the signal present. At 2.3 seconds, the three bits of data representing this decision are stored in the latch and appear at the outputs. A data valid signal goes high at this time, signaling that the data bits, Pins 10 – 12, can be read. The clear input resets all internal registers and the output latch, and is to be set low after the completion of dialing. The clear input should be pulsed high for proper operation. Recommended pulse width is between 0.2µs and 20ms. If clear is held high when envelope is high, a false output pulse (Pin 13) can result when clear is returned low. The output code is as follows: Pin 12 Pin 11 Pin 10 Dial Tone 0 0 0 Ringing Signal 1 0 0 Busy Signal 0 1 0 Re-order Tone 0 0 1 Overflow 1 1 1 For applications where dialing is done by a person rather than by a microprocessor, an uncertainty exists about the number of digits to be dialed (local vs long distance). In such situations it is possible to clear the NE5900 by application of the DTMF signal or dial pulses to the clear pin (Pin 6). When dialing is complete, the device is cleared and ready to respond to the next call progress unit. Enable is held at 5V to enable Pins 10, 11, 12 and 13. When enable is brought low, data valid is also set low. Enable must remain high while the data is also set low. Enable must remain high while the data is being read. The test pin is for production test only and must be kept low in all user applications. The overflow condition occurs in the event that too many transitions occur during the 2.3 second interval. This can result from noise, voice, or other line disturbances not normally present during the BUFFER INPUT ANTI-ALIAS FILTER SC BANDPASS FILTER 5V EXT CLOCK IN/XTAL1 IN/XTAL2 R1 3.58MHz OSCILLATOR LOWPASS FILTER DIGITAL DETECTOR 10kΩ VREF R2 10kΩ 0V CLEAR IN CLOCK DIVIDERS DECODER LOGIC ANALOG DETECTOR TRI-STATE ENABLE ENVELOPE COUNT IN PROGRESS 2.3 SECOND TIMER DECODER LATCHES TRI-STATE BUFFERS DATA VALID BIT 1 BIT 2 BIT 3 SR01144 Figure 3. Detailed Block Diagram CPD Figure 4 shows a typical application of the call progress decoder. The designer can utilize the input signal, clock, bus, or microprocessor interface which best serves the application. Figure 6 gives a typical timing diagram for the application of Figures 4 and 5. In this application only one external component is needed an no microprocessor activity other than clear is required. Figure 5 shows the recommended direct interface to the telephone line. Bus connection is possible by utilizing tri-state, and internal timing is accomplished with a 3.58MHz crystal. 1986 May 8 4 Philips Semiconductors Product specification Call progress decoder NE5900 TO EAR-PIECE 470kΩ 3.58MHz IN 10nF 470kΩ 1 16 2 15 3 14 4 1 13 ENVELOPE 12 BIT 1 6 11 BIT 2 7 10 BIT 3 8 9 INTERRUPT NE5900 5 2 10nF OPTIONAL CAPACITIVE INPUT 5V START CLEAR SR01145 Figure 4. Typical Application IN1 C1 10nF IN2 C2 R5 R1 100kΩ R2 1 16 2 15 3 14 ENABLE 4 13 ENVELOPE 470kΩ + AV – R4 5 10nF 100kΩ NE5900 12 100kΩ R3 100kΩ R6 10MΩ 3.58MHz 5V 6 11 7 10 8 9 DECODED OUTPUTS TO PROCESSOR INTERRUPT START C3 1µF CLEAR SR01146 Figure 5. Typical Two-Wire Application 1986 May 8 5 Philips Semiconductors Product specification Call progress decoder NE5900 INPUT ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ CLEAR 38ms TYPICAL ENVELOPE 2.27 SECONDS DATA VALID 1.1 SECONDS BIT 1 BIT 2 BIT 3 42ms TYPICAL COUNT IN PROGRESS SR01147 Figure 6. 1986 May 8 6 Philips Semiconductors Product specification Call progress decoder NE5900 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 OUTPUT CURRENT (mA) (Pin 13) SUPPLY CURRENT (mA) (Pin 16) 3.0 2.5 2.0 1.5 1.0 0.5 -2.5 -5.0 -7.5 -10.0 -12.5 0.0 3.0 3.5 4.0 4.5 5.0 -15.0 5.5 0 SUPPLY VOLTAGE (VDD) (Pin 16) 1 2 3 4 5 OUTPUT VOLTAGE (Pin 13) SR01148 SR01151 Figure 7. Power Supply Current vs VDD Figure 10. Output Voltage Current Curve Digital Output High LEVEL RELATIVE TO 460Hz (dBV) (Pin 15) OUTPUT VOLTAGE (Pin 4) 5 4 3 2 1 0 0 1 2 3 4 0 -20 -40 -60 5 100 1000 FREQUENCY (40 TO 4000Hz) INPUT VOLTAGE (Pin 3) SR01149 SR01152 Figure 11. Filter Frequency Response 50 -20 40 -25 Pin 1 LEVEL (dB) OUTPUT CURRENT SINK (mA) (Pin 13) Figure 8. Voltage Transfer Curve 30 20 -35 -40 10 -45 0 0 2 3 4 1 OUTPUT VOLTAGE (Pin 13) -50 300 5 SR01150 Figure 9. Digital Output Low 1986 May 8 -30 350 400 450 500 550 FREQUENCY (Hz) 600 Figure 12. Typical Threshold 7 650 SR01153