PHILIPS SAA7215HS

INTEGRATED CIRCUITS
DATA SHEET
SAA7215; SAA7216; SAA7221
Integrated MPEG AVGD decoders
Preliminary specification
Supersedes data of 1998 Sep 11
File under Integrated Circuits, IC02
2000 Jan 31
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
FEATURES
CPU related features
General features
• 16-bit data, 22-bit address, Chip Select, Data Strobe
and DaTa ACKnowledge external control protocol
• Integrated MPEG AVGD decoder: audio, video and
graphics decoding and digital video encoding
• Fast 16-bit data plus 22-bit address synchronous
interface with the SAA7214, SAA7219 family at up to
40.5 MHz
• 5 planes display chain: background colour, background
plane, MPEG display plane, graphics plane and cursor
plane
• Asynchronous interface possible with external
microcontroller
• 16-Mbit or 32-Mbit external Synchronous DRAM
(SDRAM) for MPEG audio and video decoding and
graphics data storage
• Support of fast DMA transfer
• Flexible bidirectional interface to external SDRAM
• Single or double external SDRAM organized as
1 M × 16 or 2 × 1 M × 16 (two independent 16-bit data
bus) interfacing at 81 MHz. Due to efficient memory use
in MPEG decoding, more than 1 Mbit is available for
graphics in the single SDRAM configuration whereas
17 Mbits are available in the double SDRAM
configuration.
• High speed/low latency interface with second graphics
SDRAM
• All basic operations of the AVGD decoder are possible
in both 16- and 32-Mbit configuration; enhanced
performance is achieved by the use of 32-Mbit external
SDRAM
• Two programmable independent interrupt lines
available
• Byte access to the full SDRAM in the upper 16-Mbit
address range
• Independent memory mapping of SDRAM and control
registers
• Supports Motorola 68xxx interfaces as well as LSI
L64108 interface.
• Targeted to BSkyB 3.0 and Canal+ basic box and web
box specifications
MPEG-2 system features
• Parsing of MPEG-2 PES and MPEG-1 packet streams
• Fast 16-bit data + 22-bit address synchronous or
asynchronous interface with external controller at up to
40.5 MHz
• Double system time clock counters
• Stand-alone or supervised audio/video synchronization
• Dedicated input for compressed audio and video in
Packetized Elementary Stream (PES) or Elementary
Stream (ES) in byte wide or bit serial format.
Accompanying strobe signals distinguish between audio
and video data. Transport stream error correction
available.
• Processing of errors flagged by channel decoding
section.
MPEG-2 video features
• Decoding of MPEG-2 video up to main level, main profile
• Audio and/or video can also be input via the CPU
interface in PES or ES in 8 or 16-bit parallel format
• Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures. Picture format 720 × 576 at 50 Hz or 720 × 480
at 60 Hz.
• Single 27 or 40.5 MHz external clock for time base
reference and internal processing. Internal system time
base at 90 kHz can be synchronized via CPU port.
All required decoding and presentation clocks are
generated internally.
• Support of constant and variable bit rates up to
15 Mbits/s for the elementary stream
• Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
• Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
• Flexible horizontal scaling from 0.5 up to 4 allows easy
aspect ratio conversion including support for 2.21 : 1
aspect ratio movies; in case of shrinking an anti-aliasing
pre-filter is applied
• Optimum compatibility with T-MIPS controller family
(SAA7214, SAA7219 and successors)
• Boundary scan testing implemented
• External SDRAM self test
• Supply voltage: 3.3 V; package: SQFP208.
2000 Jan 31
2
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
• Vertical scaling with fixed factors 0.5, 0.75, 1 or 2;
factor 0.5 realizes picture shrink. Factor 2 can be used
for up-conversion of pictures with 288 (240) lines or
less; factor 0.75 is used for letterbox presentation.
– CRC error detection with automatic mute
• Horizontal and vertical scaling can be combined to scale
pictures to 1⁄4 of their original size, thus freeing up
screen space for graphic applications like electronic
program guides
– Storage of last 54 bytes in ancillary data field
– Constant and variable bit rates up to 448 kbit/s
– Selectable output channel in dual channel mode
– Dynamic range control at output.
• Muting possibility via external controller; automatic
muting in case of errors
• Non full screen MPEG pictures can be displayed in a
box of which position and background colour are
adjustable by the external microcontroller; structured
background is available as part of the graphic features
• Generation of ‘beeps’ with programmable tone height,
duration and amplitude
• Linear PCM decoding
– Support for up to 8 channels linear PCM elementary
audio streams
• Nominal video input buffer size for MP at ML 2.7-Mbit
• Video output may be slaved to internally (master)
generated or externally (slave) supplied
HV synchronization signals or CCIR-656 contained
synchronization signals. The position of active video is
programmable. Display phase is not affected by MPEG
timebase changes.
– Supports for 8, 16, 20 and 24 bit/sample
– Supports for bit rates up to 6.144 Mbit/s
– 96 kHz LPCM samples will be mapped to a 48 kHz
multi-channel format
– Volume control for linear PCM samples in three
steps: −6, −12 and −18 dB.
• Decoding and presentation can be independently
handled under CPU control
• Burst-formatting for interconnection with an external
multi-channel decoder
• Various trick modes under control of external
microcontroller:
– AC-3 elementary streams (IEC1937)
– Freeze field/frame on I- or P-frames; restart on
I-picture
– MPEG-2 multi-channel streams in ES or PES format
– Output via the digital audio output or the IEC 958
output.
– Freeze field on B-frames; restart at any moment
– Scanning and decoding of I- or I- and P-frames in a
IBP sequence
• Output stage
– Global control for volume and balance
– Single step mode
– Serial multi-channel digital audio output with 16, 18,
20 or 22 bits per sample, compatible either to I2S or
Japanese formats; output can be set to high
impedance mode via the external controller
– Repeat/skip field for time base correction
– Repeat/skip frame for display parity integrity.
• Synchronization modes: DTS controlled, DTS free
running, software controlled, buffer controlled
– IEC958 (Serial SPDIF) audio output; output can be
set to high impedance mode
• DTS register can be set via external controller;
programmable processing delay compensation.
– Clock output 256 or 384 × fs for external
DA converter or clock input; output can be set to high
impedance mode.
MPEG-2 audio features
• Supported audio sampling frequencies:
48, 44.1, 32, 24, 22.05 and 16 kHz
• Audio FIFO in external SDRAM; programmable buffer
size, at least 64 kbit is available
• Independent channel volume control and programmable
inter-channel crosstalk through a baseband audio
processing unit
• Synchronization modes: PTS controlled, PTS free
running, software controlled, buffer controlled
• PTS register can be set via external controller;
programmable processing delay compensation.
• MPEG audio decoder
– Decoding of 2 channels, layer I and II MPEG-1 audio
and low sampling frequency extension of MPEG-2
Background colour
• 24 bit YCbCr colour.
– Supports for mono, stereo, intensity stereo and dual
channel mode
2000 Jan 31
3
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
In addition to the previous listed features, the second
graphics plane sustains:
Graphics features
2 nearly identical graphics planes: the first graphics plane
commonly called the background plane and the second
graphics plane commonly called foreground plane.
The following features apply for both planes.
• Teletext insertion with automatic teletext data retrieving
from the external SDRAM.
Data manipulation unit
• Graphics is presented in boxes independent of video
format
• Powerful 3D block move with different patterns for
source and destination area
• Boxes can be up to full screen allowing double buffer
display mechanism
• Dedicated events for video synchronization
• Two independent data paths with RGB 4 : 4 : 4 and
YCbCr 4 : 2 : 2 formats available with independent
mixing
• Scaling, format conversion and bit manipulation from a
chained list of instructions.
• RGB path transparent to YCbCr format
Cursor
• Conversion matrices available to allow any format on
any different data path (RGB or YCbCr)
• Size of 1024 pixels
• Programmable shape (8 × 128, 16 × 64, 32 × 32,
64 × 16 and 128 × 8)
• Screen arrangement of boxes is determined by display
list mechanism which allows for multiple boxes,
background loading, fast switching, scrolling,
overlapping and fading of regions
• 16 colours available with a 4 level transparency mixing
with video and graphics
• Cursor colours obtained via two 16 entry CLUTs with
YCbCrT at 6, 4, 4 respectively 2 bits and RGBT at 4, 4, 4
respectively 4 bits (or 4, 5, 3, respectively 4 bits)
• Real-time anti-flickering performed in hardware;
programmable hardware available for off-line
anti-flickering
• Hard edged or soft edged wiping of regions available
• Cursor can be moved freely across the screen without
overlapping restrictions.
• Support of 2, 4, 8, 16 bit/pixel in fixed bit maps format or
coded in accordance to the DVB variable/run length
standard for region based graphics
Digital output
• Programmable selection for the mixed graphics planes
with video for the CVBS and RGB outputs
• Chrominance down-sampling filter switched per region
• Display colours are obtained via colour look up tables or
directly from bitmap; CLUT output can be YCbCrT at
8-bit for each signal component thus enabling 16 M
different colours and 6-bit for T which gives 64 mixing
levels with video; CLUT output can also be RGBT with
same resolutions; non linear processing available by
means of LUTs
• Digital video input/output interface on 8 bit,
27 MHz (CbYCrY multiplexed bus), at a CCIR-656
format.
Analog output
• Analog video output interface on both the RGB and
Y/C/CVBS formats available simultaneously
• Map table mechanism to specify a sub set of entries if
the CLUT is larger than required by the coded bit
pattern; supported map tables are 16 to 256, 4 to 256
and 4 to 16
• PAL/NTSC/SECAM encoding (SAA7221HS only)
• Two DACs for CVBS, Y and C, CVBS running at
27 MHz 10-bit resolution
• Up to 4 graphics boxes may overlap vertically even
inside one graphics layer thanks to the use of flexible
chained descriptors
• Three DACs for R (Y), G (Cb) and B (Cr) running at
27 MHz; 9-bit resolution connected to a 10-bit input DAC
• Graphics mechanism can be used for signal generation
in the vertical blanking interval; useful for teletext, wide
screen signalling, closed caption etc.
• Macrovision 7.01 and 6.1 encoding capability on
Y or CVBS and C or CVBS (SAA7216HS only).
2000 Jan 31
• Closed captioning and teletext encoding on CVBS
4
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
APPLICATIONS
GENERAL DESCRIPTION
The SAA7215 integrated MPEG AVGD decoder is aimed
at being used in MPEG digital TV applications. This
decoder is primarily designed to be connected to a
SAA7214 transport stream descrambler/demultiplexer/
microcontroller by means of glueless interfaces even
though connections to other market demultiplexers and/or
microcontrollers are possible. Compatibility is also
targeted with the SAA7219 and with the successor of the
T-MIPS family.
The SAA7215HS, SAA7216HS, SAA7221H is a MPEG-2
source decoder which combines audio decoding and video
decoding. Additionally to these basic MPEG functions it
also provides means for enhanced graphics, background
display and/or on-screen display as well as encoding of
output video. Due to an optimized architecture for audio
and video decoding, maximum capacity in external
memory and processing power from the external CPU is
available for graphics support.
The SAA7215 can be used in any system where high-end
graphics are needed (associated SDRAM can be
extended to 32-Mbit) as well as in low cost systems (all
functions can be enabled with only 16-Mbit of associated
SDRAM).
Possible options are indicated in Table 1.
Table 1
Possible options
TYPE NUMBER
MACROVISION
SECAM
SAA7215HS/C2
no
no
SAA7216HS/C1
yes
no
SAA7221HS/C1
no
yes
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
functional supply voltage range
3.0
3.3
3.6
V
IDD
total supply current; VDD = 3.3 V
−
tbf
−
mA
CLK
device clock input frequency (2 solutions are possible)
−30 ppm
+27
+30 ppm
MHz
−30 ppm
+40.5
+30 ppm
MHz
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7215HS/C2
SAA7216HS/C1
SQFP208
DESCRIPTION
plastic shrink quad flat package; 208 leads (lead length 1.3 mm);
body 28 × 28 × 3.4 mm
SAA7221HS/C1
2000 Jan 31
5
VERSION
SOT316-1
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
BLOCK DIAGRAMS
16-Mbit SDRAM
(compulsory)
handbook, full pagewidth
16-Mbit SDRAM
(optional)
MEMORY INTERFACE 1
AUDIO/VIDEO
INTERFACE
data
SYSTEM TIME
BASE UNIT
DATA MANIPULATION
UNIT
data
MPEG
data
MEMORY INTERFACE 2
VIDEO INPUT BUFFER
& SYNCHRONIZATION
DIGITAL ENCODER
analog
video
DIGITAL VIDEO
SYNCHRONIZATION
digital
video
VIDEO DECODER
CURSOR UNIT
AUDIO INPUT BUFFER
& SYNCHRONIZATION
audio
DACs
GRAPHICS
UNIT 1
CLOCK GENERATION
control
CLK
GRAPHICS
UNIT 2
AUDIO DECODER
DISPLAY UNIT
JTAG
CPU
HOST INTERFACE
FCE107
Fig.1 Block diagram.
2000 Jan 31
6
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
handbook, full pagewidth
SAA7215; SAA7216; SAA7221
16-Mbit SDRAM
MEMORY INTERFACE 1
AUDIO/VIDEO
INTERFACE
SYSTEM TIME
BASE UNIT
DATA MANIPULATION
UNIT
data
MPEG
data
MEMORY INTERFACE 2
VIDEO INPUT BUFFER
& SYNCHRONIZATION
DIGITAL ENCODER
analog
video
DIGITAL VIDEO
SYNCHRONIZATION
digital
video
VIDEO DECODER
CURSOR UNIT
AUDIO INPUT BUFFER
& SYNCHRONIZATION
audio
DACs
GRAPHICS
UNIT 1
CLOCK GENERATION
control
CLK
GRAPHICS
UNIT 2
AUDIO DECODER
DISPLAY UNIT
JTAG
CPU
HOST INTERFACE
FCE108
Fig.2 Block diagram with preferred use in 16-Mbit configuration.
2000 Jan 31
7
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
handbook, full pagewidth
16-Mbit SDRAM
(MPEG)
16-Mbit SDRAM
(Graphics)
MEMORY INTERFACE 1
AUDIO/VIDEO
INTERFACE
data
SYSTEM TIME
BASE UNIT
DATA MANIPULATION
UNIT
data
MPEG
data
MEMORY INTERFACE 2
VIDEO INPUT BUFFER
& SYNCHRONIZATION
DIGITAL ENCODER
analog
video
DIGITAL VIDEO
SYNCHRONIZATION
digital
video
VIDEO DECODER
CURSOR UNIT
AUDIO INPUT BUFFER
& SYNCHRONIZATION
audio
DACs
GRAPHICS
UNIT 1
CLOCK GENERATION
control
CLK
GRAPHICS
UNIT 2
AUDIO DECODER
DISPLAY UNIT
JTAG
CPU
HOST INTERFACE
FCE109
Fig.3 Block diagram with preferred use in 32-Mbit configuration.
2000 Jan 31
8
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PINNING
Pinning table (listed numerically)
PIN
TYPE(1)
VSS
1
S
DATA(4)
2
I/O
CPU data input or output (bit 4); note 2
DATA(5)
3
I/O
CPU data input or output (bit 5); note 2
DATA(6
4
I/O
CPU data input or output (bit 6); note 2
DATA(7)
5
I/O
CPU data input or output (bit 7); note 2
DATA(8)
6
I/O
CPU data input or output (bit 8); note 2
DATA(9)
7
I/O
CPU data input or output (bit 9); note 2
VDD
8
S
DATA(10)
9
I/O
CPU data input or output (bit 10); note 2
DATA(11)
10
I/O
CPU data input or output (bit 11); note 2
DATA(12)
11
I/O
CPU data input or output (bit 12); note 2
DATA(13)
12
I/O
CPU data input or output (bit 13); note 2
DATA(14)
13
I/O
CPU data input or output (bit 14); note 2
DATA(15)
14
I/O
CPU data input or output (bit 15); note 2
VSS
15
S
ground for pad ring
SDRAM_ADDR1(3)
16
O
SDRAM address 1 output (bit 3)
SDRAM_ADDR1(2)
17
O
SDRAM address 1 output (bit 2)
SDRAM_ADDR1(4)
18
O
SDRAM address 1 output (bit 4)
SDRAM_ADDR1(1)
19
O
SDRAM address 1 output (bit 1)
SDRAM_ADDR1(5)
20
O
SDRAM address 1 output (bit 5)
SDRAM_ADDR1(0)
21
O
SDRAM address 1 output (bit 0)
VDD
22
S
supply voltage for pad ring
SDRAM_ADDR1(6)
23
O
SDRAM address 1 output (bit 6)
SDRAM_ADDR1(10)
24
O
SDRAM address 1 output (bit 10)
SDRAM_ADDR1(7)
25
O
SDRAM address 1 output (bit 7)
VSS(CO)
26
S
ground for core logic
VDD(CO)
27
S
supply voltage for digital core logic
SDRAM_ADDR1(11)
28
O
SDRAM address 1 output (bit 11)
SDRAM_ADDR1(9)
29
O
SDRAM address 1 output (bit 9)
SDRAM_ADDR1(8)
30
O
SDRAM address 1 output (bit 8)
VSS
31
S
ground for pad ring
SDRAM_UDQ1
32
O
SDRAM write mask 1 output
SDRAM_RAS1
33
O
SDRAM row address strobe 1 output
SDRAM_CAS1
34
O
SDRAM column address 1 output
SDRAM_WE1
35
O
SDRAM write enable 1 output
VDD
36
S
supply voltage for pad ring
SDRAM_DATA1(8)
37
I/O
SDRAM data 1 input or output (bit 8)
SDRAM_DATA1(7)
38
I/O
SDRAM data 1 input or output (bit 7)
SYMBOL
2000 Jan 31
DESCRIPTION
ground for pad ring
supply voltage for pad ring
9
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN
TYPE(1)
39
I/O
SDRAM data 1 input or output (bit 9)
SDRAM_DATA1(6)
40
I/O
SDRAM data 1 input or output (bit 6)
SDRAM_DATA1(10)
41
I/O
SDRAM data 1 input or output (bit 10)
SDRAM_DATA11(5)
42
I/O
SDRAM data 1 input or output (bit 5)
VSS
43
S
SDRAM_DATA1(11)
44
I/O
SDRAM data 1 input or output (bit 11)
SDRAM_DATA1(4)
45
I/O
SDRAM data 1 input or output (bit 4)
SDRAM_DATA1(12)
46
I/O
SDRAM data 1 input or output (bit 12)
SDRAM_DATA1(3)
47
I/O
SDRAM data 1 input or output (bit 3)
SDRAM_DATA1(13)
48
I/O
SDRAM data 1 input or output (bit 13)
SDRAM_DATA1(2)
49
I/O
SDRAM data 1 input or output (bit 2)
VDD
50
S
SDRAM_DATA1(14)
51
I/O
SDRAM data 1 input or output (bit 14)
SDRAM_DATA1(1)
52
I/O
SDRAM data 1 input or output (bit 1)
SDRAM_DATA1(15)
53
I/O
SDRAM data 1 input or output (bit 15)
SDRAM_DATA1(0)
54
I/O
SDRAM data 1 input or output (bit 0)
READ_OUT1
55
O
read command 1 output
SYMBOL
SDRAM_DATA1(9)
DESCRIPTION
ground for pad ring
supply voltage for pad ring
READ_IN1
56
I
read command 1 input
VSS
57
S
ground for pad ring
CP81MEXT
58
I
81 MHz SDRAM clock memory input
CP81M
59
O
81 MHz SDRAM clock return path output
VDD
60
S
supply voltage for pad ring
READ_IN2
61
I
read command 2 input
READ_OUT2
62
O
read command 2 output
SDRAM_DATA2(0)
63
I/O
SDRAM data 2 input or output (bit 0)
SDRAM_DATA2(15)
64
I/O
SDRAM data 2 input or output (bit 15)
SDRAM_DATA2(1)
65
I/O
SDRAM data 2 input or output (bit 1)
SDRAM_DATA2(14)
66
I/O
VSS
67
S
SDRAM_DATA2(2)
68
I/O
SDRAM data 2 input or output (bit 2)
SDRAM_DATA2(13)
69
I/O
SDRAM data 2 input or output (bit 13)
SDRAM_DATA2(3)
70
I/O
SDRAM data 2 input or output (bit 3)
SDRAM_DATA2(12)
71
I/O
SDRAM data 2 input or output (bit 12)
SDRAM_DATA2(4)
72
I/O
SDRAM data 2 input or output (bit 4)
SDRAM_DATA2(11)
73
I/O
SDRAM data 2 input or output (bit 11)
VDD
74
S
SDRAM_DATA2(5)
75
I/O
SDRAM data 2 input or output (bit 5)
SDRAM_DATA2(10)
76
I/O
SDRAM data 2 input or output (bit 10)
SDRAM_DATA2(6)
77
I/O
SDRAM data 2 input or output (bit 6)
VSS(CO)
78
S
ground for core logic
VDD(CO)
79
S
supply voltage for digital core logic
2000 Jan 31
SDRAM data 2 input or output (bit 14)
ground for pad ring
supply voltage for pad ring
10
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN
TYPE(1)
SDRAM_DATA2(9)
80
I/O
SDRAM data 2 input or output (bit 9)
SDRAM_DATA2(7)
81
I/O
SDRAM data 2 input or output (bit 7)
SDRAM_DATA2(8)
82
I/O
SDRAM data 2 input or output (bit 8)
VSS
83
S
SYMBOL
DESCRIPTION
ground for pad ring
SDRAM_WE2
84
O
SDRAM write enable 2 output
SDRAM_CAS2
85
O
SDRAM column address 2 output
SDRAM_RAS2
86
O
SDRAM row address strobe 2 output
SDRAM_UDQ2(0)
87
O
SDRAM write mask 2 (0) output
SDRAM_UDQ2(1)
88
O
SDRAM write mask 2 (1) output
VDD
89
S
supply voltage for pad ring
SDRAM_ADDR2(8)
90
O
SDRAM address 2 output (bit 8)
SDRAM_ADDR2(9)
91
O
SDRAM address 2 output (bit 9)
SDRAM_ADDR2(11)
92
O
SDRAM address 2 output (bit 11)
SDRAM_ADDR2(7)
93
O
SDRAM address 2 output (bit 7)
SDRAM_ADDR2(10)
94
O
SDRAM address 2 output (bit 10)
SDRAM_ADDR2(6)
95
O
SDRAM address 2 output (bit 6)
VSS
96
S
ground for pad ring
SDRAM_ADDR2(0)
97
O
SDRAM address 2 output (bit 0)
SDRAM_ADDR2(5)
98
O
SDRAM address 2 output (bit 5)
SDRAM_ADDR2(1)
99
O
SDRAM address 2 output (bit 1)
SDRAM_ADDR2(4)
100
O
SDRAM address 2 output (bit 4)
SDRAM_ADDR2(2)
101
O
SDRAM address 2 output (bit 2)
SDRAM_ADDR2(3)
102
O
SDRAM address 2 output (bit 3)
VDD
103
S
supply voltage for pad ring
TDI
104
I
TDO
105
O/Z
TMS
106
I
boundary scan test mode select input; note 2
TRST
107
I
boundary scan test data input; note 2
TCK
108
I
boundary scan test clock input
VDD(AN)
109
S
3.3 V supply for analog blocks(PLL)
boundary scan test data input; note 2
boundary scan test data output; note 2
IDUMP2
110
−
analog sink 2
B
111
−
analog video (blue)
G
112
−
analog video (green)
AVDD3
113
S
analog supply 3
R
114
−
analog video (red)
AVDD2
115
S
analog supply 2
Y/CVBS
116
−
analog luminance/analog composite video
C/CVBS
117
−
analog chrominance/analog composite video
IDUMP1
118
−
analog sink 1
AVSS
119
S
analog supply ground
RSET
120
−
analog reference
2000 Jan 31
11
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN
TYPE(1)
AVDD1
121
S
analog supply 1
VSS
122
S
ground for pad ring
GRPH
123
O/Z
indicator for graphics information output; note 2
VS
124
I/O
vertical synchronization input or output; note 2
HS
125
I/O
horizontal synchronization input or output; note 2
CP27
126
O
27 MHz video presentation clock output; note 2
VDD
127
S
supply voltage for pad ring
YUV(0)
128
I/O
VSS(CO)
129
S
ground for core logic
VDD(CO)
130
S
supply voltage for digital core logic
YUV(1)
131
I/O
YUV video input or output (bit 1); at 27 MHz; note 2
YUV(2)
132
I/O
YUV video input or output (bit 2); at 27 MHz; note 2
YUV(3)
133
I/O
YUV video input or output (bit 3); at 27 MHz; note 2
YUV(4)
134
I/O
YUV video input or output (bit 4); at 27 MHz; note 2
YUV(5)
135
I/O
YUV video input or output (bit 5); at 27 MHz; note 2
YUV(6)
136
I/O
YUV video input or output (bit 6); at 27 MHz; note 2
YUV(7)
137
I/O
YUV video input or output (bit 7); at 27 MHz; note 2
VSS
138
S
SPDIF
139
O/Z
digital audio output; note 2
WS
140
O/Z
word select output; note 2
SYMBOL
DESCRIPTION
YUV video input or output (bit 0);at 27 MHz; note 2
ground for pad ring
WB
141
O/Z
word begin output; note 2
SD
142
O/Z
serial audio data output; note 2
SCK
143
O/Z
serial audio clock output; note 2
FSCLK
144
I/O
256 or 384 x fs clock input or output;
RESET
145
I
hard reset input; note 2
TTX
146
I
teletext data input; note 2
TTXRQ/CPU_SEL(1)
147
I/O
teletext data request or CPU data interface selection (1); note 2; note 3
VDD
148
S
IRQ(1)
149
O/Z
individually maskable interrupt (1) output; note 2
IRQ(0)
150
O/Z
individually maskable interrupt (0) output; note 2
V_REQ
151
O/Z
video data request output; note 2
A_REQ
152
O/Z
audio data request output; note 2
AUDDEN
153
I
byte synchronisation of serial audio input A_DATA; note 2
A_DATA
154
I
MPEG audio stream serial port input; note 2
AV_DATA(0)
155
I
MPEG stream port input (bit 0); note 2
AV_DATA(1)
156
I
MPEG stream port input (bit 1); note 2
AV_DATA(2)
157
I
MPEG stream port input (bit 2); note 2
AV_DATA(3)
158
I
MPEG stream port input (bit 3); note 2
AV_DATA(4)
159
I
MPEG stream port input (bit 4); note 2
AV_DATA(5)
160
I
MPEG stream port input (bit 5); note 2
AV_DATA(6)
161
I
MPEG stream port input (bit 6); note 2
2000 Jan 31
supply voltage for pad ring
12
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PIN
TYPE(1)
AV_DATA(7)
162
I
MPEG stream port input (bit 7); note 2
ERROR
163
I
flag for bitstream error; note 2
A_STROBE
164
I
audio data strobe for AV_DATA and A_DATA inputs; note 2
V_STROBE
165
I
video data strobe for AV_DATA and A_DATA inputs; note 2
VSS (gate input)
166
S
ground for pad ring
CPU_SEL(0)
167
I
CPU data interface selection (0) input; note 2; note 3
CLK
168
I
27 or 40.5 MHz clock input; note 2
VSS
169
S
ground for pad ring
SIZ(1)
170
I
size of data on bus DATA (1) input; note 2
SIZ(0)
171
I
size of data on bus DATA (0) input; note 2
ADDRESS(20)
172
I
CPU address input (bit 20); note 2
ADDRESS(19)
173
I
CPU address input (bit 19); note 2
ADDRESS(18)
174
I
CPU address input (bit 18); note 2
ADDRESS(17)
175
I
CPU address input (bit 17); note 2
ADDRESS(16)
176
I
CPU address input (bit 16); note 2
ADDRESS(15)
177
I
CPU address input (bit 15); note 2
ADDRESS(14)
178
I
CPU address input (bit 14); note 2
ADDRESS(13)
179
I
CPU address input (bit 13); note 2
ADDRESS(12)
180
I
CPU address input (bit 12); note 2
ADDRESS(11)
181
I
CPU address input (bit 11); note 2
VSS(CO)
182
S
ground for core logic
VDD(CO)
183
S
supply voltage for digital core logic
VDD
184
S
supply voltage for pad ring
ADDRESS(10)
185
I
CPU address input (bit 10); note 2
ADDRESS(9)
186
I
CPU address input (bit 9); note 2
ADDRESS(8)
187
I
CPU address input (bit 8); note 2
ADDRESS(7)
188
I
CPU address input (bit 7); note 2
ADDRESS(6)
189
I
CPU address input (bit 6); note 2
ADDRESS(5)
190
I
CPU address input (bit 5); note 2
ADDRESS(4)
191
I
CPU address input (bit 4); note 2
ADDRESS(3)
192
I
CPU address input (bit 3); note 2
ADDRESS(2)
193
I
CPU address input (bit 2); note 2
ADDRESS(1)
194
I
CPU address input (bit 1); note 2
ADDRESS(0)
195
I
CPU address input (bit 0); note 2
R/W
196
I
read or write input; note 2
DMA_RDY
197
O/Z
DMA ready output; note 2
DMA_DONE
198
I
DMA_REQ
199
I/O
DMA_ACK
200
I
DMA acknowledge input; note 2
CSRG
201
I
chip select for control register access input; note 2
CSSD/ADDRESS(21)
202
I
chip select for SDRAM access or CPU address (bit 21) input; note 2
SYMBOL
2000 Jan 31
DESCRIPTION
DMA end input; note 2
DMA request input or output; note 2
13
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SYMBOL
DATACK
PIN
TYPE(1)
203
O/Z
SAA7215; SAA7216; SAA7221
DESCRIPTION
data acknowledge output; note 2
DS/TS
204
I
DATA(0)
205
I/O
CPU data input or output (bit 0); note 2
data strobe or transfer start input; note 2
DATA(1)
206
I/O
CPU data input or output (bit 1); note 2
DATA(2)
207
I/O
CPU data input or output (bit 2); note 2
DATA(3)
208
I/O
CPU data input or output (bit 3); note 2
Notes
1. Pin type abbreviations: I = Input, O = Output, I/O = Input or Output, O/Z = high impedance Output and
S = Supply voltage.
2. 5 V tolerant outputs swing between VSS and VDD. 5 V tolerant inputs can receive signals swinging between VSS and
3.3 V or VSS and 5 V.
3. Signal CPU_SEL(1) is used only after a global hardware reset is applied on external input line RESET for determining
the type of the microcontroller connected to SAA7215; SAA7216; SAA7221 and therefore apply the proper
communication protocol. This microcontroller type must be given by means of weak pull-up or pull-down externally
connected to CPU_SEL(1). During normal operation, the pin TTXRQ/CPU_SEL(1) is used for implementing the
Teletext Data Request protocol and must not be disturbed by the microcontroller type setting.
2000 Jan 31
14
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
handbook, halfpage
157
208
Pin configuration
156
1
SAA7215HS
SAA7216HS
SAA7221HS
104
105
53
52
Fig.4 Pin configuration.
2000 Jan 31
15
FCE351
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
Pinning table (listed by function)
PIN
SYMBOL
TYPE(1)
DRIVE
VOLTAGE
ACTIVITY
166
VSS (gate input)
S
−
0V
−
168
CLK
I
−
5.0 V tolerant
rising edge
145
RESET
I
−
5.0 V tolerant
low level
162
AV_DATA(7)
I
−
5.0 V tolerant
direct level
161
AV_DATA(6)
I
−
5.0 V tolerant
direct level
160
AV_DATA(5)
I
−
5.0 V tolerant
direct level
159
AV_DATA(4)
I
−
5.0 V tolerant
direct level
158
AV_DATA(3)
I
−
5.0 V tolerant
direct level
157
AV_DATA(2)
I
−
5.0 V tolerant
direct level
156
AV_DATA(1)
I
−
5.0 V tolerant
direct level
155
AV_DATA(0)
I
−
5.0 V tolerant
direct level
154
A_DATA
I
−
5.0 V tolerant
low level
153
AUDDEN
I
−
5.0 V tolerant
high level
164
A_STROBE
I
−
5.0 V tolerant
program level
165
V_STROBE
I
−
5.0 V tolerant
program level
152
A_REQ
O/Z
3 mA
5.0 V tolerant
program level
151
V_REQ
O/Z
163
ERROR
I
142
SD
143
140
3 mA
5.0 V tolerant
program level
−
5.0 V tolerant
program level
O/Z
3 mA
5.0 V tolerant
direct level
SCK
O/Z
3 mA
5.0 V tolerant
edge
WS
O/Z
3 mA
5.0 V tolerant
direct level
141
WB
O/Z
3 mA
5.0 V tolerant
direct level
139
SPDIF
O/Z
3 mA
5.0 V tolerant
direct level
144
FSCLK
I/O
3 mA
5.0 V tolerant
edge
126
CP27
O
3 mA
5.0 V tolerant
rising edge
137
YUV(7)
I/O
3 mA
5.0 V tolerant
direct level
136
YUV(6)
I/O
3 mA
5.0 V tolerant
direct level
135
YUV(5)
I/O
3 mA
5.0 V tolerant
direct level
134
YUV(4)
I/O
3 mA
5.0 V tolerant
direct level
133
YUV(3)
I/O
3 mA
5.0 V tolerant
direct level
132
YUV(2)
I/O
3 mA
5.0 V tolerant
direct level
131
YUV(1)
I/O
3 mA
5.0 V tolerant
direct level
128
YUV(0)
I/O
3 mA
5.0 V tolerant
direct level
125
HS
I/O
3 mA
5.0 V tolerant
program level
124
VS
I/O
3 mA
5.0 V tolerant
program level
123
GRPH
O/Z
3 mA
5.0 V tolerant
high level
114
R/CVBS
−
−
−
analog
112
G
−
−
−
analog
111
B
−
−
−
analog
116
Y/CVBS
−
−
−
analog
2000 Jan 31
16
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PIN
SYMBOL
SAA7215; SAA7216; SAA7221
TYPE(1)
VOLTAGE
ACTIVITY
−
−
analog
I/O
2 mA
3.3 V
direct level
I/O
2 mA
3.3 V
direct level
SDRAM_DATA1(13)
I/O
2 mA
3.3 V
direct level
46
SDRAM_DATA1(12)
I/O
2 mA
3.3 V
direct level
44
SDRAM_DATA1(11)
I/O
2 mA
3.3 V
direct level
41
SDRAM_DATA1(10)
I/O
2 mA
3.3 V
direct level
39
SDRAM_DATA1(9)
I/O
2 mA
3.3 V
direct level
37
SDRAM_DATA1(8)
I/O
2 mA
3.3 V
direct level
38
SDRAM_DATA1(7)
I/O
2 mA
3.3 V
direct level
40
SDRAM_DATA1(6)
I/O
2 mA
3.3 V
direct level
42
SDRAM_DATA1(5)
I/O
2 mA
3.3 V
direct level
45
SDRAM_DATA1(4)
I/O
2 mA
3.3 V
direct level
47
SDRAM_DATA1(3)
I/O
2 mA
3.3 V
direct level
49
SDRAM_DATA1(2)
I/O
2 mA
3.3 V
direct level
52
SDRAM_DATA1(1)
I/O
2 mA
3.3 V
direct level
54
SDRAM_DATA1(0)
I/O
2 mA
3.3 V
direct level
28
SDRAM_ADDR1(11)
O
2 mA
3.3 V
direct level
24
SDRAM_ADDR1(10)
O
2 mA
3.3 V
direct level
29
SDRAM_ADDR1(9)
O
2 mA
3.3 V
direct level
30
SDRAM_ADDR1(8)
O
2 mA
3.3 V
direct level
25
SDRAM_ADDR1(7)
O
2 mA
3.3 V
direct level
23
SDRAM_ADDR1(6)
O
2 mA
3.3 V
direct level
20
SDRAM_ADDR1(5)
O
2 mA
3.3 V
direct level
18
SDRAM_ADDR1(4)
O
2 mA
3.3 V
direct level
16
SDRAM_ADDR1(3)
O
2 mA
3.3 V
direct level
17
SDRAM_ADDR1(2)
O
2 mA
3.3 V
direct level
19
SDRAM_ADDR1(1)
O
2 mA
3.3 V
direct level
21
SDRAM_ADDR1(0)
O
2 mA
3.3 V
direct level
33
SDRAM_RAS1
O
2 mA
3.3 V
low level
34
SDRAM_CAS1
O
2 mA
3.3 V
low level
35
SDRAM_WE1
O
2 mA
3.3 V
low level
32
SDRAM_UDQ1
O
2 mA
3.3 V
direct level
59
CP81M
O
8 mA
3.3 V
edge
58
CP81MEXT
I
−
3.3 V
edge
55
READ_OUT1
O
2 mA
3.3 V
low level
56
READ_IN1
I
−
3.3 V
low level
64
SDRAM_DATA2(15)
I/O
2 mA
3.3 V
direct level
66
SDRAM_DATA2(14)
I/O
2 mA
3.3 V
direct level
69
SDRAM_DATA2(13)
I/O
2 mA
3.3 V
direct level
71
SDRAM_DATA2(12)
I/O
2 mA
3.3 V
direct level
117
C/CVBS
53
SDRAM_DATA1(15)
51
SDRAM_DATA1(14)
48
2000 Jan 31
−
DRIVE
17
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PIN
SYMBOL
SAA7215; SAA7216; SAA7221
TYPE(1)
76
SDRAM_DATA2(10)
I/O
2 mA
3.3 V
direct level
80
SDRAM_DATA2(9)
I/O
2 mA
3.3 V
direct level
82
SDRAM_DATA2(8)
I/O
2 mA
3.3 V
direct level
81
SDRAM_DATA2(7)
I/O
2 mA
3.3 V
direct level
77
SDRAM_DATA2(6)
I/O
2 mA
3.3 V
direct level
75
SDRAM_DATA2(5)
I/O
2 mA
3.3 V
direct level
72
SDRAM_DATA2(4)
I/O
2 mA
3.3 V
direct level
70
SDRAM_DATA2(3)
I/O
2 mA
3.3 V
direct level
68
SDRAM_DATA2(2)
I/O
2 mA
3.3 V
direct level
65
SDRAM_DATA2(1)
I/O
2 mA
3.3 V
direct level
63
SDRAM_DATA2(0)
I/O
2 mA
3.3 V
direct level
92
SDRAM_ADDR2(11)
O
2 mA
3.3 V
direct level
94
SDRAM_ADDR2(10)
O
2 mA
3.3 V
direct level
91
SDRAM_ADDR2(9)
O
2 mA
3.3 V
direct level
90
SDRAM_ADDR2(8)
O
2 mA
3.3 V
direct level
93
SDRAM_ADDR2(7)
O
2 mA
3.3 V
direct level
95
SDRAM_ADDR2(6)
O
2 mA
3.3 V
direct level
98
SDRAM_ADDR2(5)
O
2 mA
3.3 V
direct level
100
SDRAM_ADDR2(4)
O
2 mA
3.3 V
direct level
102
SDRAM_ADDR2(3)
O
2 mA
3.3 V
direct level
101
SDRAM_ADDR2(2)
O
2 mA
3.3 V
direct level
99
SDRAM_ADDR2(1)
O
2 mA
3.3 V
direct level
97
SDRAM_ADDR2(0)
O
2 mA
3.3 V
direct level
86
SDRAM_RAS2
O
2 mA
3.3 V
low level
85
SDRAM_CAS2
O
2 mA
3.3 V
low level
84
SDRAM_WE2
O
2 mA
3.3 V
low level
88
SDRAM_UDQ2(1)
O
2 mA
3.3 V
direct level
87
SDRAM_UDQ2(0)
O
2 mA
3.3 V
direct level
62
READ_OUT2
O
2 mA
3.3 V
low level
61
READ_IN2
I
−
3.3 V
low level
147
TTXRQ/CPU_SEL(1)
3 mA
5.0 V tolerant
direct level
167
CPU_SEL(0)
I
−
5.0 V tolerant
level
146
TTX
I
−
5.0 V tolerant
direct level
14
DATA(15)
I/O
6 mA
5.0 V tolerant
direct level
13
DATA(14)
I/O
6 mA
5.0 V tolerant
direct level
12
DATA(13)
I/O
6 mA
5.0 V tolerant
direct level
11
DATA(12)
I/O
6 mA
5.0 V tolerant
direct level
10
DATA(11)
I/O
6 mA
5.0 V tolerant
direct level
9
DATA(10)
I/O
6 mA
5.0 V tolerant
direct level
7
DATA(9)
I/O
6 mA
5.0 V tolerant
direct level
18
3.3 V
ACTIVITY
SDRAM_DATA2(11)
I/O
2 mA
VOLTAGE
73
2000 Jan 31
I/O
DRIVE
direct level
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PIN
SYMBOL
SAA7215; SAA7216; SAA7221
TYPE(1)
DRIVE
VOLTAGE
ACTIVITY
6
DATA(8)
I/O
6 mA
5.0 V tolerant
direct level
5
DATA(7)
I/O
6 mA
5.0 V tolerant
direct level
4
DATA(6)
I/O
6 mA
5.0 V tolerant
direct level
3
DATA(5)
I/O
6 mA
5.0 V tolerant
direct level
2
DATA(4)
I/O
6 mA
5.0 V tolerant
direct level
208
DATA(3)
I/O
6 mA
5.0 V tolerant
direct level
207
DATA(2)
I/O
6 mA
5.0 V tolerant
direct level
206
DATA(1)
I/O
6 mA
5.0 V tolerant
direct level
205
DATA(0)
I/O
6 mA
5.0 V tolerant
direct level
172
ADDRESS(20)
I
−
5.0 V tolerant
direct level
173
ADDRESS(19)
I
−
5.0 V tolerant
direct level
174
ADDRESS(18)
I
−
5.0 V tolerant
direct level
175
ADDRESS(17)
I
−
5.0 V tolerant
direct level
176
ADDRESS(16)
I
−
5.0 V tolerant
direct level
177
ADDRESS(15)
I
−
5.0 V tolerant
direct level
178
ADDRESS(14)
I
−
5.0 V tolerant
direct level
179
ADDRESS(13)
I
−
5.0 V tolerant
direct level
180
ADDRESS(12)
I
−
5.0 V tolerant
direct level
181
ADDRESS(11)
I
−
5.0 V tolerant
direct level
185
ADDRESS(10)
I
−
5.0 V tolerant
direct level
186
ADDRESS(9)
I
−
5.0 V tolerant
direct level
187
ADDRESS(8)
I
−
5.0 V tolerant
direct level
188
ADDRESS(7)
I
−
5.0 V tolerant
direct level
189
ADDRESS(6)
I
−
5.0 V tolerant
direct level
190
ADDRESS(5)
I
−
5.0 V tolerant
direct level
191
ADDRESS(4)
I
−
5.0 V tolerant
direct level
192
ADDRESS(3)
I
−
5.0 V tolerant
direct level
193
ADDRESS(2)
I
−
5.0 V tolerant
direct level
194
ADDRESS(1)
I
−
5.0 V tolerant
direct level
195
ADDRESS(0)
I
−
5.0 V tolerant
direct level
170
SIZ(1)
I
−
5.0 V tolerant
direct level
171
SIZ(0)
I
−
5.0 V tolerant
direct level
201
CSRG
I
−
5.0 V tolerant
low level
202
CSSD/ADDRESS(21)
I
−
5.0 V tolerant
low level
204
DS
I
−
5.0 V tolerant
low level
196
R/W
I
−
5.0 V tolerant
direct level
203
DTACK
O/Z
6 mA
5.0 V tolerant
low level
199
DMA_REQ
I/O
3 mA
5.0 V tolerant
program level
200
DMA_ACK
I
−
5.0 V tolerant
program level
197
DMA_RDY
O/Z
3 mA
5.0 V tolerant
program level
198
DMA_DONE
−
5.0 V tolerant
program level
2000 Jan 31
I
19
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PIN
SYMBOL
SAA7215; SAA7216; SAA7221
TYPE(1)
149
IRQ(1)
O/Z
150
IRQ(0)
O/Z
104
TDI
I
105
TDO
O/Z
106
TMS
108
TCK
107
DRIVE
3 mA
VOLTAGE
5.0 V tolerant
ACTIVITY
program level
3 mA
5.0 V tolerant
program level
−
5.0 V tolerant
direct level
3 mA
5.0 V tolerant
direct level
I
−
5.0 V tolerant
direct level
I
−
5.0 V tolerant
edge
TRST
I
−
5.0 V tolerant
low level
121
AVDD1
S
−
−
−
115
AVDD2
S
−
−
−
113
AVDD3
S
−
−
−
118
IDUMP1
−
−
−
−
110
IDUMP2
−
−
−
−
120
RSET
−
−
−
−
119
AVSS
S
−
−
−
27
VDD(CO)
S
−
3.3 V
−
79
VDD(CO)
S
−
3.3 V
−
130
VDD(CO)
S
−
3.3 V
−
183
VDD(CO)
S
−
3.3 V
−
8
VDD
S
−
3.3 V
−
22
VDD
S
−
3.3 V
−
36
VDD
S
−
3.3 V
−
50
VDD
S
−
3.3 V
−
60
VDD
S
−
3.3 V
−
74
VDD
S
−
3.3 V
−
89
VDD
S
−
3.3 V
−
103
VDD
S
−
3.3 V
−
127
VDD
S
−
3.3 V
−
148
VDD
S
−
3.3 V
−
184
VDD
S
−
3.3 V
−
109
VDD(AN)
S
−
3.3 V
−
26
VSS(CO)
S
−
0V
−
78
VSS(CO)
S
−
0V
−
129
VSS(CO)
S
−
0V
−
182
VSS(CO)
S
−
0V
−
1
VSS
S
−
0V
−
15
VSS
S
−
0V
−
31
VSS
S
−
0V
−
43
VSS
S
−
0V
−
57
VSS
S
−
0V
−
67
VSS
S
−
0V
−
83
VSS
S
−
0V
−
2000 Jan 31
20
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
PIN
SYMBOL
SAA7215; SAA7216; SAA7221
TYPE(1)
DRIVE
VOLTAGE
ACTIVITY
96
VSS
S
−
0V
−
122
VSS
S
−
0V
−
138
VSS
S
−
0V
−
169
VSS
S
−
0V
−
Notes
1. Pin type abbreviations: I = Input, O = Output, I/O = Input or Output, O/Z = high impedance Output and
S = Supply voltage.
2000 Jan 31
21
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
APPLICATION INFORMATION
handbook, full pagewidth
16-Mbit
SDRAM
(OPTIONAL)
4
5
12
16
ctrl
ctrl
addr
data
I2C
12
addr
UART PIO
16
data
16-Mbit
SDRAM
2
HS, VS
1
TS-in
(pktdata)
SAA7214
(T-MIPS)
AV data
8
Strobe
2
IRQ
2
SAA7215
SAA7216
SAA7221
MPEG-2AVGD
DECODER
ERROR
8
40.5 MHz
Extension bus
EPROM
DRAM
DS
R/W
CSSD
CSRG
21
addr
data
16
FLASH
FCE111
Fig.5 Set-top box example.
2000 Jan 31
22
CCIR-656
1
GRPH
2
Y/C/CVBS
3
6
13.5 MHz
CP27
RGB
Audio
DAC
DTACK
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
PACKAGE OUTLINE
SQFP208: plastic shrink quad flat package;
208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT316-1
c
y
X
A
156
157
105
104
ZE
e
E HE
A
A2
A1
(A 3)
wM
θ
Lp
bp
L
pin 1 index
208
detail X
53
52
1
ZD
wM
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
4.10
0.50
0.25
3.6
3.2
0.25
0.27
0.17
0.20
0.09
28.1
27.9
28.1
27.9
0.5
30.9
30.3
30.9
30.3
1.3
0.75
0.45
0.2
0.08
0.08
Z D (1) Z E (1)
θ
1.39
1.11
8
0o
1.39
1.11
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT316-1
2000 Jan 31
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-25
MS-029
23
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Jan 31
24
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3), SO, SOJ
suitable
suitable(2)
suitable
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Jan 31
25
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
NOTES
2000 Jan 31
26
Philips Semiconductors
Preliminary specification
Integrated MPEG AVGD decoders
SAA7215; SAA7216; SAA7221
NOTES
2000 Jan 31
27
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp28
Date of release: 2000
Jan 31
Document order number:
9397 750 05379