INTEGRATED CIRCUITS
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Family Specifications HEF, HEC
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Package Outlines/Information HEF, HEC
HEF4751V
LSI
Universal divider
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
To accommodate fixed or variable frequency offset, two
numbers are applied in parallel, one being subtracted from
the other to produce the internal programme.
The decade selection address is generated by an internal
programme counter which may run continuously or on
demand. Two or more universal dividers can be cascaded,
each extra U.D. (in slave mode) adds two decades to the
system. The combination retains the full programmability
and features of a single U.D. The U.D. provides a fast
output signal FF at output OFF, which can have a phase
jitter of ± 1 system input period, to allow fast frequency
locking. The slow output signal FS at output OFS, which is
jitter-free, is used for fine phase control at a lower speed.
DESCRIPTION
The HEF4751V is a universal divider (U.D.) intended for
use in high performance phase lock loop frequency
synthesizer systems. It consists of a chain of counters
operating in a programmable feedback mode.
Programmable feedback signals are generated for up to
three external (fast) ÷ 10/11 prescaler.
The system comprising one HEF4751V U.D. together with
prescalers is a fully programmable divider with a maximum
configuration of: 5 decimal stages, a programmable mode
M stage (1 ≤ M ≤ 16, non-decimal fraction channel
selection), and a mode H stage (H = 1 or 2, stage for half
channel offset).
Programming is performed in BCD code in a bit-parallel,
digit-serial format.
Fig.1 Pinning diagram.
HEF4751VP(N):
28-lead DIL; plastic (SOT117)
HEF4751VD(F):
28-lead DIL; ceramic (cerdip) (SOT135V)
HEF4751VT(D):
28-lead SO; plastic (SOT136A)
( ): Package Designator North America
SUPPLY VOLTAGE
RATING
RECOMMENDED OPERATING
−0,5 to + 18
4,5 to 12,5 V
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
Fig.2 Block diagram.
January 1995
3
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Philips Semiconductors
Universal divider
January 1995
4
Product specification
Fig.3 The HEF4751V U.D. used in a system with 3 (fast) prescalers.
HEF4751V
LSI
1 ≤ M ≤ 16; 1 ≤ H ≤ 2; n5 > 0; fi/fOFS = {(n5 ⋅ 104 + n4 ⋅ 103 + n3 ⋅ 102 + n2 ⋅ 10 + n1) M + n0} H + nh.
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
Fig.4 Timing diagram showing programme data inputs.
Allocation of data input
FETCH
PERIOD
Allocation of data input B3 to B0 during fetch period 6
B3
B2
C0b DIVISION RATIO
SI
L
L
1
H
2
INPUTS
A3
A2
A1
A0
B3 B2 B1
B0
0
n0A
n0B
bin
L
1
n1A
n1B
X
H
L
5
H
H
10/11
B1
B0
2
n2A
n2B
X
3
n3A
n3B
X
4
n4A
n4B
X
5
n5A
n5B
X
6
M
C0b
control
1⁄
2
channel
control
X
1⁄
2
CHANNEL CONFIGURATION
L
L
H=1
L
H
H = 2; nh = 0
H
H
H = 2; nh = 1
H
L
test state
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
January 1995
5
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
is programmed in fetch period 6 via data A inputs in
negative logic (except all HIGH is understood as: M = 16).
The counter C0 is a side steppable 10/11 counter
composed of an internal part C0b and an external part C0a.
C0b is configured via B3 and B2 to a division ratio of 1 or 2
or 5 or 10/11; C0a must have the complementary ratio
10/11 or 5/6 or 2/3 or 1 respectively. In the latter case
C0b comprises the whole C0 counter with internal
feedback, C0a is then not required.
PROGRAMME DATA INPUT (see also Figs 3 and 4)
The programming process is timed and controlled by input
PC and PE. When the programme enable (PE) input is
HIGH; the positive edges of the programme clock (PC)
signal step through the internal programme counter in a
sequence of 8 states. Seven states define fetch periods,
each indicated by a LOW signal at one of the
corresponding data address outputs (OD0 to OD6). These
data address signals may be used to address the external
programme source. The data fetched from the programme
source is applied to inputs A0 to A3 and B0 to B3. When PC
is LOW in a fetch period an internal load pulse is
generated, the data is valid during this time and has to be
stable. When PE is LOW, the programming cyclus is
interrupted on the first positive edge of PC. On the next
negative edge at input PC fetch period 6 is entered. Data
may enter asynchronously in fetch period 6.
The half channel counter C4 is enabled with B0 = HIGH
and disabled with B0 = LOW. With C4 enabled, a half
channel offset can be programmed with input B1 = HIGH,
and no offset with B1 = LOW.
FEEDBACK TO PRESCALERS (see also Figs 5 and 6)
The counters C1, C0, C−1 and C−2 are side-steppable
counters, i.e. its division ratio may be increased by one, by
applying a pulse to a control terminal for the duration of
one division cycle. Counter C2 has 10 states, which are
accessible as timing signals for the rate selectors RS1 to
RS4. A rate selector, programmed with n (n1 to n4 in the
U.D.) generates n of 10 basic timing periods an active
signal. Since n ≤ 9, 1 of 10 periods is always non-active. In
this period RS1 transfers the output of rate selector RS0,
which is timed by counter C3 and programmed with n0.
Similarly, RS0 transfers RSH output during one period of
C3. Rate selector RSH is timed by C4 and programmed
with nh. In one of the two states of C4, if enabled, or
always, if C4 is disabled, RSH transfers the LOW active
signal at input RI to RS0. If RI is not used it must be
connected to HIGH. The feedback output signals of RS1,
RS2 and RS3 are externally available as active LOW
signals at outputs OFB1, OFB2 and OFB3.
Ten blocks in the U.D. need programme input signals (see
Fig.2). Four of these (C0b, C3, C4 and RSH) are
concerned with the configuration of the U.D. and are
programmed in fetch period 6. The remaining blocks (RS0
to RS4 and C1) are programmed with number P,
consisting of six internal digits n0 to n5.
P = (n5 ⋅ 104 + n4 ⋅ 103 + n3 ⋅ 102 + n2 ⋅ 10 + n1) ⋅ M + n0
These digits are formed by a substractor from two external
numbers A and B and a borrow-in (bin).
P = A − B − bin or if this result is negative;
P = A − B − bin + M ⋅ 105.
The numbers A and B, each consisting of six four bit digits
n0A to n5A and n0B to n5B, are applied in fetch period 0 to 5
to the inputs A0 to A3 (data A) and B0 to B3 (data B) in
binary coded negative logic.
Output OFB1 is intended for the prescaler at the highest
frequency (if present), OFB2 for the next (if present) and
OFB3 for the lowest frequency prescaler (if present). A
prescaler needs a feedback signal, which is timed on one
of its own division cycles in a basic timing period. The
timing signal at OSY is LOW during the last U.D. input
period of a basic timing period and is suitable for timing of
the feedback for the last external prescaler. The
synchronization signal for a preceding prescaler is the
OR-function of the sync. input and sync. output of the
following prescaler (all sync. signals active LOW).
A = (n5A ⋅ 104 + n4A ⋅ 103 + n3A ⋅ 102 + n2A ⋅ 10 + n1A) ⋅ M
+ n0A.
B = (n5B ⋅ 104 + n4B ⋅ 103 + n3B ⋅ 102 + n2B ⋅ 10 + n1B) ⋅ M
+ n0B.
Borrow-in (bin) is applied via input SI in fetch period 0
(SI = HIGH: borrow, SI = LOW: no borrow).
Counter C1 is automatically programmed with the most
significant non-zero digit (nms) from the internal digits n5 to
n2 of number P. The counter chain C − 2 to C1 (see Fig.3)
is fully programmable by the use of pulse rate feedback.
Rate feedback is generated by the rate selectors RS4 to
RS0 and RSH, which are programmed with digits n4 to
n0 and nh respectively. In fetch period 6 the fractional
counter C3, half channel counter C4 and C0b are
programmed and configured via data B inputs. Counter C3
January 1995
6
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
Fig.5 Block diagram showing feedback to prescalers.
Fig.6 Timing diagram showing signals occurring in Fig.5.
January 1995
7
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
CASCADING OF U.D.s (see also Fig. 8)
OUTPUT (see also Fig.7)
A U.D. is programmed into the ‘slave’ mode by the
programme input data: n2A = 11, n2B = 10,
n3A = n4A = n3B = n4B = n5B = 0. A U.D. operating in the
slave mode performs the function of two extra
programmable stages C2’ and C3’ to a ‘master’ (not slave)
mode operating U.D. More slave U.D.s may be used,
every slave adding two lower significant digits to the
system.
The normal output of the U.D. is the slow output OFS,
which consists of evenly spaced LOW pulses. This output
is intended for accurate phase comparison. If a better
frequency acquisition time is required, the fast output OFF
can be used. The output frequency on OFF is a factor
M ⋅ H higher than the frequency on OFS. However, phase
jitter of maximum ± 1 system input period occurs at OFF,
since the division ratio of the counters preceding OFF are
varied by slow feedback pulse trains from rate selectors
following OFF.
Output OFB3 is converted to the borrow output of the
programme data subtractor, which is valid after fetch
period 5. Input SI is the borrow input (both in master and in
slave mode), which has to be valid in fetch period 0. Input
SI has to be connected to output OFB3 of a following slave,
if not present, to LOW. For proper transfer of the borrow
from a lower to a higher significant U.D. subtractor, the
U.D.s have to be programmed sequentially in order of
significance or synchronously if the programme is
repeated at least the number of U.D.s in the system.
Rate input RI and output OFS must be connected to rate
output OFB1 and the input IN of the next slave U.D. The
combination thus formed retains the full programmability
and features of one U.D.
Fig.7 Timing diagram showing output pulses.
January 1995
8
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Philips Semiconductors
Universal divider
January 1995
9
Product specification
HEF4751V
LSI
Fig.8 Block diagram showing cascading of U.Ds.
Philips Semiconductors
Product specification
HEF4751V
LSI
Universal divider
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
VDD
V
VOH
V
VOL
V
−40
SYMBOL
MIN.
Output (sink)
current LOW
Output (source)
current HIGH
4,75
0,4
5
0,4
10
0,5
5
4,6
5
2,5
10
9,5
+ 25
MAX.
MIN.
1,6
IOL
−IOH
+ 85
MAX.
1,4
MIN.
MAX.
1,1
mA
1,7
1,5
1,2
mA
2,9
2,7
2,2
mA
1,0
0,85
0,55
mA
3,0
2,5
1,7
mA
3,0
2,5
1,7
mA
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
PARAMETER
Propagation delay
IN → OSY
VDD
V
5
10
SYMBOL
MIN.
TYP.
tPHL
MAX.
UNIT
135
270 ns
45
90 ns
CL = 10 pF
HIGH to LOW
Output transition
times
HIGH to LOW
5
10
LOW to HIGH
5
10
Maximum input
5
frequency; IN
10
Maximum input
5
frequency; IN
10
Maximum input
5
frequency; PC
10
tTHL
tTLH
30
60 ns
12
25 ns
45
90 ns
20
40 ns
dissipation per
CL = 50 pF
4
8
MHz
δ = 50%
12
24
MHz
C0b ratio > 1
fmax
2
4
MHz
δ = 50%
6
12
MHz
C0b ratio = 1
fmax
0,15
0,3
MHz
0,5
1,0
MHz
fmax
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1 200 fi + ∑ (foCL) × VDD
10
5 400 fi + ∑ (foCL) × VDD2
Dynamic power
package (P)
CL = 50 pF
where
2
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
10
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