INTEGRATED CIRCUITS DATA SHEET PCD5003 Advanced POCSAG Paging Decoder Product specification Supersedes data of 1997 Mar 04 File under Integrated Circuits, IC17 1997 Jun 24 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder CONTENTS FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 Introduction The POCSAG paging code Error correction Operating states ON status OFF status Reset Bit rates Oscillator Input data processing Battery saving Synchronization strategy Call termination Call data output format Sync word indication Error type indication Data transfer Receiver and oscillator control External receiver control and monitoring Battery condition input Synthesizer control Serial microcontroller interface Decoder I2C-bus access External interrupt Status/Control register Pending interrupts Out-of-Range Indication Real time clock Periodic interrupt Received call delay Alert generation Alert cadence register (03H; write) Acoustic alert Vibrator alert LED alert Warbled alert Direct alert control Alert priority Cancelling alerts Automatic POCSAG alerts SRAM access RAM write address pointer (06H; read) 1997 Jun 24 2 PCD5003 7.43 7.44 7.45 7.46 7.47 7.48 7.49 7.50 7.51 7.52 7.53 7.54 7.55 7.56 7.57 7.58 7.59 RAM read address pointer (08H; read/write) RAM data output register (09H; read) EEPROM access EEPROM address pointer (07H; read/write) EEPROM data I/O register (0AH; read/write) EEPROM access limitations EEPROM read operation EEPROM write operation Invalid write address Incomplete programming sequence Unused EEPROM locations Special programmed function allocation Synthesizer programming data Identifier storage allocation Voltage doubler Level-shifted interface Signal test mode 8 OPERATING INSTRUCTIONS 8.1 8.2 8.3 8.4 Reset conditions Power-on reset circuit Reset timing Initial programming 9 LIMITING VALUES 10 DC CHARACTERISTICS 11 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER) 12 OSCILLATOR CHARACTERISTICS 13 EEPROM CHARACTERISTICS 14 AC CHARACTERISTICS 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING 17.1 17.2 17.3 17.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS 20 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 1 PCD5003 • On-chip SRAM buffer for message data FEATURES • Slave I2C-bus interface to microcontroller for transfer of message data, status/control and EEPROM programming (data transfer at up to 400 kbits/s) • Wide operating supply voltage range: 1.5 to 6.0 V • EEPROM programming requires only 2.0 V supply • Low operating current: 50 µA typ. (ON), 25 µA typ. (OFF) • Wake-up interrupt for microcontroller, programmable polarity • Temperature range: −25 to +70 °C • Direct and I2C-bus control of operating status (ON/OFF) • “CCIR Radio paging Code No. 1” (POCSAG) compatible • Battery-low indication (external detector) • 512, 1200 and 2400 bits/s data rates using 76.8 kHz crystal • Real time clock reference output • Out-of-range condition indication • On-chip voltage doubler • Built-in data filter (16-times oversampling) and bit clock recovery • Advanced ACCESS • Interfaces directly to UAA2080 and UAA2082 paging receivers. synchronization algorithm • 2-bit random and (optional) 4-bit burst error correction • Up to 6 user addresses (RICs), each with 4 functions/alert cadences 2 APPLICATIONS • Up to 6 user address frames, independently programmable • Information services • Standard POCSAG sync word, plus up to 4 user programmable sync words • Telepoint • Display pagers, basic alert-only pagers • Personal organizers • Telemetry/data transmission. • Received data inversion (optional) • Call alert via beeper, vibrator or LED • 2-level acoustic alert using single external transistor 3 • Alert control: automatic (POCSAG type), via cadence register or alert input pin The PCD5003 is a very low power POCSAG decoder and pager controller. It supports data rates of 512, 1200 and 2400 bits/s using a single 76.8 kHz crystal. On-chip EEPROM is programmable using a minimum supply voltage of 2.0 V, allowing ‘over-the-air’ programming. The PCD5003 is fast I2C-bus compatible (maximum 400 kbits/s). • Separate power control of receiver and RF-oscillator for battery economy • Synthesizer set-up and control interface (3-line serial) • On-chip EEPROM for storage of user addresses (RICs), pager configuration and synthesizer data 4 GENERAL DESCRIPTION ORDERING INFORMATION TYPE NUMBER PCD5003H PCD5003U/10 1997 Jun 24 PACKAGE NAME LQFP32 − DESCRIPTION plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm film-frame carrier (naked die) 32 pads 3 VERSION SOT358-1 − Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 5 PCD5003 BLOCK DIAGRAM handbook, full pagewidth EEPROM ZSD ZSC ZLE RXE ROE RDI 26 27 28 SYNTHESIZER CONTROL 24 25 23 RECEIVER CONTROL DATA FILTER AND CLOCK RECOVERY 9 EEPROM CONTROL DECODING DATA CONTROL 7 RESET SET-UP I 2 C-BUS CONTROL 10 POCSAG SYNCHRONIZATION 5 REGISTERS AND INTERRUPT CONTROL RAM CONTROL 3 CLOCK CONTROL 30 MASTER DIVIDER 31 ALERT GENERATION AND CONTROL TIMER REFERENCE 1 32 2 TS1 TS2 XTAL1 XTAL2 16 20 4 TEST CONTROL VOLTAGE DOUBLER AND LEVEL SHIFTER PCD5003 18 17 OSCILLATOR 11 15 14 13 8 12, 29 MLC244 VDD Fig.1 Block diagram. 1997 Jun 24 SDA SCL INT BAT MAIN DECODER RAM DON 21 RST 4 VSS VIB LED ATL ATH ALC REF CCN CCP VPO VPR Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 6 PCD5003 PINNING SYMBOL PIN DESCRIPTION 4 real time clock frequency reference output INT 5 interrupt output n.c. 6 not connected RST 7 reset input (normally LOW by internal pull-down) VPR 8 external positive voltage reference input SDA 9 I2C-bus serial data input/output SCL 10 I2C-bus serial clock input VDD 11 main positive supply voltage ATL 1 24 RXE VSS 12 main negative supply voltage ALC 2 23 RDI VPO 13 voltage converter positive output DON 3 22 n.c. CCP 14 voltage converter shunt capacitor (positive side) REF 4 INT 5 n.c. 6 19 n.c. RST 7 18 XTAL1 VPR 8 17 XTAL2 XTAL1 18 decoder crystal oscillator input n.c. 19 not connected TS2 20 test input 2 (normally LOW by internal pull-down) BAT 21 battery sense input n.c. 22 not connected RDI 23 received POCSAG data input RXE 24 receiver circuit enable output ROE 25 receiver oscillator enable output ZSD 26 synthesizer serial data output ZSC 27 synthesizer serial clock output ZLE 28 synthesizer latch enable output VSS 29 main negative supply voltage VIB 30 vibrator motor drive output LED 31 LED drive output ATH 32 alert HIGH level output 1997 Jun 24 TS1 16 decoder crystal oscillator output 20 TS2 CCN 15 17 CCP 14 XTAL2 VPO 13 test input 1 (normally LOW by internal pull-down) VSS 12 16 SCL 10 TS1 VDD 11 voltage converter shunt capacitor (negative side) 9 15 21 BAT PCD5003H SDA CCN 25 ROE REF 26 ZSD direct ON/OFF input (normally LOW by internal pull-down) 27 ZSC 3 28 ZLE DON 29 VSS alert control input (normally LOW by internal pull-down) 30 VIB alert LOW level output 2 31 LED 1 ALC 32 ATH ATL MLC245 Fig.2 Pin configuration for SOT358-1 (LQFP32). 5 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7 7.1 PCD5003 between the devices. Pager status includes features provided by the PCD5003 such as battery-low and out-of-range indications. A dedicated interrupt line minimizes the required microcontroller activity. FUNCTIONAL DESCRIPTION Introduction The PCD5003 is a very low power decoder and pager controller specifically designed for use in new generation radio pagers. The architecture of the PCD5003 allows for flexible application in a wide variety of radio pager designs. A selectable low frequency timing reference is provided for use in real time clock functions. Data synchronization is achieved by the Philips patented ACCESS algorithm ensuring that maximum advantage is made of the POCSAG code structure particularly in fading radio signal conditions. The algorithm allows for data synchronization without preamble detection whilst minimizing battery power consumption. The PCD5003 is fully compatible with “CCIR Radio paging Code No. 1” (also known as the POCSAG code) operating at data rates of 512, 1200 and 2400 bits/s using a single oscillator crystal of 76.8 kHz. In addition to the standard POCSAG sync word the PCD5003 is also capable of recognizing up to 4 User Programmable Sync Words (UPSWs). This permits the reception of both private services and POCSAG transmissions via the same radio channel. Random and (optional) burst error correction techniques are applied to the received data to optimize on call success rate without increasing falsing rate beyond specified POCSAG levels. Used together with the Philips UAA2080 or UAA2082 paging receiver, the PCD5003 offers a highly sophisticated, miniature solution for the radio paging market. Control of an RF synthesizer circuit is also provided to ease alignment and channel selection. 7.2 A transmission using the “CCIR Radio paging Code No. 1” (POCSAG code) is constructed in accordance with the following rules (see Fig.3). On-chip EEPROM provides storage for user addresses (Receiver Identity Codes or RICs) and Special Programmed Functions (SPFs), which eliminates the need for external storage devices and interconnection. For other non-volatile storage 20 bytes of general purpose EEPROM are available. The low EEPROM programming voltage makes the PCD5003 well- suited for ‘over-the-air’ programming/reprogramming. The transmission is started by sending a preamble, consisting of at least 576 continuously alternating bits (10101010...). The preamble is followed by an arbitrary number of batch blocks. Only complete batches are transmitted. Each batch comprises 17 codewords of 32 bits each. The first codeword is a synchronization codeword with a fixed pattern. The sync word is followed by 8 frames (0 to 7) of 2 codewords each, containing message information. A codeword in a frame can either be an address, message or idle codeword. On request from an external controlling device or automatically (by SPF programming), the PCD5003 will provide standard POCSAG alert cadences by driving a standard acoustic ‘beeper’. Non-standard alert cadences may be generated via a cadence register or a dedicated control input. Idle codewords also have a fixed pattern and are used to fill empty frames or to separate messages. The PCD5003 can also produce a HIGH level acoustic alert as well as drive an LED indicator and a vibrator motor via external bipolar transistors. Address codewords are identified by an MSB of logic 0 and are coded as shown in Fig.3. A user address or RIC consists of 21 bits. Only the upper 18 bits are encoded in the address codeword (bits 2 to 19). The lower 3 bits designate the frame number (0 to 7) in which the address is transmitted. The PCD5003 contains a low-power, high-efficiency voltage converter (doubler) designed to provide a higher voltage supply to LCD drivers or microcontrollers. In addition, an independent level shifted interface is provided allowing communication to a microcontroller operating at a higher voltage than the PCD5003. Four different call types (‘numeric’, ‘alphanumeric’ and two ‘alert only’ types) can be distinguished on each user address. The call type is determined by two function bits in the address codeword (bits 20 and 21), as shown in Table 1. Interface to such an external device is provided by an I2C-bus which allows received call identity and message data, data for the programming of the internal EEPROM, alert control and pager status information to be transferred 1997 Jun 24 The POCSAG paging code 6 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Alert-only calls only consist of a single address codeword. Numeric and alphanumeric calls have message codewords following the address. A message causes the frame structure to be temporarily suspended. Message codewords are sent until the message is completed, with only the sync words being transmitted in their expected positions. Each codeword is protected against transmission errors by 10 CRC check bits (bits 22 to 31) and an even-parity bit (bit 32). This permits correction of maximum 2 random errors or up to 3 errors in a burst of 4 bits (a 4-bit burst error) per codeword. The POCSAG standard recommends the use of combinations of data formats and function bits, as given in Table 1. Other (non-standard) combinations will be received normally by the PCD5003. Message data is not deformatted. Message codewords are identified by an MSB of logic 1 and are coded as shown in Fig.3. The message information is stored in a 20-bit field (bits 2 to 21). The data format is determined by the call type: 4 bits per digit for numeric messages and 7 bits per (ASCII) character for alphanumeric messages. handbook, full pagewidth PREAMBLE BATCH 1 BATCH 2 BATCH 3 LAST BATCH 10101 . . . 10101010 SYNC | CW CW | CW CW | . . . . . | CW CW FRAME 0 FRAME 1 Address code-word 0 18-bit address Message code-word 1 20-bit message FRAME 7 2 function bits 10 CRC bits P 10 CRC bits P MCD456 Fig.3 POCSAG code structure. Table 1 POCSAG recommended call types and function bits BIT 20 (MSB) BIT 21 (LSB) CALL TYPE DATA FORMAT 0 0 numeric 4-bits per digit 1997 Jun 24 0 1 alert only 1 − 1 0 alert only 2 − 1 1 alphanumeric 7-bits per ASCII character 7 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.3 PCD5003 Error correction Table 2 Error correction ITEM DESCRIPTION Preamble 4 random errors in 31 bits Synchronization codeword 2 random errors in 32 bits Address codeword 2 random errors, plus: 4-bit burst errors (optional) Message codeword 2 random errors, plus: 4-bit burst errors (optional) In the PCD5003 error correction methods have been implemented as shown in Table 2. 7.6 OFF status In OFF status the decoder will neither activate the receiver or oscillator enable outputs, nor process any data at the data input. The crystal oscillator remains active to permit communication with the microcontroller. Random error correction is default for both address and message codewords. In addition, burst error correction can be enabled by SPF programming. Up to 3 erroneous bits in a 4-bit burst can be corrected. The error type detected for each codeword is identified in the message data output to the microcontroller, allowing rejection of calls with too many errors. In both operating states an accurate timing reference is available via the REF output. By SPF programming the signal periodicity may be selected as 32.768 kHz, 50 Hz, 2 Hz or 1⁄60 Hz. 7.4 7.7 Operating states The PCD5003 has 2 operating states: The decoder can be reset by applying a positive pulse on input pin RST. A power-on reset circuit consisting of an RC network can be connected to this input as well. Conditions during and after a reset are described in Chapter “Operating instructions”. • ON status • OFF status. The operating state is determined by a Direct Control input (DON) and bit D4 in the control register (see Table 3). Table 3 7.5 For successful reset at power-on, a HIGH level must be present on the RST pin while the device is powering-up. This can be applied by the microcontroller, or via a suitable RC power-on reset circuit connected to the RST input. Reset circuit details and conditions during and after a reset are described in Chapter 8 Truth table for decoder operating status DON INPUT CONTROL BIT D4 OPERATING STATUS 0 0 OFF 0 1 ON 1 0 ON 1 1 ON 7.8 Bit rates The PCD5003 can be configured for data rates of 512, 1200 or 2400 bit/s by SPF programming. These data rates are derived from a single 76.8 kHz oscillator frequency. ON status In ON status the decoder pulses the receiver and oscillator enable outputs (respectively RXE and ROE) according to the code structure and the synchronization algorithm. Data received serially at the data input (RDI) is processed for call receipt. Reception of a valid paging call is signalled to the microcontroller by means of an interrupt signal. The received address and message data can then be read via the I2C-bus interface. 1997 Jun 24 Reset 7.9 Oscillator The oscillator circuit is designed to operate at 76.8 kHz. Typically, a tuning fork crystal will be used as a frequency source. Alternatively, an external clock signal can be applied to pin XTAL1 (amplitude = VDD to VSS), but a slightly higher oscillator current is consumed. A 2.2 MΩ feedback resistor connected between XTAL1 and XTAL2 is required for proper operation. 8 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 To allow easy oscillator adjustment (e.g. by means of a variable capacitor) a 32.768 kHz reference frequency can be selected at output REF by SPF programming. 7.10 appropriate establishment times (respectively tRXON and tROON). Before comparing received data with preamble, an enabled sync word or programmed user addresses, the appropriate error correction is applied. Input data processing Data input is binary and fully asynchronous. Input bit rates of 512, 1200 and 2400 bits/s are supported. As a programmable option, the polarity of the received data can be inverted before further processing. Initially, after switching to ON status, the decoder is in switch-on mode. Here the receiver will be enabled for a period up to 3 batches, testing for preamble and sync word. Failure to detect preamble or sync word will cause switching to ‘carrier off’ mode. The input data is noise filtered by means of a digital filter. Data is sampled at 16 times the data rate and averaged by majority decision. Detection of preamble switches to preamble receive mode, in which sync word is looked for. The receiver will remain enabled while preamble is detected. When neither sync word nor preamble is found within 1 batch duration ‘carrier off’ mode is entered. The filtered data is used to synchronize an internal clock generator by monitoring transitions. The recovered clock phase can be adjusted in steps of 1⁄8 or 1⁄32 bit period per received bit. Upon detection of a sync word the data receive mode is entered. The receiver is activated only during enabled user address frames and sync word periods. When an enabled user address has been detected, the receiver will be kept enabled for message codeword reception until the call termination criteria are met. The larger step size is used when bit synchronization has not been achieved, the smaller when a valid data sequence has been detected (e.g. preamble or sync word). 7.11 Battery saving During call reception data bytes are stored in an internal SRAM buffer, capable of storing 2 batches of message data. Current consumption is reduced by switching off internal decoder sections whenever the receiver is not enabled. Messages are transmitted contiguously, only interrupted by sync words at the beginning of each batch. When a message extends beyond the end of a batch, no testing for sync takes place. Instead, a message data transfer will be initiated by an interrupt to the external controller. Data reception continues normally after a period corresponding to the sync word duration. To further increase battery efficiency, reception and decoding of an address codeword is stopped as soon as the uncorrected address field differs by more than 3 bits from the enabled RICs. If the next codeword must be received again, the receiver is re-enabled thus observing the programmed establishment times tRXE and tRDE. The current consumption of the complete pager can be minimized by separately activating the RF oscillator circuit (at output ROE) before activating the rest of the receiver. This is possible with the UAA2082 receiver which has external biasing for the oscillator circuit. 7.12 If any message codeword is found to be uncorrectable, ‘data-fail’ mode is entered and no data transfer will be attempted at the next sync word position. Instead, a test for sync word will be carried out. In the data fail mode message reception continues normally for 1 batch duration. Upon detection of sync word at the expected position the decoder returns to ‘data receive’ mode. If sync word again fails to appear, batch synchronization is deemed lost. Call reception is then terminated and ‘fade recovery’ mode is entered. Synchronization strategy In ON status the PCD5003 synchronizes to the POCSAG data stream by means of the Philips ACCESS algorithm. A flow diagram is shown in Fig.4. Where ‘sync word’ is used, this implies both the standard POCSAG sync word and any enabled User Programmable Sync Word (UPSW). The fade recovery mode is intended to scan for sync word and preamble over an extended window (nominal position ±8 bits). Several modes of operation can be distinguished depending on the synchronization state. Each mode uses a different method to obtain or retain data synchronization. The receiver and oscillator enable outputs (respectively RXE and ROE) are switched accordingly, with the 1997 Jun 24 9 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder The formats of a call header, a message data block and a call terminator are shown in Tables 4, 6 and 8. This is done for a period of up to 15 batches, allowing recovery of synchronization from long fades in the radio signal. Detection of preamble switches to ‘preamble receive’ mode, while sync word detection switches to ‘data receive’ mode. When neither is found within a period of 15 batches, the radio signal is considered lost and ‘carrier off’ mode is entered. A Call Header contains information on the last sync word received, the RIC which began call reception and the type of error correction performed on the address codeword. A Message Data block contains the data bits from a message codeword plus the type of error correction performed. No deformatting is done on the data bits: numeric data appear as 4-bit groups per digit, alphanumeric data have a 7-bit ASCII representation. The purpose of carrier off mode is to detect a valid radio transmission and synchronize to it quickly and efficiently. Because transmissions may start at random, the decoder enables the receiver for 1 codeword in every 18 codewords looking for preamble or sync word. By using a buffer containing 32 bits (n bits from the current scan, 32 − n from the previous scan) effectively every batch bit position can be tested within a continuous transmission of at least 18 batches. Detection of preamble switches to ‘preamble receive’ mode, while sync word detection switches to ‘data receive’ mode. 7.13 The Call Terminator contains information on the last sync word received, information on the way the call was terminated (forced call termination command, loss of sync word in ‘data fail’ mode) and the type of error correction performed on the terminating codeword. 7.15 • Upon reception of any address codeword (including Idle codeword) requiring no more than single bit error correction 7.16 • In ‘data fail’ mode, when a sync word is not found at the expected batch position Error type indication Table 10 shows how the different types of detected errors are encoded in the call data output format. • When a forced call termination command is received from an external controller. A message codeword containing more than a single bit error (bit E3 = 1) may appear as an address codeword (bit M1 = 0) after error correction. In this event the codeword is processed as message data and does not cause call termination. The last method permits an external controller to stop call reception depending on the number and type of errors which occurred in a call. After a forced call termination the decoder will enter ‘data fail’ mode. The type of error correction as well as the call termination conditions are indicated by status bits in the message data output. 7.17 Data transfer Data transfer is initiated either during sync word periods or as soon as the receiver is disabled after call termination. If the SRAM buffer is full, data transfer is initiated immediately during the next codeword. Following call termination, transfer of the data received since the previous sync word period is initiated by means of an interrupt to the external controller. When the PCD5003 is ready to transfer received call data an external interrupt will be generated via output INT. Any message data can be read by accessing the RAM output register via the I2C-bus interface. Bytes will be output starting from the position indicated by the RAM read pointer. Call data output format POCSAG call information is stored in the decoder SRAM in blocks of 3 bytes per codeword. Each stored call consists of a call header, followed by message data blocks and concluded by a call terminator. In the event of concatenated messages the call terminator is replaced with the call header of the next message. An alert-only call only has a call header and a call terminator. 1997 Jun 24 Sync word indication The sync word recognized by the PCD5003 is shown in the call header (bits S3 to S1). The decimal value represents the identifier number in the EEPROM of the UPSW in question. A value of 7 indicates the standard POCSAG sync word. Call termination Call reception is terminated: 7.14 PCD5003 10 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 OFF to ON status handbook, full pagewidth no preamble or sync word (3 batches) switch-on sync word no preamble or sync word (1 batch) preamble preamble receive sync word data receive sync word no sync word data fail preamble no preamble or sync word (1 batch) sync word fade recovery preamble no preamble or sync word (15 batches) sync word carrier off preamble MLC247 Fig.4 ACCESS synchronization algorithm. 1997 Jun 24 11 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder Table 4 PCD5003 Call header format BYTE NUMBER BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) 1 0 S3 S2 S1 R3 R2 R1 DF 2 0 S3 S2 S1 R3 R2 R1 0 3 X X F0 F1 E3 E2 E1 0 Table 5 Call header bit identification BITS (MSB to LSB) IDENTIFICATION S3 to S1 identifier number of sync word for current batch (7 = standard POCSAG) R3 to R1 identifier number of user address (RIC) DF data fail mode indication (1 = data fail mode); note 1 F0 and F1 function bits of received address codeword (bits 20, 21) E3 to E1 detected error type; see Table 10; E3 = 0 in a concatenated call header Note 1. The DF bit in the call header is set: a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard POCSAG or a user-programmed sync word. The sync word identifier (bits S3 to S1) will then be made 0. b) When any codeword of a previous call received in the same batch was uncorrectable. Table 6 Message data format BYTE NUMBER BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) 1 M2 M3 M4 M5 M6 M7 M8 M9 2 M10 M11 M12 M13 M14 M15 M16 M17 3 M18 M19 M20 M21 E3 E2 E1 M1 Table 7 Message data bit identification BITS (MSB to LSB) M2 to M21 message codeword data bits E3 to E1 detected error type; see Table 10 M1 Table 8 IDENTIFICATION message codeword flag Call terminator format BYTE NUMBER BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) 1 FT S3 S2 S1 0 0 0 DF 2 FT S3 S2 S1 0 0 0 X 3 X X X X E3 E2 E1 0 1997 Jun 24 12 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder Table 9 PCD5003 Call terminator bit identification BITS (MSB to LSB) IDENTIFICATION FT forced call termination (1 = yes) S3 to S1 identifier number of last sync word DF data fail mode indication (1 = data fail mode); note 1 E3 to E1 detected error type; see Table 10; E3 = 0 in a call terminator Note 1. The DF bit in the call terminator is set: a) When any call data codeword in the terminating batch was uncorrectable, while in ‘data receive’ mode. b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a user-programmed sync word, while in ‘data fail’ mode. Table 10 Error type identification (note 1) E3 E2 E1 NUMBER OF ERRORS 0 0 0 no errors - correct codeword 0 0 1 parity bit in error 1 0 1 0 single bit error 1 + parity 0 1 1 single bit error and parity error 1 1 0 0 not used 1 0 1 4-bit burst error and parity error 3 (e.g.1101) 1 1 0 2-bit random error 2 1 1 1 uncorrectable codeword 3 or more ERROR TYPE 0 Note 1. POCSAG code allows a maximum of 3 bit errors to be detected per codeword. Successful call termination occurs by reception of a valid address codeword with less than 2 bit errors. Unsuccessful termination occurs when sync word is not detected while in ‘data fail’ mode. 7.18 A paging receiver and an RF oscillator circuit can be controlled independently via enable outputs RXE and ROE respectively. Their operating periods are optimized according to the synchronization mode of the decoder. Each enable signal has its own programmable establishment time (see Table 11). It is generally possible to distinguish these two conditions using the sync word identifier number (bits S3 to S1); the identifier number will be non-zero for correct termination, and zero for sync word failure. 7.19 Only when a call is received in ‘data fail’ mode and the call is terminated before the end of the batch, is it not possible to distinguish unsuccessful from correct termination. External receiver control and monitoring An external controller may enable the receiver control outputs continuously via an I2C-bus command, overruling the normal enable pattern. Data reception continues normally. This mode can be left by means of a reset or an I2C-bus command. Reception of message data can be terminated at any time by transmitting a forced call termination command to the control register via the I2C-bus. Any call received will then be terminated immediately and ‘data fail’ mode will be entered. 1997 Jun 24 Receiver and oscillator control External monitoring of the receiver control output RXE is possible via bit D6 in the status register, when enabled via the control register (D2 = 1). Each change of state of output RXE will generate an external interrupt at output INT. 13 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.20 PCD5003 copies the data to the internal divider registers. A timing diagram is given in Fig.5. Battery condition input A logic signal from an external sense circuit signalling battery condition can be applied to the BAT input. This input is sampled each time the receiver is disabled (RXE ↓ 0). The data output timing is synchronous, but has a pause in the bit stream of each block. This pause occurs in the 13th bit while ZSC is LOW. The nominal pause duration tp depends on the programmed bit rate for data reception and is shown in Table 12. The total duration of the 13th bit is given by tZCL + tp. When enabled via the control register (D2 = 0), the condition of input BAT is reflected in bit D6 of the status register. Each change of state of bit D6 causes an external interrupt at output INT. A similar pause occurs between the first and the second data block. The delay between the first latch enable pulse and the second data block is given by tZDL2 + tp. The complete start-up timing of the synthesizer interface is given in Fig.12. When using the UAA2080 pager receiver a battery-low condition corresponds to a logic HIGH-level. With a different sense circuit the reverse polarity can be used as well, because every change of state is signalled to an external controller. Table 12 Synthesizer programming pause After a reset the initial condition of the battery-low indicator in the status register is zero. BIT RATE (bit/s) tp (clocks) tp (µs) Table 11 Receiver and oscillator establishment times (note 1) CONTROL OUTPUT ESTABLISHMENT TIME UNIT RXE 5 10 15 30 ms ROE 20 30 40 50 ms 7.22 1. The exact values may differ slightly from the above values, depending on the bit rate (see Table 22). 1549 33 430 2400 1 13 Serial microcontroller interface Data transmission requires 2 lines: SDA (data) and SCL (clock), each with an external pull-up resistor. The clock signal (SCL) for any data transmission must be generated by the external controlling device. Synthesizer control Control of an external frequency synthesizer is possible via a dedicated 3-line serial interface (outputs ZSD, ZSC and ZLE). This interface is common to a number of available synthesizers. The synthesizer is enabled using the oscillator enable output ROE. A transmission is initiated by a start condition (S: SCL = 1, SDA = ↓) and terminated by a stop condition (P: SCL = 1, SDA = ↑). The frequency parameters must be programmed in EEPROM. Two blocks of maximum 24 bits each can be stored. Any unused bits must be programmed at the beginning of a block: only the last bits are used by the synthesizer. Data bits must be stable when SCL is HIGH. If there are multiple transmissions, the stop condition can be replaced with a new start condition. Data is transferred on a byte basis, starting with a device address and a read/write indicator. Each transmitted byte must be followed by an acknowledge bit ACK (active LOW). If a receiving device is not ready to accept the next complete byte, it can force a bus wait state by holding SCL LOW. When the function is selected by SPF programming (SPF byte 01, bit D6), data is transferred to the synthesizer each time the PCD5003 is switched from OFF to ON status. Transfer takes place serially in two blocks, starting with bit 0 (MSB) of block 1 (see Table 25). The general I2C-bus transmission format is shown in Fig.6. Formats for master/slave communication are shown in Fig.7. Data bits on ZSD change on the falling flanks of ZSC. After clocking all bits into the synthesizer, a latch enable pulse 1997 Jun 24 119 The PCD5003 has an I2C-bus serial microcontroller interface capable of operating at 400 kbits/s. The PCD5003 is a slave transceiver with a 7-bit I2C-bus address 39 (bits A6 to A0 = 0100111). Together with the R/W bit the first byte of an I2C-bus message then becomes 4EH (write) or 4FH (read). Note 7.21 512 1200 14 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder handbook, full pagewidth t ZSD MSB LSB 0 ZSD PCD5003 12 23 ZSC TIME t ZCL t ZDL1 tp t ZDS ZLE TIME t ZLE MLC248 Fig.5 Synthesizer interface timing. handbook, full pagewidth MSB LSB N SDA MSB LSB A N A S SCL P 1 START 2 ADDRESS 7 8 9 INTERRUPT SERVICING 1 2 R/W A 7 DATA 8 9 A STOP MLC249 Fig.6 I2C-bus message format. 1997 Jun 24 15 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder FROM MASTER handbook, full pagewidth (a) S R/W S SLAVE ADDRESS INDEX A A R/W DATA 1 (read) (c) S SL. ADR. R/W 0 (write) A INDEX index address A A DATA index address 0 (write) (b) A = Acknowledge N = Not acknowledge S = START condition P = STOP condition FROM SLAVE SLAVE ADDRESS PCD5003 DATA A DATA A P n bytes with acknowledge A DATA N P n bytes with acknowledge A n bytes with acknowledge S SL. ADR. R/W 1 (read) change of direction A DATA N P n bytes with acknowledge MLC250 (a) Master writes to slave. (b) Master reads from slave. (c) Combined format (shown: write plus read). Fig.7 Message types. 7.23 Data written to read-only bits will be ignored. Values read from write-only bits are undefined and must be ignored. Decoder I2C-bus access All internal access to the PCD5003 takes place via I2C-bus interface. For this purpose the internal registers, SRAM and EEPROM have been memory mapped and are accessed via an index register. Table 13 shows the index addresses of all internal blocks. Each I2C write message to the PCD5003 must start with its slave address, followed by the index address of the memory element to be accessed. An I2C read message uses the last written index address as a data source. The different I2C-bus message types are shown in Fig.7. Registers are addressed directly, while RAM and EEPROM are addressed indirectly via address pointers and I/O registers. As a slave the PCD5003 cannot initiate bus transfers by itself. To prevent an external controller from having to monitor the operating status of the decoder, all important events generate an external interrupt on output INT. Remark: The EEPROM memory map is non-contiguous and organized as a matrix. The EEPROM address pointer contains both row and column indicators. 1997 Jun 24 16 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 13 Index register ADDRESS(1) REGISTER FUNCTION ACCESS 00H status R 00H control W 01H real time clock: seconds R/W 02H real time clock: 1⁄100 second R/W 03H alert cadence W 04H alert set-up W 05H periodic interrupt modulus W 05H periodic interrupt counter R 06H RAM write address pointer R 07H EEPROM address pointer R/W 08H RAM read address pointer R/W 09H RAM data output R 0AH EEPROM data input/output R/W 0BH to 0FH unused note 2 Notes 1. The index register only uses the least significant nibble, the upper 4 bits are ignored. 2. Writing to registers 0B to 0F has no effect, reading produces meaningless data. 7.24 The interrupt output INT is reset after completion of a status read operation. External interrupt The PCD5003 can signal events to an external controller via an interrupt signal on output INT. The interrupt polarity is programmable via SPF programming. The interrupt source is shown in the status register. 7.25 The status/control register consists of two independent registers, one for reading (status) and one for writing (control). Interrupts are generated by the following events (more than one event possible): The status register shows the current operating condition of the decoder and the cause(s) of an external interrupt. The control register activates/deactivates certain functions. Tables 14 and 15 show the bit allocations of both registers. • Call data available for output (bit D2) • SRAM pointers becoming equal (bit D3) • Expiry of periodic time-out (bit D7) • Expiry of alert time-out (bit D4) • Change of state in out-of-range indicator (bit D5) All status bits will be reset after a status read operation except for the out-of-range, battery-low and receiver enable indicator bits (see note 1 to Table 14). • Change of state in battery-low indicator or in receiver control output RXE (bit D6). Status bit D0 is set when call reception is started by detection of an enabled RIC (user address). This does not generate an interrupt. Immediate interrupts are generated by status bits D3, D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6 (BAT monitoring) generate interrupts as soon as the receiver is disabled (RXE = 0). When call data is available (D2 = 1) but the receiver remains switched on, an interrupt is generated at the next sync word position. 1997 Jun 24 Status/Control register 17 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 14 Status register (00H; read) BIT(1) D1 and D0 D3 and D2 VALUE DESCRIPTION 00 no new call data 01 new call received 10 reserved for future use 11 reserved for future use 00 no data to be read (default after reset) 01 RAM read/write pointers different: data to be read 10 RAM read/write pointers equal: no more data to read 11 RAM buffer full or overflow D4 1 alert time-out expired D5 1 out-of-range D6 1 BAT input HIGH or RXE output active (selected by control bit D2) D7 1 periodic timer interrupt Note 1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is pending. D2 is reset when the RAM is empty (read and write pointers equal). Table 15 Control register (00H; write) BIT (MSB: D7) VALUE D0 1 forced call termination (automatically reset after termination) D1 1 EEPROM programming enable 0 BAT input selected for monitoring (status bit D6) 1 RXE output selected for monitoring (status bit D6) 1 receiver continuously enabled (RXE = 1, ROE = 1) 0 decoder in OFF status (while DON = 0) 1 decoder in ON status X not used: ignored when written D2 D3 D4 D5 to D7 7.26 DESCRIPTION Pending interrupts 7.27 A secondary status register is used for storing status bits of pending interrupts. This occurs: The out-of-range condition occurs when entering fade recovery or ‘carrier off’ mode. This condition is reflected in bit D5 of the status register. The out-of-range condition is reset when either preamble or a valid sync word is detected. • When a new call is received while the previous one was not yet acknowledged by reading the status register • When an interrupt occurs during a status read operation. The out-of-range bit (D5) in the status register is updated each time the receiver is disabled (RXE ↓ 0). Every change of state in bit D5 generates an interrupt. After completion of the status read the primary register is loaded with the contents of the secondary register, which is then reset. Next, an immediate interrupt is generated, output INT becoming active 1 decoder clock cycle after it was reset following the status read. Remark: In the event of multiple pending calls, only the status bits of the last call are retained. 1997 Jun 24 Out-of-range Indication 18 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.28 PCD5003 Table 17 Real time clock; 1⁄100 second register (02H; read/write) Real time clock The PCD5003 provides a periodic reference pulse at output REF. The frequency of this signal can be selected by SPF programming: BIT (MSB D7) VALUE DESCRIPTION D0 − 0 01 s D1 − 0.02 s D2 − 0.04 s D3 − 0.08 s D4 − 0.16 s D5 − 0.32 s D6 − 0.64 s D7 X not used: ignored when written, undetermined when read • 32768 Hz • 50 Hz (square-wave) • 2 Hz • 1⁄60 Hz. The 32768 Hz signal does not have a fixed period: it consists of 32 pulses distributed over 75 main oscillator cycles at 76.8 kHz. The timing is shown in Fig.14. When programmed for 1⁄60 Hz (1 pulse per minute) the pulse at output REF is held off while the receiver is enabled. 7.29 Except for the 50 Hz frequency the pulse width tRFP is equal to one decoder clock period. Periodic interrupt A periodic interrupt can be realised with the Periodic Interrupt Counter. This 8-bit counter is incremented every 1⁄ 100 second and produces an interrupt when it reaches the value stored in the Periodic Interrupt Modulus register. The Counter register is then reset and counting continues. The real time clock counter runs continuously irrespective of the operating condition of the PCD5003. It contains a seconds register (maximum 59) and a 1⁄100 second register (maximum 99), which can be read or written via the I2C-bus. The bit allocation of both registers is shown in Tables 16 and 17. Operation is started by writing a non-zero value to the Modulus register. Writing a zero will stop interrupt generation immediately and will halt the Periodic Interrupt Counter after 2.55 seconds. Table 16 Real time clock; seconds register (01H; read/write) The Modulus register is write-only, the Counter register can only be read. Both registers have the same index address (05H). BIT (MSB D7) VALUE DESCRIPTION D0 − 1s D1 − 2s 7.30 D2 − 4s D3 − 8s Call reception causes both the Periodic Interrupt Modulus and the Counter register to be reset. D4 − 16 s D5 − 32 s D6 X not used: ignored when written, undetermined when read D7 X not used: ignored when written, undetermined when read 1997 Jun 24 Received call delay Since the Periodic Interrupt Counter runs for another 2.55 seconds after a reset, the received call delay (in 1⁄100 second units) can be determined by reading the Counter register. 19 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 18 Alert set-up register (04H; write) BIT (MSB: D7) VALUE DESCRIPTION 0 call alert via cadence register 1 POCSAG call alert (pattern selected by D7, D6) 0 LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz) 1 HIGH level acoustic alert (ATL + ATH), continuous vibrator alert 0 normal alerts (acoustic and LED) 1 warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL) D3 1 acoustic alerts enable (ATL, ATH) D4 1 vibrator alert enabled (VIB) D5 1 LED alert enabled (LED) D0 D1 D2 D7 and D6(1) 00 POCSAG alert pattern FC = 00, see Fig.8(a) 01 POCSAG alert pattern FC = 01, see Fig.8(b) 10 POCSAG alert pattern FC = 10, see Fig.8(c) 11 POCSAG alert pattern FC = 11, see Fig.8(d) Note 1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address codeword, which designate the POCSAG call type as shown in Table 1. D7, D6 handbook, full pagewidth 0 0 (a) 0 1 (b) 1 0 (c) 1 1 (d) Fig.8 POCSAG alert patterns. 1997 Jun 24 20 MLC251 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.31 interrupt occurs at the start of the 8th cadence time slot. Since D1 acts immediately on the alert level, it is advised to reset the last bit of the previous pattern to prevent unwanted audible level changes. Alert generation The PCD5003 is capable of controlling 3 different alert transducers: acoustic beeper (HIGH and LOW level), LED and vibrator motor. The associated outputs are ATH/ATL, LED and VIB respectively. ATL is an open drain output capable of directly driving an acoustic alerter via a resistor. The other outputs require external transistors. 7.34 Two alert levels are supported: LOW level (25 Hz square-wave) and HIGH level (continuous). The vibrator level is controlled by bit D1 in the alert set-up register. The alert set-up register is shown in Table 18. Standard POCSAG alerts can be selected by setting bit D0 in the alert set-up register, bits D6 and D7 determining the alert pattern used. 7.35 7.36 Warbled alert When enabled by setting bit D2 in the alert set-up register, the signals on outputs ATL, ATH and LED are warbled with a 16 Hz modulation frequency. Output LED is switched on and off at the modulation rate, while outputs ATL and ATH switch between fAWH and fAWL alerter frequencies. Alert cadence register (03H; write) When not programmed for POCSAG alerts (alert set-up register bit D0 = 0), the 8-bit alert cadence register determines the alert pattern. Each bit represents a 62.5 ms time slot, a logic 1 activating the enabled alert transducers. The bit pattern is rotated with the MSB (bit D7) being output first and the LSB (bit D0) last. 7.37 Direct alert control A direct alert control input (ALC) is available for generating user alarm signals (e.g. battery-low warning). A HIGH level on input ALC activates all enabled alert outputs, overruling any ongoing alert patterns. When the last time slot (bit D0) is started an interrupt is generated to allow loading of a new pattern. When the pattern is not changed it will be repeated. Writing a zero to the alert cadence register will halt alert generation. 7.38 Acoustic alert Alert priority Generation of a standard POCSAG alert (D0 = 1) overrides any alert pattern in the alert cadence register. After completion of the standard alert, the original cadence is restarted from the position it was left at. The alert set-up register will now contain the settings for the standard alert. Acoustic alerts are generated via outputs ATL and ATH. For LOW level alerts only ATL is active, while for HIGH level alerts ATH is also active. ATL is driven in counter phase with ATH. The alert level is controlled by bit D1 of the alert set-up register. The highest priority has been assigned to the alert control input (ALC). All enabled alert outputs will be activated while ALC is set. Outputs are activated/deactivated synchronous with the decoder clock. Activation requires an extra delay of 1 clock when no alerts are being generated. When D1 is reset, for standard POCSAG alerts (D0 = 1) a LOW level acoustic alert is generated during the first 4 seconds (ATL), followed by 12 seconds at HIGH level (ATL + ATH). When D1 is set, the full 16 seconds are at HIGH level. An interrupt is generated upon expiry of the full alert time. When input ALC is reset, acoustic alerting does not cease until the current output frequency cycle has been completed. When using the alert cadence register, D1 would normally be updated by external control when the alert time-out 1997 Jun 24 LED alert The LED output pattern corresponds either to the selected POCSAG alert or to the contents of the alert cadence register. No equivalent exists for HIGH/LOW level alerts. Automatic generation via all alert outputs of the POCSAG alert pattern matching the received call type can be enabled by SPF programming (SPF byte 03, bit D2). 7.33 Vibrator alert The vibrator output (VIB) is activated continuously during a standard POCSAG alert or whenever the alert cadence register is non-zero. Each alert output can be individually enabled via the alert set-up register. Alert level and warble can be separately selected. The alert pattern can either be standard POCSAG or determined via the alert cadence register. Direct alert control is possible via input ALC. 7.32 PCD5003 21 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.39 When enabled by SPF programming (SPF byte 03, bit D2) standard POCSAG alerts will automatically be generated on outputs ATL, ATH, LED and VIB upon call reception. The alert pattern matches the call type as indicated by the function bits in the received address codeword. Cancelling alerts Standard POCSAG alerts (manual or automatic) are cancelled by resetting bit D0 in the alert set-up register. User defined alerts are cancelled by writing a zero to the alert cadence register. Any ongoing alert is cancelled when a reset pulse is applied to input RST. 7.40 PCD5003 The original settings of the alert set-up register will be lost. Bit D0 is reset after completion of the alert. Automatic POCSAG alerts Standard alert patterns have been defined for each POCSAG call type, as indicated by the function bits in the address codeword (see Table 1). The timing of these alert patterns is shown in Fig.9. handbook, full pagewidth FC = 00 t ALC t ALP FC = 01 t ALP t ALC t ALP FC = 10 t ALC t ALP t ALP FC = 11 t ALC t ALC t ALP t ALP MLC252 Fig.9 POCSAG alert timing. 1997 Jun 24 22 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.41 SRAM access PCD5003 7.44 RAM data output register (09H; read) The RAM data output register contains the byte addressed by the RAM read address pointer. It can only be read, each read operation causing an increment of the RAM read address pointer. The on-chip SRAM can hold up to 96 bytes of call data. Each call consists of a call header (3 bytes), message data blocks (3 bytes per codeword) and a call terminator (3 bytes). The RAM is filled by the decoder and can be read via the I2C-bus interface. The RAM is accessed indirectly by means of a read address pointer and a data output register. A write address pointer indicates the first byte after the last message byte stored. 7.45 EEPROM access The EEPROM is intended for storage of user addresses (RICs), sync words and special programmed function (SPF) bits representing the decoder configuration. Status register bit D2 is set when the read and write pointers are different. It is reset only when the SRAM pointers become equal during reading, i.e. when the RAM becomes empty. The EEPROM can store 48 bytes of information and is organized as a matrix of 8 rows by 6 columns. The EEPROM is accessed indirectly via an address pointer and a data I/O register. Status bit D3 is set when the read and write pointers become equal. This can be due to a RAM empty or a RAM full condition. It is reset after a status read operation. The EEPROM is protected against inadvertent writing by means of the programming enable bit in the control register (bit D1). Interrupts are generated as follows: The EEPROM memory map is non-contiguous as can be seen in Fig.10, which shows both the EEPROM organization and the access method. • When status bit D2 is set and the receiver is disabled (RXE = 0): data is available for reading • Immediately when status bit D3 is set: RAM is either empty (status bit D2 = 0) or full (status bit D2 = 1). Identifier locations contain RICs or sync words. A total of 20 unassigned bytes is available for general purpose storage. To avoid loss of data due to RAM overflow at least 3 bytes of data must be read during reception of the codeword following the ‘RAM full’ interrupt. 7.42 7.46 An EEPROM location is addressed via the EEPROM address pointer. It is incremented automatically each time a byte is read or written via the EEPROM data I/O register. RAM write address pointer (06H; read) The RAM write address pointer is automatically incremented during call reception, as the decoder writes each data byte to RAM. The RAM write address pointer can only be read. Values range from 00H to 5FH. Bit D7 (MSB) is not used and its value is undefined when read. 7.43 The EEPROM address pointer contains two counters, for the row and the column number. Bits D2 to D0 contain the column number (0 to 5) and bits D5 to D3 the row number (0 to 7). Bits D7 and D6 of the address pointer are not used. Data written to these bits will be ignored, while their values are undefined when read. RAM read address pointer (08H; read/write) The column and row counters are connected in series. Upon overflow of the column counter (column = 5) the row counter is automatically incremented and the column counter wraps to 0. On overflow the row counter wraps from 7 to 0. The RAM read address pointer is automatically incremented after reading a data byte via the RAM output register. It can be accessed for writing as well as reading. 7.47 The values range from 00H to 5FH. When at 5FH a read operation will cause wrapping around to 00H. Bit D7 (MSB) is not used; it is ignored when written and undefined when read. 1997 Jun 24 EEPROM address pointer (07H; read/write) EEPROM data I/O register (0AH; read/write) The byte addressed by the EEPROM address pointer can be written or read via the EEPROM Data I/O register. Each access automatically increments the EEPROM address pointer. 23 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.48 PCD5003 After writing each block a pause of maximum 7.5 ms is required to complete the programming operation internally. During this time the external microcontroller may generate an I2C-bus stop condition. If another I2C-bus transfer is started the decoder will pull SCL LOW during this pause. EEPROM access limitations Since the EEPROM address pointer is used during data decoding, the EEPROM may not be accessed while the receiver is active (RXE = 1). It is advised to switch to OFF state before accessing the EEPROM. The EEPROM cannot be written unless the EEPROM programming enable bit (bit D1) in the control register is set. After writing the EEPROM programming enable bit (D1) in the control register must be reset. For writing a minimum supply voltage VPG is required (2.0 V typ.). The supply current needed during writing (IPG) will be ≈500 µA. 7.51 When an invalid write address is used, the column counter bits (D2 to D0) are forced to zero before being loaded into the address pointer. The row counter bits are used normally. Any modified SPF settings (bytes 0 to 3) only take effect after a decoder reset. Modified identifiers are active immediately. 7.52 7.49 EEPROM read operation Any bytes received of the last 6-byte block will be ignored and the contents of this (incomplete) EEPROM block will remain unchanged. EEPROM write operation EEPROM write operations must always take place in blocks of 6 bytes, starting at the beginning of a row. Programming a single byte will reset the other bytes in the same row. Modifying a single byte in a row requires re-writing the unchanged bytes with their old contents. handbook, full pagewidth 0 1 COLUMN 2 3 4 Incomplete programming sequence A programming sequence may be aborted by an I2C-bus stop condition. Next, the EEPROM programming enable bit (D1) in the control register must be reset. EEPROM read operations must start at a valid address in the non-contiguous memory map. Single-byte or block reads are permitted. 7.50 Invalid write address 7.53 Unused EEPROM locations A total of 20 EEPROM bytes is available for general purpose storage (see Table 19). D7 0 1 ROW ADDRESS POINTER 5 0 2 I I I I I I 3 D D D D D D 4 1 2 3 4 5 6 1 0 D0 1 0 0 ROW COLUMN D7 5 I/O REGISTER D0 6 7 SPF bits Synthesizer data Identifiers unused bytes MLC254 Fig.10 EEPROM organization and access. 1997 Jun 24 24 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 19 Unused EEPROM addresses 7.54 ROW HEX 0 04 and 05(1) 5 28 to 2D 6 30 to 35 7 38 to 3D Special programmed function allocation The SPF bit allocation in the EEPROM is shown in Tables 20 to 24. The SPF bits are located in row 0 of the EEPROM and occupy 4 bytes. Bytes 04H and 05H are not used and are available for general purpose storage. The contents of SPF (bytes 0 to 3) are read into the associated logic only when the decoder is reset (HIGH level in input RST). Note 1. When using bytes 04H and 05H, care must be taken to preserve the SPF information stored in bytes 00H to 03H. Table 20 Special Programmed Functions (EEPROM address 00H) BIT (MSB: D7) VALUE DESCRIPTION D0 X reserved for future use; logic 0 when read D1 X reserved for future use D2 X reserved for future use D3 X reserved for future use D4 X reserved for future use D5 X reserved for future use D6 X reserved for future use; logic 0 when read D7 1 received data inversion enabled Table 21 Special Programmed Functions (EEPROM address 01H) BIT (MSB: D7) D1 and D0 D3 and D2 D5 and D4 VALUE DESCRIPTION 00 5 ms receiver establishment time (nominal); note 1 01 10 ms 10 15 ms 11 30 ms 00 20 ms oscillator establishment time (nominal); note 1 01 30 ms 10 40 ms 11 50 ms 00 512 bits/s received bit rate 01 1024 bits/s (not used in POCSAG) 10 1200 bits/s 11 2400 bits/s D6 1 synthesizer interface enabled (data is output via ZSD, ZSC and ZLE at decoder switch-on) D7 1 voltage converter enabled Note 1. Since the exact establishment time is related to the programmed bit rate, Table 22 shows the values for the various bit rates. 1997 Jun 24 25 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 22 Establishment time as a function of bit rate NOMINAL ESTABLISHMENT TIME ACTUAL ESTABLISHMENT TIME 512 bits/s 1024 bits/s 1200 bits/s 2400 bits/s 5 ms 5.9 ms (3 bits) 5.9 ms (6 bits) 5.0 ms (6 bits) 5.0 ms (12 bits) 10 ms 11.7 ms (6 bits) 11.7 ms (12 bits) 10.0 ms (12 bits) 10.0 ms (24 bits) 15 ms 15.6 ms (8 bits) 15.6 ms (16 bits) 16.7 ms (20 bits) 16.7 ms (40 bits) 20 ms 23.4 ms (12 bits) 23.4 ms (24 bits) 20.0 ms (24 bits) 20.0 ms (48 bits) 30 ms 31.2 ms (16 bits) 31.2 ms (32 bits) 26.7 ms (32 bits) 26.7 ms (64 bits) 40 ms 39.1 ms (20 bits) 39.1 ms (40 bits) 40.0 ms (48 bits) 40.0 ms (96 bits) 50 ms 46.9 ms (24 bits) 46.9 ms (48 bits) 53.3 ms (64 bits) 53.3 ms (128 bits) Table 23 Special Programmed Functions (EEPROM address 02H) BIT (MSB: D7) VALUE D0 X not used D1 X not used D3 and D2 DESCRIPTION 00 32768 Hz real time clock reference 01 50 Hz square-wave 10 2 Hz 11 1⁄ 60 Hz D4 1 signal test mode enabled (REF and INT outputs) D5 0 burst error correction enabled D7 and D6 XX reserved for future use Table 24 Special Programmed Functions (EEPROM address 03H) BIT (MSB: D7) D1 and D0 VALUE DESCRIPTION 00 2048 Hz acoustic alerter frequency 01 2731 Hz 10 4096 Hz 11 3200 Hz D2 1 automatic POCSAG alert generation enabled D3 X not used D4 X not used D5 X not used 0 INT output polarity: active LOW 1 INT output polarity: active HIGH X not used D6 D7 1997 Jun 24 26 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 7.55 Identifiers are stored in EEPROM rows 2, 3 and 4. Each identifier location consists of 3 bytes in the same column. The identifier number is equal to the column number + 1. Synthesizer programming data Data for programming a PLL synthesizer via pins ZSD, ZSC and ZLE can be stored in row 1 of the EEPROM. Six bytes are available starting from address 08H. Only the last 4 identifiers (numbers 3 to 6) can be programmed as a UPSW. Identifiers 1 and 2 always represent RICs. A UPSW represents an unused address and must differ by more than 6 bits from preamble to guarantee detection. Data is transferred in two serial blocks of 24 bits each, starting with bit 0 (MSB) of block 1. Any unused bits must be programmed at the beginning of a block. 7.56 PCD5003 The standard POCSAG sync word is always enabled and has identifier number 7. Identifier storage allocation Up to 6 different identifiers can be stored in EEPROM for matching with incoming data. The PCD5003 can distinguish two types of identifiers: Table 26 shows the memory locations of the 6 identifiers. The bit allocation per identifier is given in Table 27. • User addresses (RIC) • User Programmable Sync Words (UPSW). Table 25 Synthesizer programming data (EEPROM address 08H to 0DH) ADDRESS (HEX) BIT (MSB: D7) DESCRIPTION 08 D7 to D0 bits 0 to 7 of data block 1 (bit 0 is MSB) 09 D7 to D0 bits 8 to 15 0A D7 to D0 bits 16 to 23 0B D7 to D0 bits 0 to 7 of data block 2 (bit 0 is MSB) 0C D7 to D0 bits 8 to 15 0D D7 to D0 bits 16 to 23 Table 26 Identifier storage allocation (EEPROM address 10H to 25 H) ADDRESS (HEX) BYTE 10 to 15 1 identifier number 1 to 6 18 to 1D 2 identifier number 1 to 6 20 to 25 3 identifier number 1 to 6 1997 Jun 24 DESCRIPTION 27 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 Table 27 Identifier bit allocation BYTE BIT (MSB: D7) 1 D7 to D0 bits 2 to 9 of POCSAG codeword (RIC or UPSW); notes 1 and 2 2 D7 to D0 bits 10 to 17 D7 and D6 3 DESCRIPTION bits 18 and 19 D5 frame number bit FR3 (RIC); note 3 D4 frame number bit FR2 (RIC) D3 frame number bit FR1 (RIC) D2 identifier type selection (0 = UPSW, 1 = RIC); note 4 D1 identifier enable (1 = enabled) D0 reserved for future use, logic 0 when read Notes 1. The bit numbering corresponds with the numbering in a POCSAG codeword: bit 1 is the flag bit (0 = address, 1 = message). 2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0; bits 2 to 19 contain the identifier bit pattern; they are followed by 2 predetermined random (function) bits and the UPSW is completed by 10 CRC error correction bits and an even-parity bit. 3. Bits FR3 to FR1 (MSB: FR3) contain the 3 least significant bits of the 21-bit RIC. 4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0. 7.57 The level-shifted interface lines are: RST, DON, ALC, REF, INT. Voltage doubler An on-chip voltage doubler provides an unregulated DC output for supplying an LCD or a low power microcontroller on output VPO. An external ceramic capacitor of typical 100 nF is required between pins CCN and CCP. The voltage doubler is enabled via SPF programming. The I2C-bus interface lines SDA and SCL can be level-shifted independently of VPR by means of the standard external pull-up resistors. 7.59 7.58 Level-shifted interface A special ‘signal test’ mode is available for monitoring the performance of a receiver circuit together with the front-end of the PCD5003. All interface lines are suited for communication with a microcontroller operating from a higher supply voltage. The external device must have a common reference at VSS of the PCD5003. For this purpose the output of the digital noise filter and the recovered bit clock are made available at outputs REF and INT respectively. All synchronization and decoding functions are normally active. The reference voltage for the level-shifted interface must be applied to input VPR. This could be the on-chip voltage doubler output VPO if required. When the microcontroller has a separate (regulated) supply this separate supply voltage should be connected to VPR. 1997 Jun 24 Signal test mode The ‘signal test’ mode is activated/deactivated by SPF programming. 28 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder 8 8.1 PCD5003 A more accurate reset duration can be realised with an additional external resistor connected to VSS. Recommended minimum values in this case are C = 2.2 nF and R = 100 kΩ (see Fig.15). OPERATING INSTRUCTIONS Reset conditions When the PCD5003 is reset by applying a HIGH-level on input RST, the condition of the decoder is as follows: • OFF status (irrespective of DON input level) 8.3 • REF output frequency 32768 Hz The start-up time for the crystal oscillator may exceed 1 second (typ. 800 ms). It is advised to apply a reset condition at least during the first part of this period. The minimum reset pulse duration tRST is 50 µs. • All internal counters reset • Status/control register reset • INT output at LOW-level During reset the oscillator is active, but clock signals are inhibited internally. Once the reset condition is released the end of the oscillator start-up period can be detected by a rising edge on output INT. • No alert transducers selected • LED, VIB and ATH outputs at LOW level • ATL output high impedance During a reset the voltage converter clock (Vclk) is held at zero. The resulting output voltage drop may cause problems when the external resetting device is powered by the internal voltage doubler. A sufficiently large buffer capacitor between output VPO and VSS must be provided to supply the microcontroller during reset. The voltage at VPO will not drop below VDD − 0.7 V. • SDA, SCL inputs high impedance • Voltage converter disabled. Within tRSU after release of the reset condition (RST LOW) the programmed functions are activated. The settings affecting the external operation of the PCD5003 are as follows: • REF output frequency Immediately after a reset all programmable internal functions will start operating according to a programmed value of 0. During the first 8 full clock cycles (tRSU) all programmed values are loaded from EEPROM. • Voltage converter • INT output polarity • Signal test mode. After reset the receiver outputs RXE and ROE become active immediately, if DON is HIGH and the synthesizer is disabled. When the synthesizer is enabled, RXE and ROE will only become active after the second pulse on ZLE completes the loading of synthesizer data. When input DON is HIGH, the decoder starts operating in ON status immediately following tRSU. 8.2 Power-on reset circuit During power-up of the PCD5003 a HIGH level of minimum duration tRST = 50 µs must be applied to pin RST. This is to prevent EEPROM corruption which might otherwise occur because of the undefined contents of the Control register. The full reset timing is shown in Fig.11. The start-up timing including synthesizer programming is given in Fig.12. 8.4 Initial programming A newly-delivered PCD5002 has EEPROM contents which are undefined. The EEPROM should therefore be programmed, followed by a reset to activate the SPF settings, before any attempt is made to use the device. The reset signal can be applied by the external microcontroller or by an RC power-on reset circuit on pin RST (C to VPR, R to VSS). Such an RC-circuit should have a time constant of at least 3tRST = 150 µs. Input RST has an internal high-ohmic pull-down resistor (nominal 2 MΩ at 2.5 V supply) which could be used together with a suitable external capacitor connected to VPR to create a power-on reset signal. However, since this pull-down resistor varies considerably with processing and supply voltage, the resulting time constant is inaccurate. 1997 Jun 24 Reset timing 29 1997 Jun 24 30 (DON = 1) active LOW active HIGH asynchronous t RST t RSU programmed for 32768 Hz active LOW active HIGH (2) (1) MLC253 Fig.11 Reset timing. Advanced POCSAG Paging Decoder (1) The RXE output signal is shown for disabled synthesizer. When the synthesizer is enabled RXE is held off until after the second pulse on ZLE (programming complete). (2) The ZLE output signal is shown for enabled synthesizer and DON = 1. When DON = 0 output ZLE remains HIGH until ON state is entered (DON = 1 or control register bit D4 = 1). ZLE RXE Vclk INT REF RST handbook, full pagewidth XTAL1 Philips Semiconductors Product specification PCD5003 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder handbook, full pagewidth PCD5003 DON ZSC BLOCK 1 BLOCK 2 ZLE t ZDL1 t ZDL1 tZDL2 t p RXE t clk t ZSU t OSU MLC255 Fig.12 Start-up timing including synthesizer programming. 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VDD supply voltage CONDITIONS VPR ≥ VDD − 0.8 V MIN. MAX. UNIT −0.5 +7.0 V −0.5 +7.0 V VSS − 0.8 VPR + 0.8 V VSS − 0.8 VDD + 0.8 V mW VPR external reference voltage input Vn voltage on pins ALC, DON, RST, SDA and SCL Vn ≤ 7.0 V Vn1 voltage on any other pin Ptot total power dissipation − 250 PO power dissipation per output − 100 mW Tamb operating ambient temperature −25 +70 °C Tstg storage temperature −55 +125 °C 1997 Jun 24 Vn1 ≤ 7.0 V 31 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 10 DC CHARACTERISTICS VDD = 2.7 V; VPR = 2.7 V; VSS = 0 V; Tamb = −25 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage 1.5 2.7 6.0 V VPR external reference voltage input VPR ≥ VDD − 0.8 V 1.5 2.7 6.0 V IDD0 supply current (OFF) note 1 − 25.0 40.0 µA IDD1 supply current (ON) note 1; DON = VDD − 50.0 80.0 µA VPG programming supply voltage voltage converter disabled 2.0 − 6.0 V voltage converter enabled 2.0 − 3.0 V − − 800 µA IPG voltage converter disabled programming supply current Inputs VIL VIH LOW level input voltage RDI, BAT VSS − 0.3VDD V DON, ALC, RST VSS − 0.3VPR V SDA, SCL VSS − 0.3VDD V RDI, BAT 0.7VDD − VDD V DON, ALC, RST 0.7VPR − VPR V 0.7VDD − VPR V 0 − −0.5 µA HIGH level input voltage SDA, SCL IIL LOW level input current pins RDI, BAT,TS1, TS2, DON, ALC and RST Tamb = 25 °C; VI = VSS IIH HIGH level input current Tamb = 25 °C TS1, TS2 VI = VDD 6 − 20 µA RDI, BAT VI = VDD; RXE = 0 6 − 20 µA RDI, BAT VI = VDD; RXE = 1 0 − 0.5 µA DON, ALC, RST VI = VPR 250 500 850 nA Outputs IOL 1997 Jun 24 LOW level output current Tamb = 25 °C VIB, LED VOL = 0.3 V 80 − − µA ATH VOL = 0.3 V 250 − − µA INT, REF VOL = 0.3 V 80 − − µA ZSD, ZSC, ZLE VOL = 0.3 V 70 − − µA ATL VOL = 1.2 V; note 2 13 27 55 mA ROE, RXE VOL = 0.3 V 80 − − µA 32 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder SYMBOL IOH PARAMETER HIGH level output current PCD5003 CONDITIONS MIN. TYP. MAX. UNIT Tamb = 25 °C VIB, LED VOH = 0.7 V −0.6 − −2.4 mA ATH VOH = 0.7 V −3.0 − −11.0 mA INT, REF VOH = 2.4 V −80 − − µA ZSD, ZSC, ZLE VOH = 2.4 V −60 − − µA ATL ATL high-impedance; note 3 − − −0.5 µA ROE, RXE VOH = 2.4 V −600 − − µA Notes 1. Inputs: SDA and SCL pulled up to VDD; all other inputs connected to VSS. Outputs: RXE and ROE logic 0; REF: fref = 1⁄60 Hz; all other outputs open-circuit. Oscillator: no crystal; external clock fosc = 76800 Hz; amplitude: VSS to VDD. Voltage convertor disabled (SPF byte 01, bit D7 = 0; see Table 21). 2. Maximum output current is subject to absolute maximum ratings per output (see Chapter 9). 3. When ATL (open drain output) is not activated it is high impedance. 11 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER) VDD = 2.7 V; VSS = 0 V; VPR = VPO; Tamb = −25 to +70 °C; Cs = 100 nF; voltage converter enabled. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.5 − 3.0 V VDD = 2.7; IPO = 0 − 5.4 − V output voltage VDD = 2.0 V; IPO = −250 µA 3.0 3.5 − V output current VDD = 2.0 V; VPO = 2.7 V −400 −650 − µA VDD = 3.0 V; VPO = 4.5 V −650 −900 − µA VDD supply voltage VPO(0) output voltage; no load VPO IPO 12 OSCILLATOR CHARACTERISTICS Quartz crystal type: MX-1V or equivalent. Quartz crystal parameters: f = 76 800 Hz; RS(max) = 35 kΩ; CL = 8 pF; C0 = 1.4 pF; C1 = 1.5 fF. Maximum overall tolerance: ±200 × 10−6 (includes: cutting, temperature, aging). SYMBOL PARAMETER CXO output capacitance XTAL2 gm oscillator transconductance CONDITIONS VDD = 1.5 V MIN. TYP. MAX. UNIT − 10 − pF 6 12 − µS 13 EEPROM CHARACTERISTICS SYMBOL PARAMETER NEW erase/write cycles tDR data retention time CONDITIONS Tamb = +70 °C; note 1 Note 1. Retention cannot be guaranteed for naked dies (PCD5003U/10). 1997 Jun 24 33 MIN. TYP. MAX. 1000 10000 − 10 − − UNIT years Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 14 AC CHARACTERISTICS VDD = 2.7 V; VSS = 0 V; VPR = 2.7 V; Tamb = 25 °C;. fosc = 76800 Hz. SYMBOLS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock Tclk system clock period − 13.02 − µs D1, D0 = 0 0 − 2048 − Hz D1, D0 = 0 1 − 2731 − Hz D1, D0 = 1 0 − 3200 − Hz fosc = 76800 Hz Call alert frequencies fAL alert frequency SPF byte 03H; bits: − 4096 − Hz fAW warbled alert; modulation frequency alert set-up bit D2 = 1; outputs ATL, ATH, LED − 16 − Hz fAWH warbled alert; high acoustic alert frequency alert set-up bit D2 = 1; outputs ATL, ATH − fAL − Hz fAWL warbled alert; low acoustic alert frequency alert set-up bit D2 = 1; outputs ATL, ATH − 1⁄ − Hz fVBP pulsed vibrator frequency (square-wave) low-level alert − 25 − Hz − 16 − s D1, D0 = 1 1 2fAL Call alert duration tALT alert time-out period tALL ATL output time-out period low-level alert − 4 − s tALH ATH output time-out period high-level alert − 12 − s tVBL VIB output time-out period low -level alert − 4 − s tVBH VIB output time-out period high-level alert − 12 − s tALC alert cycle period − 1 − s tALP alert pulse duration − 125 − ms D3, D2 = 0 0; note 1 − 32768 − Hz D3, D2 = 0 1; note 2 − 50 − Hz D3, D2 = 1 0 − 2 − Hz − 1⁄ − Hz − µs Real time clock reference fref real time clock reference frequency SPF byte 02H; bits: D3, D2 = 1 1 tRFP 1997 Jun 24 real time clock reference pulse duration all reference frequencies except − 50 Hz (square-wave) 34 60 13.02 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder SYMBOLS PARAMETER PCD5003 CONDITIONS MIN. TYP. MAX. UNIT Receiver control − 100 − ns D1, D0 = 0 0 − 5 − ms D1, D0 = 0 1 − 10 − ms D1, D0 = 1 0 − 15 − ms D1, D0 = 1 1 − 30 − ms D3, D2 = 0 0 − 20 − ms D3, D2 = 0 1 − 30 − ms D3, D2 = 1 0 − 40 − ms D3, D2 = 1 1 − 50 − ms tRXT RXE, ROE transition time CL = 5 pF tRXON RXE establishment time (nominal values: actual duration is bit rate dependent, see Table 22) SPF byte 01H; bits: tROON I2C-bus ROE establishment time (nominal values: actual duration is bit rate dependent, see Table 22) SPF byte 01H; bits: interface fSCL SCL clock frequency 0 − 400 kHz tLOW SCL clock low period 1.3 − − µs tHIGH SCL clock HIGH period 0.6 − − µs tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − − ns tr SDA, SCL rise time − − 300 ns tf SDA, SCL fall time note 3 − 300 ns CB capacitive bus line load − − 400 pF tSU;STA START condition set-up time 0.6 − − µs tHD;STA START condition hold time 0.6 − − µs tSU;STO STOP condition set-up time 0.6 − − µs tRST external reset duration 50 − − µs tRSU set-up time after reset oscillator running − − 105 µs tOSU set-up time after switch-on oscillator running − − 4 ms tTDI data input transition time see Fig.13 − − 100 µs tDI1 data input logic 1 duration see Fig.13 tBIT − ∞ tDI0 data input logic 0 duration see Fig.13 tBIT − ∞ Reset Data input POCSAG data timing (512 bits/s) fDI data input rate 512 − bits/s tBIT bit duration − 1.9531 − ms tCW codeword duration − 62.5 − ms tPA preamble duration 1125 − − ms tBAT batch duration − 1062.5 − ms 1997 Jun 24 SPF byte 01H; bits D5, D4 = 0 0 − 35 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder SYMBOLS PARAMETER PCD5003 CONDITIONS MIN. TYP. MAX. UNIT POCSAG data timing (1200 bits/s) fDI data input rate SPF byte 01H; bits D5, D4 = 1 0 − 1200 − bits/s tBIT bit duration − 833.3 − µs tCW codeword duration − 26.7 − ms tPA preamble duration 480 − − ms tBAT batch duration − 453.3 − ms POCSAG data timing (2400 bits/s) fDI data input rate SPF byte 01H; bits D5, D4 = 1 1 − 2400 − bits/s tBIT bit duration − 416.6 − µs tCW codeword duration − 13.3 − ms tPA preamble duration 240 − − ms tBAT batch duration − 226.6 − ms Synthesizer control tZSU synthesizer set-up duration oscillator running; note 4 1 − 2 bits fZSC output clock frequency note 5 − 38400 − Hz tZCL clock pulse duration − 13.02 − µs tZSD data bit duration − 26.04 − µs tZDS data bit set-up time − 13.02 − µs tZDL1 data load enable delay − 91.15 − µs tZLE load enable pulse duration − 13.02 − µs tZDL2 inter block delay − 117.19 − µs note 5 Notes 1. 32768 Hz reference signal: 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods (pulse duration: tRFP). The timing is shown in Fig.14. 2. 50 Hz reference signal: square-wave. 3. The fall time may be faster than prescribed in the I2C-bus specification for very low load capacitance values. To increase the fall time external capacitance is required. 4. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits. 5. Nominal values; pause in 12th data bit (see Table 12). 1997 Jun 24 36 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder handbook, halfpage PCD5003 tDI1 tDI0 t TDI MGL100 Fig.13 Data input timing. t RFP handbook, full pagewidth t RFP 2t RFP MLC278 Fig.14 Timing of the 32 768 Hz reference signal. 1997 Jun 24 37 1997 Jun 24 V 38 XTAL2 2.2 MΩ 76.8 kHz XTAL1 VIB BATTERY NEGATIVE VSS n.c. TS1 VDD CCP CCN PCD5003 DECODER LED Cs 100 nF n.c. TS2 SCL SDA ALC REF INT DON VPO VPR RST (2) 4.7 kΩ 4.7 kΩ I2C-bus (2) (1) (1) Fig.15 Typical application example (display pager). LCD DRIVER V V LCD DRIVER V V V V function keys MLC256 LCD MICROCONTROLLER 10 µF Advanced POCSAG Paging Decoder (1) Value depends on number of devices attached. (2) Values should be chosen to give a time constant of at least 150 µs. C = 2.2 nF and R = 100 kΩ are recommended. 10 pF ZLE V ZSD ROE LATCH PWR CTRL RXE PWR CTRL ZSC V VCO BAT ATL ATH RDI BAT REF DATA OUT FREQUENCY DATA SYNTHESIZER CLK V OSC RECEIVER ANT M handbook, full pagewidth BATTERY POSITIVE Philips Semiconductors Product specification PCD5003 15 APPLICATION INFORMATION Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 16 PACKAGE OUTLINE LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1 c y X 24 A 17 25 16 ZE e Q E HE A A2 A 1 (A 3) wM θ bp Lp L pin 1 index 32 9 detail X 8 1 e ZD v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 7.1 6.9 0.8 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.69 0.59 0.2 0.25 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-06-29 95-12-19 SOT358 -1 1997 Jun 24 EUROPEAN PROJECTION 39 o 7 0o Philips Semiconductors Product specification Advanced POCSAG Paging Decoder If wave soldering cannot be avoided, the following conditions must be observed: 17 SOLDERING 17.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 17.2 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 17.4 Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jun 24 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 17.3 PCD5003 40 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder PCD5003 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 20 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jun 24 41 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder NOTES 1997 Jun 24 42 PCD5003 Philips Semiconductors Product specification Advanced POCSAG Paging Decoder NOTES 1997 Jun 24 43 PCD5003 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 437027/25/06/pp44 Date of release: 1997 Jun 24 Document order number: 9397 750 02433