INTEGRATED CIRCUITS DATA SHEET SAA7157 Clock signal generator circuit for digital TV systems (SCGC) Product specification File under Integrated Circuits, IC02 May 1992 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 FEATURES • Clock generation suitable for digital TV systems (line-locked) • PLL frequency multiplier to generate 4 times of input frequency • Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency) • PLL mode or VCO mode selectable • Reset control and power fail detection • Suitable for applications with feature box and picture memory GENERAL DESCRIPTION The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator mode (VCO). QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage (pin 5) 4.5 5.0 5.5 V VDDD digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V IDDA analog supply current 3 - 9 mA IDDD digital supply current 10 - 60 mA VLFCO LFCO input voltage (peak-to-peak value) 1 - VDDA V fi input frequency range 6.0 - 7.25 MHz VI input voltage LOW input voltage HIGH 0 2.0 - 0.8 VDDD V V VO output voltage LOW output voltage HIGH 0 2.6 - 0.6 VDDD V V Tamb operating ambient temperature range 0 - 70 °C ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE SAA7157 20 DIL plastic SOT146(1) SAA7157T 20 mini-pack (SO20) plastic SOT163A(2) Note 1. SOT146-1; 1996 December 17. 2. SOT163-1; 1996 December 17. May 1992 2 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) VDDA handbook, full pagewidth MS VDDD1 VDDD2 5 1 LOOP FILTER SAA7157 8 17 VCO MS = LOW FREQUENCY DIVIDER 1:2 SAA7157 FREQUENCY DIVIDER 1:2 PHASE DETECTOR LFCO2 CE 11 PRE-FILTER AND PULSE SHAPER LL1.5A (LL27A) 10 LL1.5B (LL27B) 14 20 15 DELAY LFCO 7 POWER-ON RESET 12 LL3A LL3B CREF RESN 19 2 16 3 4 6, 9, 13, 18 LFCOSEL PORD VSSA VSSD MEH452 Fig.1 Block diagram. FUNCTIONAL DESCRIPTION Mode select MS The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family consisting of an 8-bit analog-to-digital converter (ADC8), digital video multistandard decoder (DMSD2) and video enhancement and D/A processor circuit (VEDA). Optional extras (feature box, video memory etc.) can be driven via external buffers, advantageous for a digital TV system based on display standard conversion concepts. The 6.75 MHz input signal LFCO (triangular waveform) coming from the DMSD or LFCO2 is multiplied to 27 MHz by the PLL (including phase detector, loop filter, VCO and frequency divider) and output on LL1.5A (pin 7) and LL1.5B (pin 10). The 13.5 MHz frequencies are generated by dividers using ratio of 1:2 and are output on LL3A (pin 14) and LL3B (pin 20). The rectangular output signals have 50% duty factor. Outputs with equal frequency may be connected together externally. The clock outputs go HIGH during power-on reset (and chip enable) to ensure that no output clock signals are available before the PLL has locked-on. The LFCO input signal is directly connected to the VCO at MS = HIGH. The circuit operates as an oscillator and frequency divider. This function is not tested. May 1992 Source select LFCOSEL Line frequency control signal (LFCO) is selected by LFCOSEL input. LFCOSEL = LOW: signal from LFCO (pin 11) is selected. LFCOSEL = HIGH: signal from LFCO2 (pin 19) is selected. This function is not tested. Chip enable CE The buffer outputs are enabled and RESN is set to HIGH by CE = HIGH (Fig.4). CE = LOW sets the clock outputs HIGH and RESN output LOW. 3 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 CREF output TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency. Power-on reset Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied to reset other circuits of this digital TV system. The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH. PINNING SYMBOL PIN DESCRIPTION MS 1 mode select input (LOW = PLL mode) CE 2 chip enable /reset (HIGH = outputs enabled) PORD 3 power-on reset delay, dependent on external capacitor VSSA 4 analog ground (0 V) VDDA 5 analog supply voltage (+5 V) VSSD1 6 digital ground 1 (0 V) LL1.5A 7 line-locked clock output signal 1.5A (4 times fLFCO) VDDD1 8 digital supply voltage 1 (+5 V) VSSD2 9 digital ground 2 (0 V) LL1.5B 10 line-locked clock output signal 1.5B (4 times fLFCO) LFCO 11 line-locked frequency control input signal 1 RESN 12 reset output (active-LOW, Fig.4) VSSD3 13 digital ground 3 (0 V) LL3A 14 line-locked clock output signal 3A (2 times fLFCO) CREF 15 clock reference output, qualifier signal (2 times fLFCO) LFCOSEL 16 LFCO source select (LOW = LFCO selected) (1) VDDD2 17 digital supply voltage 2 (+5 V) VSSD4 18 digital ground 4 (0 V) LFCO2 19 line-locked frequency control input signal 2(1) LL3B 20 line-locked clock output signal 3B (2 times fLFCO) Note 1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency. May 1992 4 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 PIN CONFIGURATION Fig.2 Pin configuration. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together connected. SYMBOL PARAMETER MIN. −0.5 MAX. UNIT VDDA analog supply voltage (pin 5) VDDD digital supply voltage (pins 8 and 17) −0.5 7.0 V Vdiff GND difference voltage VDDA − VDDD - ±100 mV VO output voltage (IOM = 20 mA) −0.5 VDDD V 7.0 V Ptot total power dissipation (DIL20) 0 1.1 W Tstg storage temperature range −65 150 °C Tamb operating ambient temperature range 0 70 °C VESD handling(1) - tbf V electrostatic for all pins Notes 1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal handling precautions appropriate to “Handling MOS devices”. May 1992 5 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 CHARACTERISTICS VDDA = 4.5 to 5.5 V; VDDD = 4.5 to 5.5 V; fLFCO = 6.0 to 7.25 MHz and Tamb = 0 to 70 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. 4.5 TYP. 5.0 MAX. 5.5 UNIT VDDA analog supply voltage (pin 5) V VDDD digital supply voltage (pins 8 and 17) 4.5 5.0 5.5 V IDDA analog supply current (pin 5) 3 − 9 mA IDDD digital supply current (I8 + I17) note 1 10 − 60 mA Vreset power-on reset threshold voltage Fig.4 − 3.5 − V Input LFCO (pin 11) V11 DC input voltage 0 − VDDA V Vi input signal (peak-to-peak value) 1 − VDDA V fLFCO input frequency range 6.0 − 7.25 MHz C11 input capacitance − − 10 pF Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3 VIL input voltage LOW 0 − 0.8 V VIH input voltage HIGH 2.0 − VDDD V fLFCO2 input frequency range for LFCO2 ILI input leakage current CI 6.0 − 7.25 MHz LFCOSEL 50 − 150 µA others − − 10 µA − − 5 pF input capacitance Output RESN (pin 12) VOL output voltage LOW IO L = 2 mA 0 − 0.4 V VOH output voltage HIGH IOH = −0.5 mA 2.4 − VDDD V td RESN delay time C3 = 0.1 µF; Fig.4 20 − 200 ms 0 − 0.6 V VDDD V Output CREF (pin 15) VOL output voltage LOW IO L = 2 mA VOH output voltage HIGH IOH = −0.5 mA 2.4 − fCREF output frequency CREF Fig.3 − 2 fLFCO(2) CL output load capacitance 15 − 40 pF tSU set-up time Fig.3; note 1 12 − − ns tHD hold time Fig.3; note 1 4 − − ns May 1992 6 MHz Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SYMBOL PARAMETER SAA7157 CONDITIONS MIN. TYP. MAX. UNIT Output signals LL1.5A, LL1.5B, LL3A and LL3B (pins 7, 10, 14, and 20); note 3 VOL output voltage LOW IO L = 2 mA 0 - 0.6 V VOH output voltage HIGH IOH = −0.5 mA 2.6 - VDDD V tcomp composite rise time Fig.3; notes 1 and 2 - - 8 ns fLL output frequency LL1.5A Fig.3 - 4 fLFCO(2) MHz output frequency LL1.5B - 4 fLFCO(2) MHz output frequency LL3A - 2 fLFCO(2) MHz - 2 fLFCO(2) tr, tf rise and fall times output frequency LL3B note 1; Fig.3 - - 5 ns tLL duty factor LL1.5A, LL1.5B, LL3A and LL3B (mean values) note 1; Fig.3; at 1.5 V level 43 50 57 % MHz Notes 1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together. 2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more than ±2 ns if output loads are matched within 20%. 3. MS and LFCO2 functions not tested. 2.4 V handbook, full pagewidth CREF 0.6 V tSU tHD tHD tLL1.5 tLL1.5H tLL1.5L 2.6 V LL1.5A LL1.5B 1.5 V 0.6 V tr tf tLL3 tLL3H tLL3L 2.6 V LL3A LL3B 1.5 V 0.6 V tcomp tf Fig.3 Output timing. May 1992 7 tr MEH456 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 +3.5 V handbook, full pagewidth VDDA VDDD 0V oscillation disturbed power-on LFCO oscillation td td RESN normal operation normal operation LL1.5A LL1.5B LL3A LL3B MEH457 PLL lock-on power failure starts a new reset procedure clock HIGH during internal reset reset time Fig.4 Reset procedure. handbook, full pagewidth VDDD VDDD VSSD VSSD 1 2 16 19 MS CE LFCOSEL LFCO2 7 10 14 15 LL1.5A 20 LL1.5B LL3A LL3B CREF VDDD 11 12 LFCO RESN VSSD Fig.5 Internal circuit. May 1992 8 MEH468 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 May 1992 REFERENCES IEC JEDEC EIAJ SC603 9 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.419 0.043 0.050 0.055 0.394 0.016 inches 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC May 1992 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 10 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating May 1992 11 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) SAA7157 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. May 1992 12