INTEGRATED CIRCUITS DATA SHEET TDA9855 I2C-bus controlled BTSC stereo/SAP decoder and audio processor Product specification Supersedes data of July 1994 File under Integrated Circuits, IC02 1997 Nov 04 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 FEATURES • Quasi alignment-free BTSC stereo decoder due to automatic adjustment of channel separation via I2C-bus • High integration level with automatically tuned integrated filters • Input level adjustment I2C-bus controlled • Alignment-free SAP processing GENERAL DESCRIPTION • dbx noise reduction circuit The TDA9855 is a bipolar-integrated BTSC stereo/SAP decoder with hi-fi audio processor (I2C-bus controlled) for application in TV sets. • I2C-bus transceiver. Audio processor • Selector for internal and external signals (line in) • Automatic volume level control • Subwoofer or surround output with separate volume control • Volume control • Special loudness characteristic automatically controlled in combination with volume setting • Bass and treble control • Audio signal zero-crossing detection between any volume step switching • Mute control at audio signal zero-crossing. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA9855 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 TDA9855WP PLCC68 plastic leaded chip carrier; 68 leads SOT188-2 LICENSE INFORMATION A license is required for the use of this product. For further information, please contact COMPANY THAT Corporation 1997 Nov 04 BRANCH ADDRESS Licensing Operations 734 Forest St. Marlborough, MA 01752 USA Tel.: (508) 229-2500 Fax: (508) 229-2590 Tokyo Office 405 Palm House, 1-20-2 Honmachi Shibuya-ku, Tokyo 151 Japan Tel.: (03) 3378-0915 Fax: (03) 3374-5191 2 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 8.0 8.5 9.0 V ICC supply current 50 75 95 mA VCOMP(rms) input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − 250 − mV VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − 500 − mV GLA input level adjustment control maximum gain − 4 − dB maximum attenuation − −3.5 − dB αcs stereo channel separation fL = 300 Hz; fR = 3 kHz 25 35 − dB THDL,R total harmonic distortion L + R fi = 1 kHz − 0.2 − % VI, O(rms) signal handling (RMS value) THD < 0.5% 2 − − V AVL control range −15 − +6 dB Gc volume control range −71 − +16 dB LB maximum loudness boost fi = 40 Hz − 17 − dB Gbass bass control range fi = 40 Hz −12 − +16.5 dB Gtreble treble control range fi = 15 kHz −12 − +12 dB Gs subwoofer control range fi = 40 Hz −14 − +14 dB S/N signal-to-noise ratio line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) − 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA CCIR noise weighting filter (peak value) − 94 − dB DIN noise weighting filter (RMS value) − 107 − dBA audio section; Vo = 2 V (RMS); gain = 0 dB 1997 Nov 04 3 1997 Nov 04 C1 4 C17 C18 (30) 23 SAP DEMODULATOR INPUT LEVEL ADJUST (31) 24 34 (46) C19 C21 R7 R6 (29) (25) 22 20 STEREO /SAP SWITCH 35 (47) 37 (49) LOR C20 STEREO ADJUST DEMATRIX + LINEOUT SELECT 36 (48) C16 38 (50) C7 C6 LIL D1 VCC 10 (14) C28 C49 C15 C34 (33, (39) (15) 34) 30 11 25 SUPPLY AUTOMATIC VOLUME AND LEVEL CONTROL (18) (37) 13 28 40 (52) VCC C9 43 (56) (6) 5 46 (59) C12 R3 C30 C29 R4 VIL (12) 8 R5 C31 (11) 7 VOLUME LEFT LOUDNESS CONTROL 50 (66) BASS RIGHT CONTROL 51 (67) C13 C32 (3) 2 (4) 3 BASS LEFT CONTROL ZERO CROSSING VOLUME RIGHT LOUDNESS CONTROL VIR 45 (58) R2 TDA9855 44 (57) C45 C11 (35) (36) (13) 28 27 9 LOGIC, I2CTRANCEIVER EFFECTS 42 (55) C8 MAD SDA SCL Fig.1 Block diagram. External Input Left (EIL) C47 C26 (16) (19) 12 14 INPUT SELECT 41 39 (54) (51) LIR C10 C22 C23 C24 C25 C37 C27 LOL (27) (24) (23) (22) (21) (20) 21 19 18 17 16 15 DBX CERAMIC RESONATOR MURATA CSB503F58 Q1 handbook, full pagewidth 29 (38) 33 (43) C5 STEREO DECODER 32 (41) R1 C4 C33 (1) 1 TREBLE LEFT CONTROL SUBWOOFER MATRIX, VOLUME SURROUND TREBLE RIGHT CONTROL 52 (68) C14 MHA837 (7) 6 (5) 4 (65) 49 (63) 47 C39 C40 C35 C36 OUTL OUTS OUTR I2C-bus controlled BTSC stereo/SAP decoder and audio processor The numbers given in parenthesis refer to the TDA9855WP version. COMP 31 (40) C2 C3 External Input Right (EIR) Philips Semiconductors Product specification TDA9855 BLOCK DIAGRAM Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Component list Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1. COMPONENTS VALUE TYPE REMARK C1 10 µF electrolytic 63 V C2 470 nF foil − C3 4.7 µF electrolytic 63 V C4 220 nF foil − C5 10 µF electrolytic 63 V; Ileak < 1.5 µA C6 2.2 µF electrolytic 16 V C7 4.7 µF electrolytic 16 V C8 15 nF foil ±5% C9 15 nF foil ±5% C10 2.2 µF electrolytic 63 V C11 8.2 nF foil or ceramic ±5% SMD 2220/1206 C12 150 nF foil ±5% C13 33 nF foil ±5% C14 5.6 nF foil or ceramic ±5% SMD 2220/1206 C15 100 µF electrolytic 16 V C16 4.7 µF electrolytic 63 V 63 V C17 4.7 µF electrolytic C18 100 nF foil C19 10 µF electrolytic 63 V C20 4.7 µF electrolytic 63 V C21 47 nF foil ±5% C22 1 µF electrolytic 63 V C23 1 µF electrolytic 63 V C24 10 µF electrolytic 63 V ±10% C25 10 µF electrolytic 63 V ±10% C26 2.2 µF electrolytic 16 V C27 2.2 µF electrolytic 63 V C28 4.7 µF electrolytic 63 V ±10% C29 2.2 µF electrolytic 16 V C30 8.2 nF foil or ceramic ±5% SMD 2220/1206 C31 150 nF foil ±5% C32 33 nF foil ±5% C33 5.6 nF foil or ceramic ±5% SMD 2220/1206 C34 100 µF electrolytic 16 V C35 150 nF foil ±5% C36 4.7 µF electrolytic 16 V C37 4.7 µF electrolytic 16 V C39 4.7 µF electrolytic 16 V C40 4.7 µF electrolytic 16 V 1997 Nov 04 5 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 COMPONENTS VALUE TYPE REMARK C45 2.2 µF electrolytic 16 V C47 220 µF electrolytic 25 V C49 100 nF foil or ceramic SMD 1206 D1 − − general purpose diode R1 2.2 kΩ − − R2 20 kΩ − − R3 2.2 kΩ − − R4 20 kΩ − − R5 2.2 kΩ − − R6 8.2 kΩ − ±2% R7 160 Ω − ±2% Q1 CSB503F58 radial leads CSB503JF958 alternative as SMD PINNING PINS SYMBOL TL DESCRIPTION PLCC68 SDIP52 1 1 treble control capacitor, left channel n.c. 2 − not connected B1L 3 2 bass control capacitor, left channel B2L 4 3 bass control capacitor, left channel OUTS 5 4 output subwoofer or output surround sound MAD 6 5 programmable address bit (module address) OUTL 7 6 output, left channel 8 to 10 − not connected LDL 11 7 input loudness, left channel VIL 12 8 input volume control, left channel EOL 13 9 output effects, left channel CAV 14 10 automatic volume control capacitor Vref 15 11 reference voltage 0.5VCC LIL 16 12 input line, left channel n.c. n.c. 17 − not connected AVL 18 13 input automatic volume control, left channel SOL 19 14 output selector, left channel LOL 20 15 output line control, left channel CTW 21 16 capacitor timing wideband for dbx CTS 22 17 capacitor timing spectral for dbx CW 23 18 capacitor wideband for dbx CS 24 19 capacitor spectral for dbx VEO 25 20 variable emphasis output for dbx 1997 Nov 04 6 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 PINS SYMBOL DESCRIPTION PLCC68 SDIP52 n.c. 26 − not connected VEI 27 21 variable emphasis input for dbx n.c. 28 − not connected CNR 29 22 capacitor noise reduction for dbx CM 30 23 capacitor mute for SAP CDEC 31 24 capacitor DC-decoupling for SAP n.c. 32 − not connected AGND 33 − analog ground DGND 34 − digital ground GND − 25 ground SDA 35 26 serial data input/output (I2C-bus) SCL 36 27 serial clock input (I2C-bus) VCC 37 28 supply voltage COMP 38 29 composite input signal VCAP 39 30 capacitor for electronic filtering of supply CP1 40 31 capacitor for pilot detector CP2 41 32 capacitor for pilot detector n.c. 42 − not connected CPH 43 33 capacitor for phase detector n.c. 44, 45 − not connected CADJ 46 34 capacitor for filter adjustment CER 47 35 ceramic resonator CMO 48 36 capacitor DC-decoupling mono CSS 49 37 capacitor DC-decoupling stereo/SAP LOR 50 38 output line control, right channel SOR 51 39 output selector, right channel AVR 52 40 input automatic volume control, right channel n.c. 53 − not connected LIR 54 41 input line control, right channel CPS2 55 42 capacitor 2 pseudo function CPS1 56 43 capacitor 1 pseudo function EOR 57 44 output effects, right channel VIR 58 45 input volume control, right channel LDR 59 46 input loudness, right channel n.c. 60 to 62 − not connected OUTR 63 47 output, right channel n.c. 64 48 not connected SW 65 49 filter capacitor for subwoofer 1997 Nov 04 7 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 PINS SYMBOL DESCRIPTION 61 n.c. 62 n.c. n.c. 10 60 n.c. LDL 11 59 LDR VIL 12 58 VIR EOL 13 57 EOR CAV 14 56 CPS1 Vref 15 55 CPS2 LIL 16 54 LIR n.c. 17 53 n.c. TDA9855H AVL 18 52 AVR SOL 19 51 SOR LOL 20 50 LOR CTW 21 49 CSS CTS 22 48 CMO CW 23 47 CER CS 24 46 CADJ 8 CPH 43 n.c. 42 CP2 41 CP1 40 VCAP 39 COMP 38 VCC 37 SCL 36 SDA 35 DGND 34 AGND 33 n.c. 32 CDEC 31 CM 30 44 n.c. CNR 29 n.c. 26 n.c. 28 45 n.c. VEI 27 VEO 25 Fig.2 Pin configuration (PLCC version). 1997 Nov 04 63 OUTR 64 n.c. 65 SW TL 1 66 B2R n.c. 2 67 B1R B1L 3 handbook, full pagewidth 68 TR B2L 4 treble control capacitor OUTS 52 5 68 MAD TR 6 bass control capacitor, right channel OUTL bass control capacitor, right channel 51 7 50 67 n.c. 66 B1R 8 B2R n.c. SDIP52 9 PLCC68 MHA836 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 FUNCTIONAL DESCRIPTION Decoder INPUT LEVEL ADJUSTMENT The composite input signal is fed to the input level adjustment stage. In order to compensate tolerances of the FM demodulator which supplied the composite input signal, the TDA9855 provides an input level adjustment stage. The control range is from −3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 3 of Tables 5 and 6 and the level adjust setting of Table 22 allows an optimum signal adjustment during the set alignment in the production line. This value has to be stored in a non-volatile memory. The maximum input signal voltage is 2 V (RMS). handbook, halfpage TL 1 52 TR B1L 2 51 B1R B2L 3 50 B2R OUTS 4 49 SW MAD 5 48 n.c. OUTL 6 47 OUTR LDL 7 46 LDR VIL 8 45 VIR EOL 9 44 EOR CAV 10 43 CPS1 Vref 11 42 CPS2 LIL 12 STEREO DECODER The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation can be adjusted by an automatic procedure or manually. For a detailed description see Section “Adjustment procedure”. The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds can be selected via the I2C-bus (see Table 24). 41 LIR AVL 13 40 AVR TDA9855 SOL 14 39 SOR LOL 15 38 LOR CTW 16 37 CSS CTS 17 36 CMO CW 18 35 CER Cs 19 34 CADJ VEO 20 33 CPH VEI 21 32 CP2 CNR 22 31 CP1 CM 23 30 VCAP CDEC 24 29 COMP GND 25 28 VCC SDA 26 27 SCL SAP DEMODULATOR The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH (fH = horizontal frequency) band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes internal noise and field strength detectors that mute the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2). MHA835 SWITCH The stereo/SAP switch feeds either the L − R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/line out select circuit. Table 21 shows the different switch modes provided at the output pins LOR and LOL. Fig.3 Pin configuration (SDIP version). 1997 Nov 04 9 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 control of each channel. The volume control blocks operate in combination with the loudness control. The filter is linear when maximum gain for volume control is selected. The filter characteristic changes automatically over a range of 28 dB down to a setting of −12 dB. At −12 dB volume control the maximum loudness boost is obtained. The filter characteristic is determined by external components. The proposed application provides a maximum boost of 17 dB for bass and 4.5 dB for treble. The loudness may be switched on or off via I2C-bus control (see Table 14). The left and right volume control stages include two independent zero-crossing detectors. In the zero-crossing mode a change in volume is automatically activated but not executed. The execution is enabled at the next zero-crossing of the signal. If a new volume step is activated before the previous one has been processed, the previous value will be executed first, and then the new value will be activated. If no zero-crossing occurs the next volume transmission will enforce the last activated volume setting. dbx DECODER The circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block. INTEGRATED FILTERS The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit. Audio processor SELECTOR The selector allows selecting either the internal line out signals LOR or LOL (dematrix output) or the external line in signals LIR and LIL and combines the left and right signals in several modes (see Table 12). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is AC-coupled to the automatic volume level control circuit via pins SOR/SOL and AVR/AVL to avoid offset voltages. The zero-crossing mode is realized between adjoining steps and between any steps, but not from any step to mute. In this case the GMU bit is required for use. In case only one channel has to be muted, two steps are necessary. The first step is a transmission of any step to −71 dB and the second step is the −71 dB step to mute mode. The step of −71 dB to mute mode has no zero-crossing but this is not relevant. This procedure has to be provided by software. AUTOMATIC VOLUME LEVEL CONTROL The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range of 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and due to changes in the programme material. The function can be switched off. To avoid audible ‘plops’ during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay time can be changed via the I2C-bus (see notes 7 and 8 of Chapter “Characteristics”). BASS CONTROL A single external 33 nF capacitor for each channel in combination with a linear operational amplifier and internal resistors provides a bass control range of +16.5 to −12 dB in steps of 1.5 dB at low frequencies (40 Hz). Internally the basic step width is 3 dB, with intermediate steps obtained by a toggle function that provides an additional 1.5 dB boost or attenuation (see Table 9). It should be noted that both loudness and bass control together result in a maximum bass boost of 34.5 dB for low volume steps. EFFECTS TREBLE CONTROL The audio processor section offers the following mode selections: linear stereo, pseudo stereo, spatial stereo and forced mono.The spatial mode provides an antiphase crosstalk of 30% or 52% (switchable via the I2C-bus; see Table 18). The adjustable range of the treble control stage is from −12 to +12 dB in steps of 3 dB. The filter characteristic is determined by an external 5.6 nF capacitor for each channel. The logic circuitry is arranged in a way that the same data words (06H to 16H) can be used for both tone controls if a bass control range from −12 to +12 dB and a treble control range from −12 to +12 dB with 3 dB steps are used (see Tables 9 and 10). VOLUME/LOUDNESS The volume control range is from +16 dB to −71 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume 1997 Nov 04 10 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 wideband expander is performed via the stereo channel separation adjust. SUBWOOFER; SURROUND SOUND CONTROL The subwoofer or the surround mode can be activated with the control bit SUR (see Table 6). A low bit provides an output signal 1⁄2(L + R) in subwoofer mode, a high bit selects surround mode and provides an output signal 1⁄ (L − R). The signal is fed through a volume control stage 2 with a range from +14 to −14 dB in 2 dB steps on top of the main channel control to the output pin OUTS. The last setting is the mute position (see Table 11). The capacitor C35 at pin SW provides a 230 Hz low-pass filter in subwoofer mode. In surround mode this capacitor should be disconnected. If balance is not in mid position the selected left and right output levels will be combined. AUTOMATIC ADJUSTMENT PROCEDURE • Capacitors of external inputs EIL and EIR must be grounded • Composite input signal L = 300 Hz, R = 3.1 kHz, 14% modulation for each channel; volume gain +16 dB via the I2C-bus; to avoid annoying sound level set GMU bit to logic 1 during adjustment procedure • Effects, AVL, loudness off • Selector setting SC0, SC1 and SC2 = 0, 0, 0 (see Table 12) • Line out setting bits: STEREO = 1, SAP = 0 (see Table 21) MUTE The mute function can be activated independently with the last step of volume or subwoofer/surround control at the left, right or centre output. By setting the general mute bit GMU via the I2C-bus all audio part outputs are muted. All channels include an independent zero-crossing detector. The zero-crossing mute feature can be selected via bit TZCM: • Start adjustment by transmission ADJ = 1 in register ALI3; the decoder will align itself • After 1 second, stop alignment by transmitting ADJ = 0 in register ALI3 read the alignment data by an I2C-bus read operation from ALR1 and ALR2 (see Chapter “I2C-bus protocol”) and store it in a non-volatile memory; the alignment procedure overwrites the previous data stored in ALI1 and ALI2 TZCM = 0: forced mute with direct execution TZCM = 1: execution in time with signal zero-crossing. • Disconnect the capacitors of external inputs from ground. In the zero-crossing mode a change of the GMU bit is activated but not executed. The execution is enabled at the next zero-crossing of the signal. To avoid a large delay of mute switching, when very low frequencies are processed, or the output signal amplitude is lower than the DC offset voltage, the following I2C-bus transmissions are needed: MANUAL ADJUSTMENT Manual adjustment is necessary when no dual tone generator is available (e.g. for service). • Spectral and wideband data have to be set to 10000 (middle position for adjustment range) A first transmission for mute execution A second transmission approximately 100 ms later, which must switch the zero-crossing mode to forced mute (TZCM = 0) • Composite input L = 300 Hz; 14% modulation A third transmission to reactivate the zero-crossing mode (TZCM = 1). This transmission can take place immediately, but must follow before the next mute execution. • Adjust channel separation by varying spectral data • Adjust channel separation by varying wideband data • Composite input L = 3 kHz; 14% modulation • Iterative spectral/wideband operation for optimum adjustment • Store data in non-volatile memory. Adjustment procedure After every power-on, the alignment data and the input level adjustment data must be loaded from the non-volatile memory. COMPOSITE INPUT LEVEL ADJUSTMENT Apply the composite signal (from the FM demodulator) with 100% modulation (25 kHz deviation) L + R; fi = 300 Hz. Set input level control via the I2C-bus monitoring line output (500 mV ±20 mV). Store the setting in a non-volatile memory. Adjustment of the spectral and 1997 Nov 04 TIMING CURRENT FOR RELEASE RATE Due to possible internal and external spreading, the timing current can be adjusted via the I2C-bus (see Table 25) as recommended by dbx. 11 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Requirements for the composite input signal to ensure correct system performance SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT COMPL+R(rms) composite input level for 100% modulation L + R; 25 kHz deviation; fi = 300 Hz; RMS value measured at pin COMP 162 250 363 mV ∆COMP composite input level spreading under operating conditions Tamb = −20 to +70 °C; aging; power supply influence −0.5 − +0.5 dB Zo output impedance note 1 − low-ohmic 5 kΩ flf low frequency roll-off 25 kHz deviation L + R; −2 dB − − 5 Hz fhf high frequency roll-off 25 kHz deviation L + R; −2 dB 100 − − kHz THDL,R total harmonic distortion L + R fi = 1 kHz; 25 kHz deviation − − 0.5 % fi = 1 kHz; 125 kHz deviation; note 2 − − 1.5 % critical picture modulation 44 − − dB with sync only S/N signal-to-noise ratio L + R/noise CCIR 468-2 weighted quasi peak; L + R; 25 kHz deviation; fi = 1 kHz; 75 µs de-emphasis 54 − − dB αSB side band suppression mono into unmodulated SAP carrier; SAP carrier/side band mono signal: 25 kHz deviation, 46 fi = 1 kHz; side band: SAP carrier frequency ±1 kHz − − dB αSP spectral spurious attenuation L + R/spurious 50 Hz to 100 kHz; 40 mainly n × fH; no de-emphasis; L + R; 25 kHz deviation, f = 1 kHz as reference − − dB Notes 1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Zo and the composite input impedance (see Chapter “Characteristics”, Section INPUT LEVEL ADJUSTMENT CONTROL) must be taken into account. 2. In order to prevent clipping at over-modulation (maximum deviation in the BTSC system for 100% modulation is 73 kHz). 1997 Nov 04 12 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 0 9.5 V Vn voltage of all other pins with respect to pin GND 0 VCC V Tamb operating ambient temperature −20 +70 °C Tstg storage temperature Vesd electrostatic handling −65 +150 °C note 1 −2000 +2000 V note 2 −300 +300 V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ. 2. Charge device model: C = 200 pF; R = 0 Ω. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1997 Nov 04 PARAMETER CONDITIONS VALUE UNIT SOT247-1 43 K/W SOT188-2 38 K/W thermal resistance from junction to ambient 13 in free air Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 CHARACTERISTICS All voltages are measured relative to GND; VCC = 8.5 V; source resistance Rs ≤ 600 Ω; output load RL ≥ 10 kΩ; CL ≤ 2.5 nF; AC-coupled; fi = 1 kHz; Tamb = 25 °C; volume gain control Gc = 0 dB; bass linear; treble linear; loudness off; AVL off; effects linear; composite input signal in accordance with BTSC standard; see Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General VCC supply voltage 8.0 ICC supply current 50 75 95 mA VDC DC voltage at signal handling pins − 1⁄ − V maximum gain − 4.0 − dB maximum attenuation − −3.5 − dB 8.5 2VCC 9.0 V Decoder section INPUT LEVEL ADJUSTMENT CONTROL GLA input level adjustment control Gstep step resolution − 0.5 − dB Vi(rms) maximum input voltage level (RMS value) 2 − − V Zi input impedance 29.5 35 40.5 kΩ input level adjusted via I2C-bus − (L + R; fi = 300 Hz); monitoring line out 250 − mV STEREO DECODER MPXL+R(rms) input voltage level for 100% modulation L + R; 25 kHz deviation (RMS value) MPXL−R input voltage level for 100% modulation L − R; 50 kHz deviation (peak value) − 707 − mV MPX(max) maximum headroom for L + R, fmod < 15 kHz; THD < 15% for L, R 75 µs equivalent input modulation 9 − − dB − 50 − mV MPXpilot(rms) nominal stereo pilot voltage level (RMS value) STon(rms) SToff(rms) hys OUTL+R 1997 Nov 04 pilot threshold voltage stereo on (RMS value) data STS = 1 − − 35 mV data STS = 0 − − 30 mV pilot threshold voltage stereo off (RMS value) data STS = 1 15 − − mV data STS = 0 10 − − mV − 2.5 − dB 480 500 520 mV hysteresis input level adjusted via I2C-bus output voltage level for 100% modulation L + R at LINE OUT (L + R; fi = 300 Hz); monitoring LINE OUT 14 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL αcs fL, R PARAMETER stereo channel separation L/R at LINE OUT L, R frequency response TDA9855 CONDITIONS MIN. TYP. MAX. UNIT aligned with dual tone 14% modulation; see Section “Adjustment procedure” in Chapter “Functional description” fL = 300 Hz; fR = 3 kHz 25 35 − dB fL = 300 Hz; fR = 8 kHz 20 30 − dB fL = 300 Hz; fR = 10 kHz 15 25 − dB fi = 50 Hz to 11 kHz −3 − − dB fi = 12 kHz − −3 − dB 14% modulation; fref = 300 Hz L or R THDL,R total harmonic distortion L, R at LINE OUT modulation L or R 1% to 100%; fi = 1 kHz − 0.2 1.0 % S/N signal-to-noise ratio mono mode; CCIR 468-2 weighted; quasi peak; 500 mV output signal 50 60 − dB STEREO DECODER, OSCILLATOR (VCXO); note 1 fo nominal VCXO output frequency (32fH) with nominal ceramic resonator − 503.5 − kHz fof spread of free-running frequency with nominal ceramic resonator 500.0 − 507.0 kHz ∆fH capture range frequency (nominal pilot) ±190 ±265 − Hz − 150 − mV SAP DEMODULATOR; note 2 SAPi(rms) nominal SAP carrier input voltage level (RMS value) SAPon(rms) pilot threshold voltage SAP on (RMS value) − − 85 mV SAPoff(rms) pilot threshold voltage SAP off (RMS value) 35 − − mV SAPhys hysteresis − 2 − dB SAPLEV SAP output voltage level at LINE OUT LINE OUT (LOL, LOR) in position SAP/SAP; fmod = 300 Hz; 100% modulation − 500 − mV fres frequency response 14% modulation; 50 Hz to 8 kHz; fref = 300 Hz −3 − − dB THD total harmonic distortion fi = 1 kHz − 0.5 2.0 % 1997 Nov 04 15 kHz frequency deviation of intercarrier 15 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9855 CONDITIONS MIN. TYP. MAX. UNIT LINE OUT AT PINS LOL AND LOR − 500 − mV output headroom 9 − − dB Zo output impedance − 80 120 Ω Vo(rms) nominal output voltage (RMS value) HEADo 100% modulation VO DC output voltage 0.45VCC 0.5VCC RL output load resistance 5 − − kΩ CL output load capacitance − − 2.5 nF αct idle crosstalk L, R into SAP 100% modulation; fi = 1 kHz; L or R; line out switched to SAP/SAP 50 − − dB idle crosstalk SAP into L, R 100% modulation; fi = 1 kHz; SAP; line out switched to stereo 50 − − dB output voltage difference if switched from L, R to SAP 250 Hz to 6.3 kHz − − 3 dB ∆VST-SAP 0.55VCC V dbx NOISE REDUCTION CIRCUIT tadj stereo adjustment time see Section “Adjustment procedure” in Chapter “Functional description” − − 1 s Is nominal timing current for nominal release rate of spectral RMS detector Is can be measured at pin 17 (pin 22) via current meter connected to 1⁄2VCC + 1 V − 24 − µA ∆Is spread of timing current − − 15 % − ±30 − % − 1⁄ 3Is − µA wideband − 125 − dB/s spectral − 381 − dB/s Is(range) timing current adjustment range It timing current for release rate of wideband RMS detector Relrate nominal RMS detector release rate 1997 Nov 04 7 steps via I2C-bus nominal timing current and external capacitor values 16 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9855 CONDITIONS MIN. TYP. MAX. UNIT Audio part CIRCUIT SECTION FROM PINS LIL AND LIR TO PINS OUTL, OUTR AND OUTS; note 3 B THD roll-off frequencies total harmonic distortion C6, C7, C10, C26, C27 and C29 = 2.2 µF; Zi = Zi(min) low frequency (−3 dB) − − 20 Hz high frequency (−0.5 dB) 20 − − kHz Vi = 1 V (RMS); Gc = 0 dB; AVL on − 0.2 0.5 % Vi = 2 V (RMS); Gc = 0 dB; AVL on − 0.2 0.5 % Vi = 1 V (RMS); Gc = 0 dB; AVL off − 0.05 − % Vi = 2 V (RMS); Gc = 0 dB; AVL off − 0.02 − % PSRR power supply ripple rejection Vr(rms) < 200 mV; fi = 100 Hz 47 50 − dB αB crosstalk between bus inputs and signal outputs notes 4 and 5 − 110 − dB Vno noise output voltage CCIR 468-2 weighted; quasi peak − 40 80 µV measured in dBA − 8 − µV αcs channel separation Vi = 1 V; fi = 1 kHz 75 − − dB Vi = 1 V; fi = 12.5 kHz 75 − − dB 16 20 24 kΩ f = 1 kHz; Vi = 1 V 86 96 − dB f = 12.5 kHz; Vi = 1 V 80 96 − dB THD < 0.5% 2 2.3 − V 25 mV SELECTOR (FROM PINS LOL, LOR, LIL AND LIR TO PINS SOL AND SOR) Zi input impedance αs input isolation of one selected source to any other input Vi(rms) maximum input voltage (RMS value) Voffset DC offset voltage at selector output by selection of any inputs − − Zo output impedance − 80 120 Ω RL output load resistance (AC) 5 − − kΩ CL output load capacitance − − 2.5 nF Gc voltage gain, selector − 0 − dB 1997 Nov 04 17 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9855 CONDITIONS MIN. TYP. MAX. UNIT AUTOMATIC VOLUME LEVEL CONTROL (AVL) Zi input impedance Vi(rms) maximum input voltage (RMS value) Gv gain, maximum boost THD < 0.2% 8.8 11.0 13.2 kΩ 2 − − V 5 6 7 dB maximum attenuation 14 15 16 dB Gstep equivalent step width between the input stages (soft switching system) − 1.5 − dB Vi(rms) input level at maximum boost (RMS value) see Fig.4 − 0.1 − V input level at maximum attenuation (RMS value) see Fig.4 − 1.125 − V Vo(rms) output level in AVL operation (RMS value) see Fig.4 160 200 250 mV VDC(OFF) DC offset between different gain steps voltage at pin CAV 6.50 to 6.33 V or 6.33 to 6.11 V or 6.11 to 5.33 V or 5.33 to 2.60 V; note 6 − − 6 mV Ratt discharge resistors for attack time constant AT1 = 0; AT2 = 0; note 7 340 420 520 Ω AT1 = 1; AT2 = 0; note 7 590 730 910 Ω AT1 = 0; AT2 = 1; note 7 0.96 1.2 1.5 kΩ AT1 = 1; AT2 = 1; note 7 1.7 2.1 2.6 kΩ normal mode; CCD = 0; note 8 1.6 2.0 2.4 µA − 52 − % − 30 − % − − − − Idec charge current for decay time EFFECT CONTROLS αspat1 αspat2 anti-phase crosstalk by spatial effect ϕ phase shift by pseudo-stereo see Fig.5 VOLUME TONE CONTROL PART (INPUT PINS VIL AND VIR TO PINS OUTX AND OUTS) Zi volume input impedance 8.0 10.0 12.0 kΩ Zo output impedance − 80 120 Ω RL output load resistance (AC) 5 − − kΩ − − 2.5 nF 2.0 2.15 − V CL output load capacitance Vi(rms) maximum input voltage (RMS value) THD < 0.5% Vno noise output voltage CCIR 468-2 weighted; quasi peak 1997 Nov 04 Gc = 16 dB − 110 220 µV Gc = 0 dB − 33 50 µV mute position − 10 − µV 18 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER Gc total continuous control range Gstep step resolution step error between any adjoining step ∆Ga attenuator set error ∆Gt gain tracking error αm mute attenuation VDC(OFF) DC step offset between any adjacent step DC step offset between any step to mute TDA9855 CONDITIONS MIN. TYP. MAX. UNIT maximum boost − 16 − dB maximum attenuation − 71 − dB − 1 − dB − − 0.5 dB Gc = +16 to −50 dB − − 2 dB Gc = −51 to −71 dB − − 3 dB Gc = +16 to −50 dB − − 2 dB 80 − − dB Gc = +16 to 0 dB − 0.2 10.0 mV Gc = 0 to −71 dB − − 5 mV Gc = +16 to +1 dB − 2 15 mV Gc = 0 to −71 dB − 1 10 mV fi = 40 Hz − 17 − dB fi = 10 kHz − 4.5 − dB LOUDNESS CONTROL PART LB maximum loudness boost loudness on; referred to loudness off; boost is determined by external components; see Fig.6 BASS CONTROL (see Fig.7) Gbass Gstep VDC(OFF) bass control maximum boost fi = 40 Hz 15.5 16.5 17.5 dB maximum attenuation fi = 40 Hz 11 12 13 dB step resolution fi = 40 Hz − 1.5 − dB step error between any adjoining step − − 0.5 dB DC step offset between any adjacent step − − 15 mV 11 12 13 dB TREBLE CONTROL (see Fig.8) Gtreble Gstep VDC(OFF) 1997 Nov 04 treble control maximum boost fi = 15 kHz maximum attenuation fi = 15 kHz 11 12 13 dB maximum boost fi > 15 kHz − − 15 dB step resolution fi = 15 kHz − 3 − dB step error between any adjoining step − − 0.5 dB DC step offset between any adjacent step − − 10 mV 19 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor SYMBOL PARAMETER TDA9855 CONDITIONS MIN. TYP. MAX. UNIT SUBWOOFER OR SURROUND CONTROL Gs subwoofer control Gstep step resolution αm mute attenuation VDC(OFF) DC step offset between any adjacent step DC step offset between any step to mute RF internal resistor for low-pass filter with external capacitor at pin SW L + RREJ common mode rejection in surround sound at pin OUTS maximum boost; fi = 40 Hz 12 14 16 dB maximum attenuation; fi = 40 Hz 12 14 16 dB − 2 − dB 60 − − dB Gs = 0 to +14 dB − − 10 mV Gs = 0 to −14 dB − − 5 mV Gs = +2 to +14 dB without − input offset (pin SW connected to Vref) − 15 mV Gs = +2 to +14 dB inclusive offset from OUTR, OUTL − − 50 mV Gs = 0 to −14 dB − − 10 mV 4 5 6 kΩ 26 36 − dB − VCAP − 0.7 − V increasing supply voltage − − 2.5 V decreasing supply voltage 4.2 5 5.8 V increasing supply voltage 5.2 6 6.8 V mono signal at VIL/VIR; f = 1 kHz; Vi = 1 V; balance = 0 dB MUTING AT POWER SUPPLY DROP FOR OUTL, OUTR AND OUTS VCC-DROP supply drop for mute active POWER-ON RESET; note 9 VRESET(STA) start of reset voltage VRESET(END) end of reset voltage Digital part (I2C-bus pins); note 10 VIH HIGH-level input voltage 3 − VCC V VIL LOW-level input voltage −0.3 − +1.5 V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current −10 − +10 µA VOL LOW-level output voltage − − 0.4 V 1997 Nov 04 IIL = 3 mA 20 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Notes to the characteristics 1. The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855. 2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain. 3. Select in to input line control. V bus(p-p) 4. Crosstalk: 20 log --------------------V o(rms) 5. The transmission contains: a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics b) Clock frequency = 50 kHz c) Repetition burst rate = 400 Hz d) Maximum bus signal amplitude = 5 V (p-p). 6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB. 7. Attack time constant = CAV × Ratt. 8. – G v2 –Gv1------------ -----------20 20 C AV × 0.76 V 10 – 10 Decay time = ----------------------------------------------------------------------------------I dec Example: CAV = 4.7 µF; Idec = 2 µA; Gv1 = −9 dB; Gv2 = +6 dB → decay time results in 4.14 s. 9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver is in the reset position. 10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz. Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011). 1997 Nov 04 21 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS R/W A DATA MA DATA Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION S START condition; generated by the master Standard SLAVE ADDRESS 101 101 1 pin MAD not connected Pin programmable SLAVE ADDRESS 101 101 0 pin MAD connected to ground R/W logic 1 (read); generated by the master A acknowledge; generated by the slave DATA slave transmits an 8-bit data word MA acknowledge; generated by the master P STOP condition; generated by the master Table 2 P Definition of the transmitted bytes after read condition MSB FUNCTION LSB BYTE D7 D6 D5 D4 D3 D2 D1 D0 Alignment read 1 ALR1 Y SAPP STP A14 A13 A12 A11 A10 Alignment read 2 ALR2 Y SAPP STP A24 A23 A22 A21 A20 Table 3 Function of the bits in Table 2 BITS FUNCTION STP stereo pilot identification (stereo received = 1) SAPP SAP pilot identification (SAP received = 1) A1X to A2X stereo alignment read data A1X for wideband expander A2X for spectral expander Y indefinite The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word ALR1 etc. until the master generates no acknowledge and transmits a STOP condition. 1997 Nov 04 22 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A DATA A P Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION S START condition Standard SLAVE ADDRESS 101 101 1 pin MAD not connected Pin programmable SLAVE ADDRESS 101 101 0 pin MAD connected to ground R/W logic 0 (write) A acknowledge; generated by the slave SUBADDRESS (SAD) see Table 5 DATA see Table 6 P STOP condition If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress second byte after slave address MSB FUNCTION Volume right LSB REGISTER VR HEX D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 00 Volume left VL 0 0 0 0 0 0 0 1 01 Bass BA 0 0 0 0 0 0 1 0 02 Treble TR 0 0 0 0 0 0 1 1 03 Subwoofer SW 0 0 0 0 0 1 0 0 04 Control 1 CON1 0 0 0 0 0 1 0 1 05 Control 2 CON2 0 0 0 0 0 1 1 0 06 Control 3 CON3 0 0 0 0 0 1 1 1 07 Alignment 1 ALI1 0 0 0 0 1 0 0 0 08 Alignment 2 ALI2 0 0 0 0 1 0 0 1 09 Alignment 3 ALI3 0 0 0 0 1 0 1 0 0A 1997 Nov 04 23 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor Table 6 TDA9855 Definition of third byte after slave address MSB FUNCTION LSB REGISTER D7 D6 D5 D4 D3 D2 D1 D0 VR 0 VR6 VR5 VR4 VR3 VR2 VR1 VR0 Volume left VL 0 VL6 VL5 VL4 VL3 VL2 VL1 VL0 Bass BA 0 0 0 BA4 BA3 BA2 BA1 BA0 Treble TR 0 0 0 TR4 TR3 TR2 TR1 0 Volume right Subwoofer SW 0 0 SW5 SW4 SW3 SW2 0 0 Control 1 CON1 GMU AVLON LOFF X SUR SC2 SC1 SC0 Control 2 CON2 SAP STEREO TZCM VZCM LMU EF2 EF1 EF0 Control 3 CON3 0 0 0 0 L3 L2 L1 L0 Alignment 1 ALI1 0 0 0 A14 A13 A12 A11 A10 Alignment 2 ALI2 STS 0 0 A24 A23 A22 A21 A20 Alignment 3 ALI3 ADJ AT1 AT2 0 1 TC2 TC1 TC0 Table 7 Function of the bits in Table 6 BITS FUNCTION VR0 to VR6 volume control right VL0 to VL6 volume control left BA0 to BA4 bass control TR1 to TR3 treble control SW2 to SW5 subwoofer, surround control GMU mute control for outputs OUTL, OUTR and OUTS (generate mute) AVLON AVL on/off LOFF switch loudness on/off X don’t care bit SUR surround/subwoofer SUR = 1 → 1⁄2(L − R); SUR = 0 → 1⁄2(L + R) SC0 to SC2 selection between line in and line out STEREO, SAP mode selection for line out TZCM zero-crossing mode in mute operation (treble and subwoofer/surround output stage) VZCM zero-crossing mode in volume operation LMU mute control for dematrix + line out select EF0 to EF2 selection between mono, stereo linear, spatial stereo and pseudo mode L0 to L3 input level adjustment ADJ stereo adjustment on/off A1X stereo alignment data for wideband expander A2X stereo alignment data for spectral expander AT1 and AT2 attack time at AVL TC0 to TC2 timing current alignment data STS stereo level switch 1997 Nov 04 24 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor Table 8 TDA9855 Volume setting in registers VR and VL DATA Gc (dB) D6 V6 D5 V5 D4 V4 D3 V3 D2 V2 D1 V1 D0 V0 HEX 16 1 1 1 1 1 1 1 7F 15 1 1 1 1 1 1 0 7E 14 1 1 1 1 1 0 1 7D 13 1 1 1 1 1 0 0 7C 12 1 1 1 1 0 1 1 7B 11 1 1 1 1 0 1 0 7A 10 1 1 1 1 0 0 1 79 9 1 1 1 1 0 0 0 78 8 1 1 1 0 1 1 1 77 7 1 1 1 0 1 1 0 76 6 1 1 1 0 1 0 1 75 5 1 1 1 0 1 0 0 74 4 1 1 1 0 0 1 1 73 3 1 1 1 0 0 1 0 72 2 1 1 1 0 0 0 1 71 1 1 1 1 0 0 0 0 70 0 1 1 0 1 1 1 1 6F −1 1 1 0 1 1 1 0 6E −2 1 1 0 1 1 0 1 6D −3 1 1 0 1 1 0 0 6C −4 1 1 0 1 0 1 1 6B −5 1 1 0 1 0 1 0 6A −6 1 1 0 1 0 0 1 69 −7 1 1 0 1 0 0 0 68 −8 1 1 0 0 1 1 1 67 −9 1 1 0 0 1 1 0 66 −10 1 1 0 0 1 0 1 65 −11 1 1 0 0 1 0 0 64 −12 1 1 0 0 0 1 1 63 −13 1 1 0 0 0 1 0 62 −14 1 1 0 0 0 0 1 61 −15 1 1 0 0 0 0 0 60 −16 1 0 1 1 1 1 1 5F −17 1 0 1 1 1 1 0 5E −18 1 0 1 1 1 0 1 5D −19 1 0 1 1 1 0 0 5C −20 1 0 1 1 0 1 1 5B −21 1 0 1 1 0 1 0 5A 1997 Nov 04 25 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 DATA Gc (dB) D6 V6 D5 V5 D4 V4 D3 V3 D2 V2 D1 V1 D0 V0 HEX −22 1 0 1 1 0 0 1 59 −23 1 0 1 1 0 0 0 58 −24 1 0 1 0 1 1 1 57 −25 1 0 1 0 1 1 0 56 −26 1 0 1 0 1 0 1 55 −27 1 0 1 0 1 0 0 54 −28 1 0 1 0 0 1 1 53 −29 1 0 1 0 0 1 0 52 −30 1 0 1 0 0 0 1 51 −31 1 0 1 0 0 0 0 50 −32 1 0 0 1 1 1 1 4F −33 1 0 0 1 1 1 0 4E −34 1 0 0 1 1 0 1 4D −35 1 0 0 1 1 0 0 4C −36 1 0 0 1 0 1 1 4B −37 1 0 0 1 0 1 0 4A −38 1 0 0 1 0 0 1 49 −39 1 0 0 1 0 0 0 48 −40 1 0 0 0 1 1 1 47 −41 1 0 0 0 1 1 0 46 −42 1 0 0 0 1 0 1 45 −43 1 0 0 0 1 0 0 44 −44 1 0 0 0 0 1 1 43 −45 1 0 0 0 0 1 0 42 −46 1 0 0 0 0 0 1 41 −47 1 0 0 0 0 0 0 40 −48 0 1 1 1 1 1 1 3F −49 0 1 1 1 1 1 0 3E −50 0 1 1 1 1 0 1 3D −51 0 1 1 1 1 0 0 3C −52 0 1 1 1 0 1 1 3B −53 0 1 1 1 0 1 0 3A −54 0 1 1 1 0 0 1 39 −55 0 1 1 1 0 0 0 38 −56 0 1 1 0 1 1 1 37 −57 0 1 1 0 1 1 0 36 −58 0 1 1 0 1 0 1 35 −59 0 1 1 0 1 0 0 34 −60 0 1 1 0 0 1 1 33 1997 Nov 04 26 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 DATA Gc (dB) D6 V6 D5 V5 D4 V4 D3 V3 D2 V2 D1 V1 D0 V0 HEX −61 0 1 1 0 0 1 0 32 −62 0 1 1 0 0 0 1 31 −63 0 1 1 0 0 0 0 30 −64 0 1 0 1 1 1 1 2F −65 0 1 0 1 1 1 0 2E −66 0 1 0 1 1 0 1 2D −67 0 1 0 1 1 0 0 2C −68 0 1 0 1 0 1 1 2B −69 0 1 0 1 0 1 0 2A −70 0 1 0 1 0 0 1 29 −71 0 1 0 1 0 0 0 28 Mute 0 1 0 0 1 1 1 27 Table 9 Bass setting in register BA DATA Gbass (dB) D4 BA4 D3 BA3 D2 BA2 D1 BA1 D0 BA0 HEX 16.5 1 1 0 0 1 19 15.0 1 1 0 0 0 18 13.5 1 0 1 1 1 17 12.0 1 0 1 1 0 16 10.5 1 0 1 0 1 15 9.0 1 0 1 0 0 14 7.5 1 0 0 1 1 13 6.0 1 0 0 1 0 12 4.5 1 0 0 0 1 11 3.0 1 0 0 0 0 10 1.5 0 1 1 1 1 0F 0 0 1 1 1 0 0E −1.5 0 1 1 0 1 0D −3.0 0 1 1 0 0 0C −4.5 0 1 0 1 1 0B −6.0 0 1 0 1 0 0A −7.5 0 1 0 0 1 09 −9.0 0 1 0 0 0 08 −10.5 0 0 1 1 1 07 −12.0 0 0 1 1 0 06 1997 Nov 04 27 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Table 10 Treble setting in register TR Table 12 Selector setting in register CON1 DATA Gtreble (dB) DATA FUNCTION(1) D4 TR4 D3 TR3 D2 TR2 D1 TR1 HEX 12 1 0 1 1 16 9 1 0 1 0 6 1 0 0 1 3 1 0 0 0 D2 SC2 D1 SC1 D0 SC0 Inputs LOR and LOL 0 0 0 14 Inputs LOR and LOR 0 0 1 12 Inputs LOL and LOL 0 1 0 10 Inputs LOL and LOR 0 1 1 0 0 1 1 1 0E Inputs LIR and LIL 1 0 0 −3 0 1 1 0 0C Inputs LIR and LIR 1 0 1 −6 0 1 0 1 0A Inputs LIL and LIL 1 1 0 −9 0 1 0 0 08 Inputs LIL and LIR 1 1 1 −12 0 0 1 1 06 Note 1. Input connected to outputs SOR and SOL. Table 11 Subwoofer/surround setting in register SW DATA Gs (dB) Table 13 SUR bit setting in register CON1 D5 SW5 D4 SW4 D3 SW3 D2 SW2 HEX 14 1 1 1 1 3C 12 1 1 1 0 38 10 1 1 0 1 34 8 1 1 0 0 30 6 1 0 1 1 2C 4 1 0 1 0 28 2 1 0 0 1 24 0 1 0 0 0 20 −2 0 1 1 1 1C −4 0 1 1 0 18 −6 0 1 0 1 14 −8 0 1 0 0 10 −10 0 0 1 1 0C −12 0 0 1 0 08 −14 0 0 0 1 04 Mute 0 0 0 0 00 1997 Nov 04 FUNCTION DATA D3 Surround sound 1 Subwoofer 0 Table 14 LOFF bit setting in register CON1 CHARACTERISTIC DATA D5 With loudness 0 Linear 1 Table 15 AVLON bit setting in register CON1 28 FUNCTION DATA D6 Automatic volume control off 0 Automatic volume control on 1 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Table 16 Mute setting in register CON1 DATA D7 GMU FUNCTION Forced mute at OUTR, OUTL and OUTS 1 Audio processor controlled outputs 0 Table 17 Mute setting in register CON2 DATA D3 LMU FUNCTION Forced mute at LOR and LOL 1 Stereo processor controlled outputs 0 Table 18 Effects setting in register CON2 DATA FUNCTION D2 EF2 D1 EF1 D0 EF0 Stereo linear on 0 0 0 Pseudo on 0 0 1 Spatial stereo; 30% anti-phase crosstalk 0 1 0 Spatial stereo; 50% anti-phase crosstalk 0 1 1 Forced mono 1 1 1 Table 19 Zero-crossing detection setting in register CON2 DATA D5 TZCM FUNCTION Direct mute control 0 Mute control delayed until the next zero-crossing 1 Table 20 Zero-crossing detection setting in register CON2 DATA D4 VZCM FUNCTION Direct volume control 0 Volume control delayed until the next zero-crossing 1 1997 Nov 04 29 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Table 21 Switch setting at line out LOL SETTING BITS IN REGISTER CON2 DATA TRANSMISSION STATUS INTERNAL SWITCH, READABLE BITS IN REGISTER ALR1, ALR2: D6 (SAPP), D5 (STP) LINE OUT SIGNALS AT LOR D7 SAP D6 STEREO SAP SAP SAP received 1 1 Mute mute no SAP received 1 1 Left right STEREO received 0 1 Mono mono no STEREO received 0 1 Mono SAP SAP received 1 0 Mono mute no SAP received 1 0 Mono mono independent 0 0 Table 22 Input level adjust setting in register CON3 DATA Gl (dB) D3 L3 D2 L2 D1 L1 D0 L0 HEX 4.0 1 1 1 1 0F 3.5 1 1 1 0 0E 3.0 1 1 0 1 0D 2.5 1 1 0 0 0C 2.0 1 0 1 1 0B 1.5 1 0 1 0 0A 1.0 1 0 0 1 09 0.5 1 0 0 0 08 0 0 1 1 1 07 −0.5 0 1 1 0 06 −1.0 0 1 0 1 05 −1.5 0 1 0 0 04 −2.0 0 0 1 1 03 −2.5 0 0 1 0 02 −3.0 0 0 0 1 01 −3.5 0 0 0 0 00 1997 Nov 04 30 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Table 23 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2 DATA FUNCTION Gain increase Nominal gain Gain decrease D4 AX4 D3 AX3 D2 AX2 D1 AX1 D0 AX0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 Table 24 STS bit setting in register ALI2 (pilot threshold stereo on) FUNCTION DATA D7 STon(rms) ≤ 35 mV 1 STon(rms) ≤ 30 mV 0 1997 Nov 04 31 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Table 25 Timing current setting in register ALI3 Table 27 ADJ bit setting in register ALI3 DATA IS RANGE FUNCTION D2 TC2 D1 TC1 D0 TC0 +30% 1 0 0 +20% 1 0 1 +10% 1 1 0 Nominal 0 1 1 −10% 0 1 0 −20% 0 0 1 −30% 0 0 0 DATA D7 Stereo decoder operation mode 0 Auto adjustment of channel separation 1 Table 26 AVL attack time setting in register ALI3 DATA Ratt (Ω) D6 AT1 D5 AT2 420 0 0 730 1 0 1200 0 1 2100 1 1 MHA312 300 7 handbook, full pagewidth Vo(rms) (mV) VCAV (V) (1) 6 250 (2) 5 200 4 (3) 160 3 2 100 10−2 (1) VCAV (2) Vo max(rms) (3) Vo min(rms) 1 10−1 1 VI(rms) (V) AVL measured at pin EOL/EOR. Y1 axis output level in AVL operation with typically 200 mV. Y2 axis VCAV DC voltage at pin CAV corresponds with typical gain steps in range of +6 to −15 dB. Fig.4 Automatic volume level control diagram. 1997 Nov 04 32 10 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 MHA311 0 handbook, full pagewidth (1) phase (degree) (2) −100 (3) −200 −300 −400 10 102 103 104 f (Hz) 105 (1) see Table 28. (2) see Table 28. (3) see Table 28. Fig.5 Pseudo (phase in degrees) as a function of frequency (left output). Table 28 Explanation of curves in Fig.5 CAPACITANCE AT PIN CPS1 (nF) CAPACITANCE AT PIN CPS2 (nF) 1 15 15 normal 2 5.6 47 intensified 3 5.6 68 more intensified CURVE 1997 Nov 04 33 EFFECT Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 MHA844 25 Gc (dB) 16 14 15 9 4 5 −1 −6 −5 −11 −16 −15 −21 −26 −25 −31 −36 −35 10 20 102 103 f (Hz) 104 Fig.6 Volume control with loudness (including low roll-off frequency). MHA843 21 handbook, full pagewidth 18 Gbass (dB) 15 12 9 6 3 0 −3 −6 −9 −12 −15 10 20 102 103 Fig.7 Bass control. 1997 Nov 04 34 f (Hz) 104 parameter: volume gain setting (dB) handbook, full pagewidth Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 MHA845 15 handbook, full pagewidth 12 Gtreble (dB) 9 6 3 0 −3 −6 −9 −12 −15 102 103 200 104 f (Hz) Fig.8 Treble control. MHA842 60 handbook, halfpage noise (µV) 40 20 0 −80 −60 −40 −20 0 gain (dBA) 20 Fig.9 Noise as function of gain in dBA (RMS value). 1997 Nov 04 35 105 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 gain volume = 16 dB (Gv(max)) handbook, full pagewidth LIL POWER STAGE TDA9855 LIR G = 20 dB P(max) = 40 W at 4 Ω VI = 200 mV; AVL off or VI = 100 to 1250 mV; AVL on VO = 1.26 V for P(max) 4 dB margin for power peaks MHA841 All values given are in RMS value. Fig.10 Level diagram. 1997 Nov 04 36 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 APPLICATION HINTS Selection of input signals by using the zero-crossing mute mode (see Fig.11) A selection between the internal signal path and the external input LIL/LIR produces a modulation click depending on the difference of the signal values at the time of switching. At t1 the maximum possible difference between signals is 7 V (p-p) and gives a large click. Using the zero-crossing detector no modulation click is audible. For example: The selection is enabled at t1, the microcontroller sets the zero-crossing bit (TZCM = 1) and then the mute bit (GMU = 1) via the I2C-bus. The output signal follows the input A signal, until the next zero-crossing occurs and then activates mute. After a fixed delay time before t2, the microcontroller has to send the forced mute mode (TZCM = 0) and the return to the zero-crossing mode (TZCM = 1) to be sure that mute is enabled. The output signal remains muted until the next signal zero-crossing of input B occurs, and then follows that signal. The delay time t2 − t1 is e.g. 40 ms. The zero-crossing function is working at the lowest frequency of 40 Hz. handbook, full pagewidth MED436 V 4 (1) 3 2 1 0 −1 (2) t1 t t2 (3) −2 −3 −4 (1) Input A (internal signal). (2) Output. (3) Input B (external input signal). Fig.11 Zero-crossing function; only one channel shown. 1997 Nov 04 37 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Loudness filter calculation example Figure 12 shows the basic loudness circuit with an external low-pass filter application. R1 allows an attenuation range of 21 dB while the boost is determined by the gain stage V1. Both result in a loudness control range of +16 to −12 dB. handbook, halfpage C KVL VIX R1 33 kΩ Defining fref as the frequency where the level does not change while switching loudness on/off. The external resistor R3 for fref → ∞ can be calculated as: LOX V1 C1 Gv ------20 R2 R3 10 R3 = R1 -------------------- . With Gv = −21 dB and R1 = 33 kΩ, G v ------20 MHA838 1 – 10 R3 = 3.2 kΩ is generated. For the low-pass filter characteristic the value of the external capacitor C1 can be determined by setting a specific boost for a defined frequency and referring the gain to Gv at fref as indicated above. Fig.12 Basic loudness circuit. Gv ------20 ( R1 + R3 ) × 10 – R3 1 --------------------- = ------------------------------------------------------------Gv j ( ωC1 ) ------20 1 – 10 For example: 3 dB boost at f = 1 kHz Gv = Gv(ref) + 3 dB = −18 dB; f = 1 kHz and C1 = 100 nF. handbook, halfpage 220 nF VIX R1 33 kΩ 8.2 nF If a loudness characteristic with additional high frequency boost is desired, an additional high-pass section has to be included in the external filter circuit as indicated in the block diagram. A filter configuration that provides AC coupling avoids offset voltage problems. 20 kΩ LOX 150 nF V1 R2 2.2 kΩ Figure 13 shows an example of the loudness circuit with bass and treble boost. MHA839 Fig.13 Loudness circuit with bass and treble boost. 1997 Nov 04 38 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 VP handbook, full pagewidth VCC 8.5 V +8.5 V to oscilloscope 470 µF 4.7 kΩ 28 inputs 12 6 outputs to oscilloscope TDA9855 47 41 25 2 × 220 nF 11 30 100 µF 2 × 600 Ω 2 × 4.7 µF 100 µF 2 × 5 kΩ MHA840 Fig.14 Turn-on/off power supply circuit diagram. MED433 10 handbook, full pagewidth (V) 8 (1) 6 4 (2) 2 0 0 1 2 3 (1) VCC. (2) VO. Fig.15 Turn-on/off behaviour. 1997 Nov 04 39 4 t (s) 5 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 INTERNAL PIN CONFIGURATIONS The pin numbers refer to the SDIP-version. handbook, halfpage handbook, halfpage 4.25 V 4.25 V + 1 + 3.64 kΩ + 2 7.79 kΩ 2.4 kΩ 4.25 V MHA846 MHA847 Fig.16 Pin 1: treble control capacitor, left; pin 52: treble control capacitor, right. handbook, halfpage + Fig.17 Pin 2: bass control capacitor input, left; pin 51: bass control capacitor input, right. 3 4.25 V handbook, halfpage 80 Ω 80 Ω MHA849 MHA848 Fig.19 Pin 4: output subwoofer; pin 6: output, left channel; pin 14: output selector, left channel; pin 39: output selector, right channel; pin 47: output, right channel. Fig.18 Pin 3: bass control capacitor output, left; pin 50: bass control capacitor output, right. 1997 Nov 04 4 4.25 V + 40 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor handbook, halfpage TDA9855 5 + 1.8 kΩ MHA850 Fig.20 Pin 5: MAD (I2C-bus address switch). handbook, halfpage 7 4.25 V + 1.33 kΩ MHA851 Fig.21 Pin 7: input loudness, left; pin 46: input loudness, right. handbook, halfpage 8 4.25 V + 10.58 kΩ 4.8 kΩ MHA852 Fig.22 Pin 8: input volume, left; pin 45: input volume, right. 1997 Nov 04 41 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor handbook, halfpage TDA9855 9 4.25 V + handbook, halfpage 10 + 15 kΩ 6.8 kΩ MHA854 MHA853 Fig.23 Pin 9: output effects, left; pin 44: output effects, right. handbook, halfpage Fig.24 Pin 10: automatic volume control capacitor. 11 handbook, halfpage + 12 4.25 V + 3.4 kΩ 3.4 kΩ 20 kΩ 20 kΩ MHA856 MHA855 Fig.26 Pin 12: line input, left; pin 41: line input, right. Fig.25 Pin 11: reference voltage 0.5VCC. 1997 Nov 04 42 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 handbook, halfpage 4.25 V 13 1 handbook, halfpage + + 2 15 4.25 V 5 kΩ 3 1.75 kΩ MHA858 8 MHA857 Fig.27 Pin 13: input automatic volume control, left; pin 40: input automatic volume control, right. handbook, halfpage Fig.28 Pin 15: line output, left; pin 38: line output, right. handbook, halfpage 16 18 4.25 V + + 6 kΩ MHA859 MHA860 Fig.29 Pin 16: timing capacitor wideband for dbx; pin 17: timing capacitor spectral for dbx. 1997 Nov 04 Fig.30 Pin 18: capacitor wideband for dbx; pin 19: capacitor spectral for dbx. 43 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor handbook, halfpage TDA9855 handbook, halfpage 20 + + 21 600 Ω MHA861 MHA862 Fig.31 Pin 20: variable emphasis out for dbx. Fig.32 Pin 21: variable emphasis in for dbx. handbook, halfpage handbook, halfpage 22 4.25 V + + 23 10 kΩ MHA863 MHA864 Fig.33 Pin 22: capacitor noise reduction for dbx. handbook, halfpage + Fig.34 Pin 23: capacitor mute for SAP. 24 4.25 V handbook, halfpage 26 5 V 1.8 kΩ 20 kΩ 20 kΩ MHA866 MHA865 Fig.36 Pin 26: SDA (I2C-bus data input/output). Fig.35 Pin 24: capacitor DC decoupling for SAP. 1997 Nov 04 44 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor handbook, halfpage TDA9855 handbook, halfpage 5 V 27 28 apply 8.5 V to this pin 1.8 kΩ MHA867 MHA868 Fig.37 Pin 27: SCL (I2C-bus clock). Fig.38 Pin 28: supply voltage. handbook, halfpage 29 4.25 V handbook, halfpage 30 + + 4.7 kΩ 300 Ω 5 kΩ MHA870 30 kΩ MHA869 Fig.39 Pin 29: input composite signal. Fig.40 Pin 30: smoothing capacitor for supply. handbook, halfpage + handbook, halfpage 32 4.25 V 31 4.25 V + 3.5 kΩ 3.5 kΩ 3.5 kΩ MHA871 MHA872 Fig.41 Pin 31: capacitor for pilot detector. 1997 Nov 04 Fig.42 Pin 32: capacitor for pilot detector. 45 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor handbook, halfpage TDA9855 handbook, halfpage 33 4.25 V + 10 kΩ 34 + 10 kΩ MHA873 MHA874 Fig.43 Pin 33: capacitor for phase detector. handbook, halfpage Fig.44 Pin 34: capacitor for filter adjust. 35 + handbook, halfpage 36 4.25 V + 3 kΩ 10 kΩ 10 kΩ MHA876 MHA875 Fig.46 Pin 36: capacitor DC decoupling mono; pin 37: capacitor DC decoupling stereo/SAP. Fig.45 Pin 35: ceramic resonator. handbook, halfpage 4.25 V 49 handbook, halfpage + 43 4.25 V + 1 2 3 15 kΩ 10 kΩ 10 kΩ MHA877 8 Fig.47 Pin 43: capacitor 1 pseudo function; pin 42: capacitor 2 pseudo function. 1997 Nov 04 Fig.48 Pin 49: capacitor subwoofer. 46 MHA878 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 PACKAGE OUTLINES seating plane SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 27 52 pin 1 index E 1 26 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-01-22 95-03-11 SOT247-1 1997 Nov 04 EUROPEAN PROJECTION 47 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 HE E pin 1 index A e A4 A1 (A 3) β 9 k1 27 Lp k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.30 0.53 0.33 0.81 0.66 0.180 0.020 0.01 0.165 0.13 0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950 inches D (1) E (1) e eD eE HD HE k 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 2.16 β 2.16 45 o Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT188-2 112E10 MO-047AC 1997 Nov 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-03-11 48 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING SDIP Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The package footprint must incorporate solder thieves at the downstream corners. • The longitudinal axis of the package footprint must be parallel to the solder flow. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. REPAIRING SOLDERED JOINTS Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. PLCC REPAIRING SOLDERED JOINTS REFLOW SOLDERING Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9398 510 63011). 1997 Nov 04 49 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Nov 04 50 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 NOTES 1997 Nov 04 51 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/03/pp52 Date of release: 1997 Nov 04 Document order number: 9397 750 02446