INTEGRATED CIRCUITS DATA SHEET TDA4850 Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors Product specification Supersedes data of September 1991 File under Integrated Circuits, IC02 1997 Jun 05 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 FEATURES GENERAL DESCRIPTION • VGA operation fully implemented including alignment-free vertical and E/W amplitude pre-settings The TDA4850 provides economical solutions in VGA/XGA and multi-frequency monitors. The IC incorporates the complete horizontal and vertical small signal processing. VGA-dependent mode detection and settings are performed on chip. In conjunction with TDA486X or TDA8351 (vertical output circuits) both ICs offer an extremely advanced system solution. • 4th VGA mode easy applicable (XGA, Super VGA) • Multi-frequency operation externally selectable • All adjustments DC-controllable • Alignment-free oscillators • Sync separators for video or horizontal and vertical TTL sync levels regardless of polarity • Horizontal oscillator with PLL1 for sync and PLL2 for flyback • Constant vertical and E/W amplitude in multi-frequency operation • DC-coupling to vertical power amplifier (TDA486X or TDA8351) • Internal supply voltage stabilization with excellent ripple rejection to ensure stable geometrical adjustments. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage (pin 1) 9.2 12 16 V IP supply current − 40 − mA Vi sync AC-coupled composite video signal with negative-going sync − (peak-to-peak value; pin 9) 1 − V sync slicing level − 120 − mV DC-coupled TTL-compatible horizontal sync signal (peak value; pin 9) 1.7 − − V slicing level 1.2 1.4 1.6 V DC-coupled TTL-compatible vertical sync signal (peak value; pin 10) 1.7 − − V slicing level 1.2 1.4 1.6 V Io V vertical differential output current (peak-to-peak value; pins 5 and 6) − 1 − mA Io H horizontal sink output current on pin 3 − − 60 mA Tamb operating ambient temperature 0 − 70 °C ORDERING INFORMATION TYPE NUMBER TDA4850 1997 Jun 05 PACKAGE NAME DIP20 DESCRIPTION plastic dual in-line package; 20 leads (300 mil) 2 VERSION SOT146-1 1997 Jun 05 3 AC-coupled (video) DC-coupled (TTL level) mode detector disable + 9 7 10 HORIZONTAL SYNC SEPARATOR (TTL VIDEO SYNC) VGA MODE DETECTOR AND OUTPUT VERTICAL SYNC SEPARATOR RHOS 18 2 PLL2 horizontal flyback CHOS 19 HORIZONTAL OSCILLATOR 5 6 20 HORIZONTAL OUTPUT H supply SUPPLY AND REFERENCE VOLTAGE MEH165 3 4 1 14 11 +VB horizontal drive VP (9.2 to 16 V) parabola amplitude E/W drive differential vertical output PARABOLA ADJUSTMENT AND OUTPUT V supply VERTICAL AMPLITUDE ADJUSTMENT AND OUTPUT 13 TDA4850 12 vertical amplitude Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors Fig.1 Block diagram. 17 PLL1 16 CVOS CVA VERTICAL OSCILLATOR AMPLITUDE CONTROL 15 RVOS H+V CLAMPING AND BLANKING GENERATOR VERTICAL SYNC INTEGRATOR AUTOMATIC POLARITY CORRECTION VGA/MULTIFREQUENCY SWITCH AUTOMATIC POLARITY CORRECTION 8 handbook, full pagewidth 4th mode vertical sync (TTL level) clamping/ blanking pulse Philips Semiconductors Product specification TDA4850 BLOCK DIAGRAM Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 PINNING SYMBOL PIN DESCRIPTION VP 1 positive supply voltage FLB 2 horizontal flyback input HOR 3 horizontal output GND 4 ground (0 V) VERT1 5 vertical output 1; negative-going sawtooth handbook, halfpage VP 1 20 PLL2 FLB 2 19 CHOS HOR 3 18 RHOS GND 4 17 PLL1 VERT2 6 vertical output 2; positive-going sawtooth MODE 7 4th mode output and mode detector disable input VERT1 5 16 CVOS TDA4850 CLBL 8 clamping/blanking pulse output VERT2 6 15 RVOS HVS 9 horizontal sync/video input MODE 7 14 REW VS 10 vertical sync input CLBL 8 13 RVA EW 11 E/W output (parabola to driver stage) HVS 9 12 CVA CVA 12 capacitor for amplitude control RVA 13 vertical amplitude adjustment input REW 14 E/W amplitude adjustment input (parabola) RVOS 15 vertical oscillator resistor CVOS 16 vertical oscillator capacitor PLL1 17 PLL1 phase RHOS 18 horizontal oscillator resistor CHOS 19 horizontal oscillator capacitor PLL2 20 PLL2 phase 1997 Jun 05 11 EW VS 10 MEH168 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 FUNCTIONAL DESCRIPTION Clamping and blanking generator Horizontal sync separator and polarity correction A combined clamping and blanking pulse is available on pin 8 (suitable for the video preamplifier TDA4880). The lower level of 2.1 V can be the blanking signal derived from line flyback, or the vertical blanking pulse from the internal vertical oscillator. An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. Vertical blanking equals to the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA as well as for multi-frequency operation (selectable via pin 7). DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The upper level of 3.9 V is the horizontal clamping pulse with internally fixed pulse width of 1 µs. A mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage. PLL1 phase detector Vertical sync separator, polarity correction and vertical sync integrator The phase detector is a standard one using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17. DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then polarity is corrected. The polarity information is fed to the VGA mode detector. If pin 10 is not used, it must be connected to ground. Horizontal oscillator This oscillator is a relaxation type oscillator. Its frequency is determined mainly by the capacitor on pin 19. A frequency range of one octave is achieved by the current on pin 18. The ϕ1 control voltage from pin 17 is fed via a buffer amplifier and an attenuator to the current reference pin 18 to achieve a high DC loop gain. Therefore, changes in frequency will not affect the phase relationship between horizontal sync pulses and line flyback pulses. The separated Vi(sync) signal from pin 10, or the integrated composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator. VGA mode detector and mode output The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from VP to pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters. PLL2 phase detector This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses. VGA mode detector input A certain amount of phase adjustments is possible by injecting a DC current from an external source into the PLL2 filter capacitor on pin 20. For multi-frequency operation the voltage on pin 7 must be externally forced to a level of <50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 to 300 µs (575 µs is needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 to 110 Hz. 1997 Jun 05 5 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 To achieve a stabilized amplitude the free-running frequency fo (without adjustment) must be lower than the lowest occurring sync frequency. The contributions shown in Table 1 can be assumed. Horizontal driver This open-collector output stage (pin 3) can directly drive an external driver transistor. The saturation voltage is 300 mV at 20 mA. To protect the line deflection transistor, the horizontal output stage does not conduct at VP < 6.4 V (pin 1). Table 1 Calculation of fo total spread CONTRIBUTING ELEMENTS Vertical oscillator and amplitude control This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency fo is determined by the values of RVOS and CVOS. The recommended values should be altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I5 and I6 are in relation to the value of RVOS. Therefore, the oscillator frequency must be determined only by CVOS on pin 16. % Minimum frequency offset between fo and the lowest trigger frequency 10 Spread of IC ±3 Spread of R (22 kΩ) ±1 Spread of C (0.1 µF) ±5 Total 19 50 Hz Result for 50 to 110 Hz application: f o = --------------- = 42 Hz 1.19 1 f o = ---------------------------------------------------10.8 × R VOS × C VOS Table 2 VGA modes HORIZONTAL/VERTICAL SYNC POLARITY HORIZONTAL FREQUENCY (kHz) VERTICAL FREQUENCY (Hz) NUMBER OF ACTIVE LINES MODE OUTPUT PIN 7 1 +/− 31.45 70 350 LOW 2 −/+ 31.45 70 400 LOW 3 −/− 31.45 60 480 LOW 4 +/+ fixed by external circuitry − − HIGH MODE 1997 Jun 05 6 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage (pin 1) −0.5 +16 V V3,7 voltage on pins 3 and 7 −0.5 +16 V V8 voltage on pin 8 −0.5 +7 V Vn voltage on pins 5, 6, 9, 10, 13, 14 and 18 −0.5 +6.5 V I2 current on pin 2 − ±10 mA I3 current on pin 3 − 100 mA I7 current on pin 7 − 20 mA I8 current on pin 8 − −10 mA Tamb operating ambient temperature 0 70 °C Tj junction temperature − 150 °C Tstg storage temperature −55 +150 °C Vesd electrostatic handling for all pins − ±300 V note 1 Note 1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1997 Jun 05 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 7 VALUE UNIT 65 K/W Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 CHARACTERISTICS VP = 12 V; Tamb = 25 °C; measurements taken in Fig.6; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 1) 9.2 12 16 V IP supply current − 40 − mA Internal reference voltage Vref internal reference voltage 6.0 6.25 6.5 V TC temperature coefficient Tamb = 20 to 100 °C − − ±90 10−6/K PSRR power supply ripple rejection f = 1 kHz sine wave 60 75 − dB VP supply voltage (pin 1) to ensure all internal reference voltages 25 35 − dB 9.2 − 16 V − 300 − mV top sync clamping level 1.1 1.32 1.5 V slicing level above top sync level 90 120 150 mV RS allowed source resistance for 7% duty cycle Vi sync > 200 mV − − 1.5 kΩ f = 1 MHz sine wave Composite sync input (AC-coupled; V10 = 5 V) Vi sync sync amplitude of video input signal (pin 9) sync on green; RS = 50 Ω r9 differential input resistance during sync − 80 − Ω I9 charging current of coupling capacitor V9 > 1.5 V 1.7 2.6 3.4 µA tint vertical sync integration time to generate sync pulse 7 10 13 µs sync input signal (peak value; pin 9) 1.7 − − V slicing level 1.2 1.4 1.6 V Horizontal sync input (DC-coupled, TTL-compatible) Vi sync tp minimum pulse width 700 − − ns tr, tf rise time and fall time 10 − 500 ns I9 input current V9 = 0.8 V − − −200 µA V9 = 5.5 V − − 10 µA Automatic horizontal polarity switch (H-sync on pin 9) tp H/tH horizontal sync pulse width related to tH (duty cycle for automatic polarity correction) − − 30 % tp delay time for changing sync polarity 0.3 − 1.8 ms 1.7 − − V 1.2 1.4 1.6 V − − ±10 µA − − 300 µs Vertical sync input (DC-coupled, TTL-compatible; V-sync on pin 10) Vi sync sync input signal (peak value; pin 10) slicing level I10 input current tp V maximum vertical sync pulse width for automatic vertical polarity switch 1997 Jun 05 0 < V10 < 5.5 V 8 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors SYMBOL PARAMETER CONDITIONS TDA4850 MIN. TYP. MAX. UNIT Horizontal mode detector output (VGA mode) V7 I7 output saturation voltage LOW (for modes 1, 2 and 3) I7 = 6 mA − 0.275 0.33 V output voltage HIGH mode 4 − − VP V load current to force VGA mode-dependent vertical and parabola amplitudes modes 1, 2 and 3 2 − 6 mA output current mode 4 − 0 − mA 0 − 50 mV upper control voltage limitation − 5.0 − V lower control voltage limitation − 1.2 − V see Fig.3 − ±300 − µA R18 = 12 kΩ (pin 18); C19 = 2.2 nF (pin 19) − 31.45 − kHz VGA/multi-frequency mode switch V7 input voltage LOW to force multi-frequency mode Horizontal comparator PLL1 V17 I17 control current Horizontal oscillator fosc centre frequency ∆fosc deviation of centre frequency − − ±3.0 % TC temperature coefficient − − ±150 10−6/K ϕH/tH relative holding/catching range ±6 ±6.5 ±7.3 % R18 external oscillator resistor V18 voltage at reference current input (pin 18) ∆V18 control voltage PLL1 and PLL2 locked; Vref = 6.25 V 9 − 18 kΩ − 3.125 − V − ±205 − mV Horizontal PLL2; see Fig.3 V2 upper clamping level of flyback input I2 = 6 mA − 5.5 − V lower clamping level of flyback input I2 = −1 mA − −0.75 − V − 3.0 − V H-scan; V8 < 0.9 V −0.5 − − mA H-flyback; V8 > 1.8 V − − −0.2 mA H-flyback slicing level I2 input current td/tH delay between middle of sync and middle of H-flyback related to tH − 3.2 − % V20 upper control voltage limitation − 4.6 − V lower control voltage limitation − 1.6 − V I20 control current − ±200 − µA ∆t/tH PLL2 control range related to tH 30 − − % 1997 Jun 05 9 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors SYMBOL PARAMETER CONDITIONS TDA4850 MIN. TYP. MAX. UNIT Horizontal output (open-collector); see Fig.3 V3 output voltage LOW tp/tH tH duty cycle VP threshold to activate too low supply voltage protection I3 = 20 mA − − 0.3 V I3 = 60 mA − − 0.8 V 42 45 48 % horizontal output off − 5.3 − V horizontal output on − 5.6 − V Horizontal clamping/blanking generator output; see Fig.3 output voltage LOW H and V scanning − − 0.9 V blanking output voltage internal V blanking 1.8 2.1 2.4 V external H blanking 1.8 2.1 2.4 V clamping output voltage H-sync on pin 9 3.5 3.9 4.3 V I8 internal sink current for all output levels H and V scanning 2.3 2.9 3.5 mA t8 clamping pulse start with end of H-sync tclp clamping pulse width 0.8 1.0 1.2 µs S steepness of rise and fall times − 40 − ns/V 40 42 43.3 Hz V8 Vertical oscillator (Vref = 6.25 V) fo vertical free-running frequency fV nominal vertical sync range no fo adjustment 50 − 110 Hz V15 voltage on pin 15 R15 = 22 kΩ 2.8 3.0 3.2 V td delay between sync pulse and start of vertical scan measured on pin 8 500 575 650 µs 240 300 360 µs R15 = 22 kΩ; C16 = 0.1 µF in VGA/XGA mode, activated by an external resistor on pin 7 in multi-frequency mode V7 < 50 mV I12 control current for amplitude control − ±200 − µA C12 capacitor for amplitude control − − 0.33 µF Vertical differential output; see Fig.4 Io differential output current between pins 5 and 6 (peak-to-peak value) mode 3; I13 > −135 µA; R15 = 22 kΩ 0.9 1.0 1.1 mA maximum offset current error Io = 1 mA − − ±2.5 % − − ±1.5 % maximum linearity error 1997 Jun 05 10 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors SYMBOL PARAMETER CONDITIONS TDA4850 MIN. TYP. MAX. UNIT Vertical amplitude adjustment (in percent of output signal) − 5.0 − V Io max (100%) −110 −120 −135 µA Io min (typically 58%) − 0 − µA mode 1 116.1 116.8 117.5 % mode 2 102.0 102.2 102.5 % mode 3 − 100 − % mode 4 − 100 − % multi-frequency operation (VGA operation V7 < 50 mV disabled) − 100 − % 1.05 1.2 1.35 V top output signal during flyback 4.1 4.35 4.6 V temperature coefficient of output signal − − 250 10−6/K − 5.0 − V 100% parabola −110 −120 −135 µA typically 28% parabola − 0 − µA V13 input voltage I13 adjustment current ∆Io/∆t VGA mode-dependent pre-settings activated by an external resistor on pin 7 note 1; see Table 2 E/W output; note 2 V11 TC bottom output signal during mid-scan (pin 11) internally stabilized E/W amplitude adjustment (parabola); see Fig.4 V14 input voltage (pin 14) I14 adjustment current Notes to the Characteristics 1. ∆Io/∆t relative to value of mode 3. 2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment. Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14. 1997 Jun 05 11 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 handbook, full pagewidth H-sync (VGA) 15% 85% 4.6 V sawtooth of horizontal oscillator 42.5% 1.6 V 39.5% control current of PLL1 line flyback pulse on pin 2 current control of PLL2 3.9 V 1 µs clamping pulse clamping and blanking pulses on pin 8 2.1 V H + V blanking pulse 0.7 V horizontal output pulse with 45% duty cycle PLL2 control range (minimum 30%) MEH170 Fig.3 Horizontal timing diagram. 1997 Jun 05 12 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 4.0 V(2) handbook, full pagewidth 3.8 V sawtooth voltage on pin 16 1.4 V internal timing pulse V trigger pulse trigger inhibit window ,,,,,,,,,, ,,,,,,,,,, amplitude control pulse vertical blanking pulse on pin 8 2.1 V 0.7 V 550 µA on pin 6 differential output currents 50 µA on pin 5 4.5 V E/W parabola on pin 11 1.2 V 100 µs 150 µs 50 µs(1) 325 µs 19.4 to 8.5 ms (50 to 110 Hz) MHA711 (1) In multi-frequency mode. (2) For free-running oscillator. Fig.4 Vertical and E/W timing diagram. 1997 Jun 05 13 1997 Jun 05 all inputs and outputs protected in this way except pins 2, 9 and 10 pin 14 11 80 Ω 20 Ω 7.3 V 2 kΩ 1.4 V 80 Ω 9 HVS 12 1.4 V CVA + 7.3 V Vref 3 mA 1.28 V 8 CLBL REW RVA 1.4 V 15 RVOS 5V 2× 7.3 V Vref Vref 6 VERT2 16 CVOS 3V 1.6 mA Vref Vref 3.1 V 4V 5V Vref 5 VERT1 PLL1 17 18 RHOS 1.2 V Vref 300 µA Vref 3 HOR 300 µA 4 GND 19 CHOS 1.4 mA Vref 1 kΩ 2 FLB 20 Vref MEH258 200 µA 200 µA 1 Vref 3V PLL2 260 µA 7.3 V 7 × VBE + VP Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors Fig.5 Internal circuit. 14 5V TDA4850 7.3 V 13 7.3 V 2.1 V blanking 3.9 V clamping 7 MODE dbook, full pagewidth EW 30 kΩ + 2 kΩ 10 VS Philips Semiconductors Product specification TDA4850 INTERNAL CIRCUITRY Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 TEST AND APPLICATION INFORMATION handbook, full pagewidth Vi sync clamp/blank 4th pulses mode 47 nF composite sync vertical differential output VP = 9.2 to 16 V 47 nF horizontal TTL sync vertical TTL sync 2.7 kΩ H-output LOW H-flyback mode detector disable HIGH 10 9 8 7 5 6 4 3 2 1 17 18 19 20 TDA4850 11 12 13 0.22 µF 14 39 kΩ 220 kΩ 15 39 kΩ 16 22 kΩ (1%) 220 kΩ 0.1 µF (5%) 220 pF 22 kΩ 2.2 nF 12 kΩ (1%) 2.2 nF (2%) 2.2 nF MEH169 E/W output vertical amplitude parabola amplitude Fig.6 Test and application circuit (measurements taken at VP = 12 V). 1997 Jun 05 15 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1997 Jun 05 REFERENCES IEC JEDEC EIAJ SC603 16 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors TDA4850 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 1997 Jun 05 17 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors NOTES 1997 Jun 05 18 TDA4850 Philips Semiconductors Product specification Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors NOTES 1997 Jun 05 19 TDA4850 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/03/pp20 Date of release: 1997 Jun 05 Document order number: 9397 750 02184