INTEGRATED CIRCUITS DATA SHEET UDA1350ATS IEC 958 audio DAC Preliminary specification Supersedes data of 1999 Dec 21 File under Integrated Circuits, IC01 2000 Mar 29 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS CONTENTS 1 FEATURES 1.1 1.2 1.3 1.4 General Control IEC 958 input Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.6.9 Clock regeneration and lock detection Mute Auto mute Data path IEC 958 input Audio feature processor Interpolator Noise shaper Filter stream DAC Control Static pin control mode L3 control mode L3 interface General Device addressing Register addressing Data write mode Data read mode Initialisation string Overview of L3 interface registers Writable registers Readable registers 2000 Mar 29 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 TIMING CHARACTERISTICS 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 15.2 15.3 15.4 15.5 2 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS Philips Semiconductors Preliminary specification IEC 958 audio DAC 1 1.1 UDA1350ATS FEATURES General • 2.7 to 3.6 V power supply • Integrated digital filter and Digital-to-Analog Converter (DAC) • 256fs system clock output • 20-bit data path in interpolator • High performance • No analog post filtering required for DAC. 1.2 2 APPLICATIONS • Digital audio systems. Control • Controlled either by means of static pins or via the L3 microcontroller interface. 3 GENERAL DESCRIPTION Available in two versions: 1.3 • UDA1350ATS: IEC 958 input • On-chip amplifier for converting IEC 958 input to CMOS levels – only IEC 958 input to DAC in SSOP28 package. • UDA1350AH: • Lock indication signal available on pin LOCK – full featured version in QFP44 package. • Lock indication signal combined on-chip with the Pulse Code Modulation (PCM) status bit; in case non-PCM has been detected pin LOCK indicates out-of-lock The UDA1350ATS is a single chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter employing bitstream conversion techniques. • Key channel-status bits available via L3 interface (lock, pre-emphasis, audio sample frequency, two channel PCM indication and clock accuracy). 1.4 A lock indication signal is available on pin LOCK indicating that the IEC 958 decoder is locked. This pin is also used to indicate whether PCM data is applied to the input or not. In the event non-PCM data has been detected, the device indicates out-of-lock. Digital sound processing and DAC • Automatic de-emphasis when using IEC 958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies By default the DAC output and the data output interface are muted when the decoder is out-of-lock. However, this setting can be overruled in the L3 control mode. • Soft mute by means of a cosine roll-off circuit selectable via pin MUTE or the L3 interface • dB linear volume control with 1 dB steps from 0 dB to −60 dB and −∞ dB • Bass boost and treble control in L3 control mode • Interpolating filter (fs to 128fs) by means of a cascade of a recursive filter and a FIR filter • Third order noise shaper operating at 128fs generates the bitstream for the DAC • Filter stream digital-to-analog converter. 2000 Mar 29 3 Philips Semiconductors Preliminary specification IEC 958 audio DAC 4 UDA1350ATS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage VDDA analog supply voltage IDDA(DAC) analog supply current of DAC 2.7 3.0 3.6 V 2.7 3.0 3.6 V power-on − 8.0 − mA power-down − 750 − µA IDDA(PLL) analog supply current of PLL − 0.7 − mA IDDD digital supply current − 2.0 − mA IDDD(C) digital supply current of core − 16.0 − mA P power consumption DAC in playback mode − 80 − mW DAC in Power-down mode − 58 − mW General trst reset active time − 250 − µs Tamb ambient temperature −40 − +85 °C − 900 − mV at 0 dB − −90 −85 dB at −40 dB; A-weighted Digital-to-analog converter Vo(rms) output voltage (RMS value) note 1 (THD + N)/S total harmonic distortion-plus-noise to signal ratio fi = 1.0 kHz tone − −60 −55 dB S/N signal-to-noise ratio fi = 1.0 kHz tone; code = 0; A-weighted 95 100 − dB αcs channel separation fi = 1.0 kHz tone − 96 − dB ∆Vo unbalance of output voltages fi = 1.0 kHz tone − 0.1 0.4 dB Note 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 5 ORDERING INFORMATION TYPE NUMBER UDA1350ATS 2000 Mar 29 PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads 4 VERSION SOT341-1 Philips Semiconductors Preliminary specification IEC 958 audio DAC 6 UDA1350ATS BLOCK DIAGRAM handbook, full pagewidth TEST1 TEST4 TEST2 VDDA(PLL) VSSA(PLL) 18 4 24 VSSA TEST3 28 25 21 VDDA(DAC) VDDA VOUTL 22 15 Vref VSSA(DAC) 14 20 VOUTR 19 17 23 CLOCK AND TIMING CIRCUIT DAC DAC NOISE SHAPER VDDD(C) VSSD(C) L3MODE L3CLOCK L3DATA SELSTATIC 6 UDA1350ATS 12 INTERPOLATOR 10 9 8 L3 INTERFACE AUDIO FEATURE PROCESSOR 11 MUTE 26 SLICER SPDIF VDDD VSSD 13 5 IEC 958 DECODER 3 7 1, 2, 27 16 MGL847 n.c. LOCK Fig.1 Block diagram. 2000 Mar 29 5 RESET Philips Semiconductors Preliminary specification IEC 958 audio DAC 7 UDA1350ATS PINNING SYMBOL TYPE(1) PIN DESCRIPTION n.c. 1 − not connected n.c. 2 − not connected VDDD 3 DS digital supply voltage TEST1 4 DID test pin 1; must be connected to digital ground (VSSD) RESET 5 DISD reset input VDDD(C) 6 DS digital supply voltage for core VSSD 7 DGND digital ground L3DATA 8 DIOS L3 interface data input and output L3CLOCK 9 DIS L3 interface clock input L3MODE 10 DIS L3 interface mode input MUTE 11 DID mute control input VSSD(C) 12 DGND digital ground for core SPDIF 13 AI IEC 958 channel input VDDA(DAC) 14 AS analog supply voltage for DAC VOUTL 15 AO analog DAC left channel output LOCK 16 DO SPDIF and PLL lock indicator output VOUTR 17 AO analog DAC right channel output TEST2 18 DID test pin 2; must be connected to digital ground (VSSD) Vref 19 A DAC reference voltage VSSA(DAC) 20 AGND analog ground for DAC VSSA 21 AGND analog ground VDDA 22 AS analog supply voltage VSSA(PLL) 23 AGND analog ground for PLL VDDA(PLL) 24 AS analog supply voltage for PLL TEST4 25 DIU test pin 4; must be connected to the digital supply voltage (VDDD) SELSTATIC 26 DIU static pin control selection input n.c. 27 − not connected TEST3 28 DISD test pin 3; must be connected to digital ground (VSSD) Note 1. See Table 1. 2000 Mar 29 6 Philips Semiconductors Preliminary specification IEC 958 audio DAC Table 1 UDA1350ATS Pin type references PIN TYPE DESCRIPTION DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output A analog reference voltage AI analog input AO analog output handbook, halfpage n.c. 1 28 TEST3 n.c. 2 27 n.c. VDDD 3 26 SELSTATIC TEST1 4 25 TEST4 RESET 5 24 VDDA(PLL) VDDD(C) 6 23 VSSA(PLL) VSSD 7 L3DATA 8 21 VSSA L3CLOCK 9 20 VSSA(DAC) UDA1350ATS 22 VDDA 19 Vref L3MODE 10 18 TEST2 MUTE 11 17 VOUTR VSSD(C) 12 16 LOCK SPDIF 13 15 VOUTL VDDA(DAC) 14 MGL845 Fig.2 Pin configuration. 2000 Mar 29 7 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8 UDA1350ATS FUNCTIONAL DESCRIPTION When operating in the L3 control mode the device will mute on start-up. In L3 mode it is necessary to explicitly switch off the mute for audio output by means of the MT bit in the L3 register. The UDA1350ATS is a low cost audio IEC 958 decoder with an on-board DAC. The minimum audio input sampling frequency conforming to the IEC958 standard is 28.0 kHz and the maximum audio sampling frequency is 54.0 kHz. 8.1 In the L3 mode pin MUTE does not have any function (the same holds for several other pins) and can either be left open-circuit (since it has an internal pull-down resistor) or be connected to ground. Clock regeneration and lock detection The UDA1350ATS contains an on-board PLL for regenerating a system clock from the IEC 958 input bitstream. 8.3 Auto mute By default the outputs of the digital data output interface and the DAC will be muted until the IC is locked, regardless the level on pin MUTE (in static mode) or the state of bit MT of the sound feature register (in L3 mode). In this way only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. When the on-board clock has locked to the incoming frequency the lock indicator bit will be set and can be read via the L3 interface. Internally the PLL lock indication is combined with the PCM status bit of the input data stream. When both the IEC 958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, then pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data then pin LOCK is returned to LOW level. The lock indication output can be used, for example, for muting purposes. If needed this muting can be bypassed by setting bit AutoMT to logic 0 via the L3 interface. As a result the IC will no longer mute during out-of-lock situations. 8.4 8.2 Mute The UDA1350ATS data path consists of the IEC 958 decoder, the audio feature processor, digital interpolator and noise shaper and the digital-to-analog converters. The UDA1350ATS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC, by pin MUTE (in static mode) or via bit MT (in L3 mode) will result in a soft mute as presented in Fig.3. The cosine roll-off soft mute takes 32 × 32 samples = 24 ms at 44.1 kHz sampling frequency. 8.4.1 IEC 958 INPUT The UDA1350ATS IEC 958 decoder features an on-chip amplifier with hysteresis which amplifies the IEC 958 input signal to CMOS level (see Fig.4). All 24 bits of data for left and right are extracted from the input bitstream as well as several of the IEC 958 key channel-status bits. MGU119 1 Data path handbook, halfpage mute factor 0.8 0.6 handbook, halfpage 10 nF 0.4 75 Ω SPDIF 13 180 pF 0.2 UDA1350ATS MGS874 0 0 5 10 15 20 25 t (ms) Fig.3 Mute as a function of raised cosine roll-off. 2000 Mar 29 Fig.4 IEC 958 input circuit and typical application. 8 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS The extracted key parameters are: 8.4.4 • Pre-emphasis The third-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. • Audio sample frequency • Two-channel PCM indicator • Clock accuracy. Both the lock indicator and the key channel status bits are accessible via the L3 interface. 8.4.5 The UDA1350ATS supports the following sample frequencies and data bit rates: fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. The UDA1350ATS supports timing level I, II and III as specified by the IEC 958 standard. AUDIO FEATURE PROCESSOR The audio feature processor automatically provides de-emphasis for the IEC 958 data stream in the static pin control mode and default mute at start-up in the L3 control mode. The output voltage of the FSDAC is scaled proportionally with the power supply voltage. 8.5 When used in the L3 control mode it provides the following additional features: • Bass boost control using 4 bits • Treble control using 2 bits • Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum It should be noted that the static pin control mode and L3 control mode are mutual exclusive. In the static pin control mode pins L3MODE and L3DATA are used to select the format for the data output and input interface. • Soft mute control with raised cosine roll-off • De-emphasis selection of the incoming data stream for fs = 32.0, 44.1 and 48.0 kHz. INTERPOLATOR The UDA1350ATS includes an on-board interpolating filter which converts the incoming data stream from 1fs to 128fs by cascading a recursive filter and a FIR filter. Table 2 Interpolator characteristics PARAMETER CONDITIONS VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.03 >0.65fs −50 0 to 0.45fs 115 − −3.5 Stop band Dynamic range DC gain 2000 Mar 29 Control The UDA1350ATS can be controlled by means of static pins or via the L3 interface. For optimum use of the features of the UDA1350ATS the L3 control mode is recommended since only basic functions are available in the static pin control mode. • Volume control using 6 bits 8.4.3 FILTER STREAM DAC The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s 8.4.2 NOISE SHAPER 9 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.5.1 UDA1350ATS STATIC PIN CONTROL MODE The default values for all non-pin controlled settings are identical to the default values at start-up in the L3 control mode. Table 3 Pin description of static pin control mode PIN NAME VALUE FUNCTION Mode selection pin 26 SELSTATIC 1 select static pin control mode; must be connected to VDDD RESET 0 normal operation 1 reset Input pins 5 8 L3DATA 0 must be connected to VSSD 9 L3CLOCK 0 must be connected to VSSD 10 L3MODE 0 must be connected to VSSD 11 MUTE 0 normal operation 1 mute active 0 clock regeneration and IEC 958 decoder out-of-lock or non-PCM data detected 1 clock regeneration and IEC 958 decoder locked and PCM data detected Status pins 16 LOCK Test pins 4 TEST1 0 must be connected to digital ground (VSSD) 18 TEST2 0 must be connected to digital ground (VSSD) 25 TEST4 1 must be connected to digital supply voltage (VDDD) 28 TEST3 0 must be connected to digital ground (VSSD) 2000 Mar 29 10 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.5.2 UDA1350ATS L3 CONTROL MODE The L3 control mode allows maximum flexibility in controlling the UDA1350ATS. It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface. Table 4 Pin description in the L3 control mode PIN NAME VALUE FUNCTION Mode selection pin 26 SELSTATIC 0 select L3 control mode; must be connected to VSSD Input pins 5 RESET 0 normal operation 1 reset 8 L3DATA − must be connected to the L3-bus 9 L3CLOCK − must be connected to the L3-bus 10 L3MODE − must be connected to the L3-bus LOCK 0 clock regeneration and IEC 958 decoder out-of-lock or non-PCM data detected 1 clock regeneration and IEC 958 decoder locked and PCM data detected Status pins 16 Test pins 4 TEST1 0 must be connected to ground (VSSD) 18 TEST2 0 must be connected to ground (VSSD) 25 TEST4 1 must be connected to digital supply voltage (VDDD) 28 TEST3 0 must be connected to ground (VSSD) 2000 Mar 29 11 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6 8.6.1 UDA1350ATS L3 interface Basically two types of data transfers can be defined: • Write action: data transfer to the device GENERAL • Read action: data transfer from the device. The UDA1350ATS has an L3 microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. Remark: when the device is powered up, at least one L3CLOCK pulse must be given to the L3 interface to wake-up the interface before starting sending to the device (see Fig.5). This is only needed once after the device is powered up. The controllable settings are: • Restoring L3 defaults • Power-on 8.6.2 • Selection of filter mode and settings of treble and bass boost DEVICE ADDRESSING The device address consists of one byte with: • Volume settings • Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 5) • Selection of soft mute via cosine roll-off and bypass of auto mute • Address bits 2 to 7 representing a 6-bit device address. • Selection of de-emphasis (only effective in L3 control mode). Table 5 Selection of data transfer DOM The readable settings are: TRANSFER • Mute status of interpolator BIT 0 BIT 1 • PLL locked 0 0 not used • SPDIF input signal locked 1 0 not used • Audio Sample Frequency (ASF) 0 1 write data or prepare read • Valid PCM data detected 1 1 read data • Pre-emphasis of the IEC 958 input signal • ACcuracy of the Clock (ACC). 8.6.3 The exchange of data and control information between the microcontroller and the UDA1350ATS is accomplished through a serial hardware L3 interface comprising the following pins: After sending the device address, including DOM bits indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. • L3DATA: data line REGISTER ADDRESSING • L3MODE: mode line Basically there are three methods for register addressing: • L3CLK: clock line. 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.5). The exchange of bytes via the L3 interface is LSB first. 2. Addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see Fig.6). The L3 format has two modes of operation: • Address mode 3. Addressing for data read action: in this case the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid. • Data transfer mode. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.5). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. 2000 Mar 29 12 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... L3CLOCK L3MODE register address device address 0 L3DATA 1 data byte 1 data byte 2 Philips Semiconductors IEC 958 audio DAC 2000 Mar 29 L3 wake-up pulse after power-up 0 MGS753 DOM bits write Fig.5 Data write mode (for L3 version 2). 13 L3CLOCK L3MODE register address device address 1 DOM bits read 1 1 data byte 1 data byte 2 0/1 valid/non-valid prepare read send by the device Fig.6 Data read mode. MGS754 UDA1350ATS 0 1 register address Preliminary specification L3DATA device address Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6.4 UDA1350ATS For reading data from a device, the following six bytes are involved (see Table 7): DATA WRITE MODE The data write mode is explained in the signal diagram of Fig.5. For writing data to a device, four bytes must be sent (see Table 6): 1. One byte with the device address including ‘01’ for signalling the write action to the device. 2. One byte is sent with the register address from which data needs to be read. This byte starts with a ‘1’, which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with A6 being the MSB and A0 being the LSB. 1. One byte starting with ‘01’ for signalling the write action to the device, followed by the device address (‘011000’ for the UDA1350ATS). 2. One byte starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination address in binary format with A6 being the MSB and A0 being the LSB. 3. One byte with the device address including ‘11’ is sent to the device. The ‘11’ indicates that the device must write data to the microcontroller. 3. Two data bytes with D15 being the MSB and D0 being the LSB. 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1). It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 8.6.5 5. Two bytes, sent by the device to the bus, with the data information in binary format with D15 being the MSB and D0 being the LSB. DATA READ MODE For reading data from the device, first a prepare read must be done and then data read. The data read mode is explained in the signal diagram of Fig.6. Table 6 L3 write data FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 0 1 1 0 0 0 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 7 L3 read data FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 0 1 0 1 1 0 0 0 1 address device address 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 0 1 1 0 0 0 4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0 5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 2000 Mar 29 14 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6.6 UDA1350ATS INITIALISATION STRING For proper and reliable operation it is needed that the UDA1350ATS is initialized in the L3 control mode. This is needed to have the PLL start up after powering up of the device under all conditions. The initialisation string is given in Table 8. Table 8 L3 init string and set defaults after power-up. FIRST IN TIME BYTE L3 MODE LATEST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address 2 3 device address 0 1 0 1 1 0 0 0 data transfer register address 0 1 0 0 0 0 0 0 data transfer data byte 1 0 0 0 0 0 0 0 0 4 data transfer data byte 2 0 0 0 0 0 0 1 1 5 address 0 1 0 1 1 0 0 0 6 data transfer register address 0 1 1 1 1 1 1 1 7 data transfer data byte 1 0 0 0 0 0 0 0 0 8 data transfer data byte 2 0 0 0 0 0 0 0 0 2000 Mar 29 init string set defaults device address 15 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... UDA1350ATS register map BIT ADDR FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Writable settings 00H 10H 11H 40H system parameters PON default 1 sound features M1 M0 default 0 0 0(1) 0(1) 1(2) BB3 BB2 BB1 BB0 0 0 0 0 0(1) TR1 TR0 DE1 DE0 MT 0 0 0 0 1 volume control DAC VC5 VC4 VC3 VC2 VC1 VC0 default 0 0 0 0 0 0 Auto MT RST PLL multiplex parameters 0(1) 16 default 7FH 0(1) 0(1) 0(1) 0(1) Philips Semiconductors Table 9 OVERVIEW OF L3 INTERFACE REGISTERS IEC 958 audio DAC 2000 Mar 29 8.6.7 1 restore L3 defaults Readable settings 18H interpolator parameters 38H SPDIF input and lock parameters MT stat PLL lock SPD lock ASF1 ASF0 PCM stat PRE ACC1 ACC0 Notes 1. When writing new settings via the L3 interface, these bits should always remain logic 0 (default value) to warrant correct operation. Preliminary specification UDA1350ATS 2. When writing new settings via the L3 interface, these bits should always remain logic 1 (default value) to warrant correct operation. Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6.8 UDA1350ATS 8.6.8.5 WRITABLE REGISTERS 8.6.8.1 Restoring L3 defaults A 4-bit value to program the bass boost setting in combination with the filter mode settings. At fs = 44.1 kHz the −3 dB point for minimum setting is 250 Hz and the −3 dB point for maximum setting is 300 Hz. The default value is ‘0000’. By writing to the 7FH register, all L3 control values are restored to their default values. Only the L3 interface is affected, the system will not be reset. Consequently readable registers, which are not reset, can be affected. 8.6.8.2 Bass boost Table 13 Bass boost settings Power-on LEVEL (dB) A 1-bit value to switch the DAC on and off. BB3 Table 10 Power-on setting PON FUNCTION BB2 BB1 BB0 FLAT MIN. MAX. 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 power-down 0 0 1 0 0 4 4 1 power-on (default setting) 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 A 2-bit value to program the mode for the sound processing filters of bass boost and treble. 0 1 1 0 0 12 12 0 1 1 1 0 14 14 Table 11 Filter mode settings 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 1 1 0 0 0 18 24 1 1 0 1 0 18 24 1 1 1 0 0 18 24 1 1 1 1 0 18 24 8.6.8.3 Filter mode selection M1 M0 0 0 flat (default setting) 0 1 minimum 1 0 1 1 8.6.8.4 FUNCTION maximum Treble A 2-bit value to program the treble setting in combination with the filter mode settings. At fs = 44.1 kHz the −3 dB point for minimum setting is 3.0 kHz and the −3 dB point for maximum setting is 1.5 kHz. The default value is ‘00’. 8.6.8.6 A 2-bit value to enable the digital de-emphasis filter. Table 14 De-emphasis selection Table 12 Treble settings LEVEL (dB) TR1 De-emphasis TR0 DE1 DE0 FUNCTION 0 0 other (default setting) FLAT MIN. MAX. 0 1 fs = 32.0 kHz 0 0 0 0 0 1 0 fs = 44.1 kHz 0 1 0 2 2 1 1 fs = 48.0 kHz 1 0 0 4 4 1 1 0 6 6 2000 Mar 29 17 Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6.8.7 UDA1350ATS Soft mute 8.6.8.9 A 1-bit value to enable the digital mute. A 1-bit value to activate mute during out-of-lock. In normal operation the output is automatically hard muted when an out-of-lock situation is detected. Setting this bit to logic 0 will disable that function. Table 15 Soft mute selection MT FUNCTION 0 no muting 1 muting (default setting) 8.6.8.8 Auto mute Table 17 Auto mute setting Auto MT Volume control A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to −∞ dB in steps of 1 dB. 0 do not mute output during out-of-lock 1 mute output during out-of-lock (default setting) 8.6.8.10 Table 16 Volume settings of the interpolator FUNCTION PLL reset A 1-bit value to reset the PLL. This is the bit which is set in the initialisation string. When this bit is asserted, the PLL will be reset and the output clock of the PLL will be forced to its lowest value, which is in the area of a few MHz. VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 RST PLL : : : : : : : 0 normal operation 1 1 1 0 1 1 −58 1 PLL is reset 1 1 1 1 0 0 −59 1 1 1 1 0 1 −60 1 1 1 1 1 0 −∞ 1 1 1 1 1 1 −∞ 2000 Mar 29 Table 18 PLL reset 18 FUNCTION Philips Semiconductors Preliminary specification IEC 958 audio DAC 8.6.9 UDA1350ATS 8.6.9.5 READABLE REGISTERS 8.6.9.1 Mute status A 1-bit value which indicates whether the IEC 958 input contains PCM audio data or other binary data. A 1-bit value indicating whether the interpolator is muting or not muting. Table 23 Two channel PCM input detection Table 19 Interpolator mute status MT stat PCM stat FUNCTION 0 no muting 1 muting 8.6.9.2 Pre-emphasis detection PRE FUNCTION out-of-lock 1 locked input without two channel PCM data Table 24 Pre-emphasis detection Table 20 PLL lock indication 0 input with two channel PCM data 1 A 1-bit value which indicates whether the pre-emphasis bit was set on the IEC 958 input signal or not set. A 1-bit value indicating that the clock regeneration is locked. PLL lock FUNCTION 0 8.6.9.6 PLL lock detection 8.6.9.3 PCM detection 8.6.9.7 SPDIF lock detection FUNCTION 0 no pre-emphasis 1 pre-emphasis Clock accuracy detection A 2-bit value indicating the timing accuracy of the IEC 958 input signal is conforming to the IEC 958 specification. A 1-bit value indicating the IEC 958 decoder is locked and is decoding correct data. Table 25 Input signal accuracy detection Table 21 SPDIF lock detection ACC1 ACC0 FUNCTION SPD lock FUNCTION 0 0 level II 0 not locked or non-PCM data detected 0 1 level I 1 locked and PCM data detected 1 0 level III 1 1 undefined 8.6.9.4 Audio sample frequency detection A 2-bit value indicating the audio sample frequency of the IEC 958 input signal. Table 22 Audio sample frequency detection ASF1 ASF0 0 0 44.1 kHz 0 1 undefined 1 0 48.0 kHz 1 1 32.0 kHz 2000 Mar 29 FUNCTION 19 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VDD supply voltage Txtal CONDITIONS MIN. note 1 MAX. UNIT 2.7 5.0 V crystal temperature −25 +150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage Human Body Model (HBM); note 2 −2000 +2000 V Machine Model (MM); note 3 −200 +200 V 200 mA Ilu(prot) latch-up protection current Tamb = 125 °C; VDD = 3.6 V Isc(DAC) short-circuit current of DAC Tamb = 0 °C; VDD = 3 V; note 4 output short-circuited to VSSA(DAC) − 482 mA output short-circuited to VDDA(DAC) − 346 mA Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant, except pin VSSA(PLL) which can withstand ESD pulses of −130 to +130 V. 4. DAC operation after short-circuiting cannot be warranted. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 85 K/W in free air 11 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 958 input with fs = 48.0 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies; note 1 VDDA analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) analog supply voltage for DAC 2.7 3.0 3.6 V VDDA(PLL) analog supply voltage for PLL 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V VDDD(C) digital supply voltage for core 2.7 3.0 3.6 V IDDA(DAC) analog supply current of DAC power-on − 8.0 − mA power-down − 750 − µA IDDA(PLL) analog supply current of PLL − 0.7 − mA IDDD digital supply current − 2.0 − mA IDDD(C) digital supply current of core − 16.0 − mA P power dissipation DAC in playback mode − 80 − mW DAC in Power-down mode − 58 − mW 2000 Mar 29 20 Philips Semiconductors Preliminary specification IEC 958 audio DAC SYMBOL UDA1350ATS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital input pins VIH HIGH-level input voltage 0.8VDD − VDD + 0.5 V VIL LOW-level input voltage −0.5 − +0.2VDD V Vhys(RESET) hysteresis voltage on pin RESET − 0.8 − V ILI input leakage current − − 10 µA Ci input capacitance − − 10 pF Rpu(int) internal pull-up resistance 16 33 78 kΩ Rpd(int) internal pull-down resistance 16 33 78 kΩ Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85VDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V IL(max) maximum load current − 3 − mA Digital-to-analog converter; note 2 Vref reference voltage measured with respect to VSSA 0.45VDDA 0.50VDDA 0.55VDDA V Vo(rms) output voltage (RMS value) note 3 − 900 − mV at 0 dB − −90 −85 dB at −40 dB; A-weighted − −60 −55 dB 100 − dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio fi = 1.0 kHz tone S/N signal-to-noise ratio fi = 1.0 kHz tone; code = 0; 95 A-weighted αcs channel separation fi = 1.0 kHz tone − 96 − dB ∆Vo unbalance of output voltages fi = 1.0 kHz tone − 0.1 0.4 dB IEC 958 input Vi(p-p) AC input voltage (peak-to-peak value) 0.2 0.5 3.3 V Ri input resistance − 6 − kΩ Vhys hysteresis voltage − 40 − mV Notes 1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100 Ω must be used in order to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage. 2000 Mar 29 21 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS 12 TIMING CHARACTERISTICS VDDD = VDDA = 2.7 to 3.6 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Device reset trst − 250 − µs fs = 32.0 kHz − 97.0 − ms fs = 44.1 kHz − 91.0 − ms fs = 48.0 kHz − 90.0 − ms reset active time PLL lock time tlock time to lock Microcontroller L3 interface timing (see Figs 7 and 8) Tcy(CLK)(L3) L3CLOCK cycle time 500 − − ns tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time for address mode 190 − − ns th(L3)A L3MODE hold time for address mode 190 − − ns tsu(L3)D L3MODE set-up time for data transfer mode 190 − − ns th(L3)D L3MODE hold time for data transfer mode 190 − − ns t(stp)(L3) L3MODE stop time in data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 − − ns th(L3)DA L3DATA hold time in address and data transfer mode 30 − − ns 2000 Mar 29 22 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 7 BIT 0 L3DATA MGL723 Fig.7 Timing for address mode. handbook, full pagewidth tstp(L3) tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA tsu(L3)DA L3DATA WRITE BIT 7 BIT 0 MGL882 Fig.8 Timing for data transfer mode. 2000 Mar 29 23 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... X1 VDDA X1 L27 VDDD(C) X1 BZN32A07 C11 100 µF (16 V) X1 L3CLOCK X1 L3MODE X1 24 C45 C48 180 pF (50 V) R41 75 Ω VDDD(C) 28 25 14 L3DATA X1 SELSTATIC SPDIF VDDA VSSA(DAC) X1 X1 TEST4 18 VDDA(DAC) X1 X1 TEST3 X1 TEST1 X1 X1 VDDA(PLL) 4 TEST2 X1 VSSA(PLL) 24 22 BZN32A07 C14 100 µF (16 V) C43 100 nF (50 V) 20 19 Vref X1 C44 100 nF (50 V) 21 6 RESET X1 C13 10 µF (16 V) C40 VDDD(C) 100 nF (50 V) 9 10 11 8 1 VDDD(C) X16 X11 VSSA 23 L29 VDDD 5 X1 IEC channel VDDA C41 100 nF (50 V) L3-bus J14 3 static 2 1 L3 C42 100 nF (50 V) Philips Semiconductors C12 100 µF (16 V) IEC 958 audio DAC BZN32A07 13 APPLICATION INFORMATION handbook, full pagewidth 2000 Mar 29 L26 VDDA UDA1350ATS 26 2 12 13 10 nF (50 V) 27 15 MUTE X1 n.c. X1 n.c. X1 VDDD(C) 3 2 1 J26 mute no mute VSSD(C) X1 n.c. X1 VOUTL X1 C15 47 µF (16 V) R44 100 Ω R43 10 kΩ X18 output left X13 ground DGND 17 AGND DGND VDDD VSSD LOCK VDDD MGL846 R38 1Ω C9 100 µF (16 V) R39 1 kΩ C28 100 nF (50 V) V5 lock Fig.9 Test and application diagram. R46 100 Ω R45 10 kΩ X19 output right X14 UDA1350ATS C5 100 µF (16 V) VDDD(C) C16 Preliminary specification J2 C3 100 µF (16 V) VDDA VOUTR X1 47 µF (16 V) 16 X1 J3 7 X1 +3 V 3 VDDD J1 X1 AGND Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS 14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2000 Mar 29 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-150 25 o Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS If wave soldering is used the following conditions must be observed for optimal results: 15 SOLDERING 15.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.3 15.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Mar 29 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 26 Philips Semiconductors Preliminary specification IEC 958 audio DAC 15.5 UDA1350ATS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Mar 29 27 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS 16 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Mar 29 28 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS NOTES 2000 Mar 29 29 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS NOTES 2000 Mar 29 30 Philips Semiconductors Preliminary specification IEC 958 audio DAC UDA1350ATS NOTES 2000 Mar 29 31 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/02/pp32 Date of release: 2000 Mar 29 Document order number: 9397 750 06925