Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DESCRIPTION PIN CONFIGURATION The NE5241 is a complete stereo digital to audio converter for the Dolby ADM digital audio system, which allows CD quality stereo audio to be delivered with data rates on the order of 400 to 600kb/s. The NE5241 is intended for use in high quality consumer digital audio equipment for the reproduction of broadcast (or pre-recorded) digital audio. The IC contains channel de-multiplexing data input latches, control signal filter drivers and buffers, variable gain integrators, and variable de-emphasis filters. Precision, temperature compensated voltage reference circuitry assures accurate performance over temperature. The IC is implemented in a bipolar process to achieve low noise, low distortion, and wide dynamic range. The NE5241 is an improved version of the NE5240, which has been discontinued. N, D Packages MULTI OUT 1 1 28 MULTI OUT 2 VCC 2 27 AGND VARZ 1 3 26 VARZ 2 OUT 1 4 25 OUT 2 24 FEEDBACK 2 FEEDBACK 1 5 23 INT IN 2 INT IN 1 6 22 EM FILT IN 2 EM FILT IN 1 7 21 EM FILT OUT 2 EM FILT OUT 1 8 20 SS FILT IN 2 SS FILT IN 1 9 19 SS FILT OUT 2 SS FILT OUT 1 10 Note: The NE5241 is available only to licensees of Dolby Laboratories Licensing Corporation, from who licensing and applications information must be obtained. Dolby is a registered trademark of Dolby Laboratories Licensing Corporation, San Francisco, California. VDD 11 18 DGND SS 12 17 REX AD 13 16 VREF 15 CK EM 14 APPLICATIONS • High quality digital audio transmission systems • Pre-recorded digital audio • Satellite delivered digital audio • Cable TV delivered digital audio • Microwave delivered digital audio • Terrestrial delivered digital audio • Digital audio for advanced television sound TOP VIEW SR01021 Figure 1. Pin Configuration FEATURES • Wide dynamic range: >95dB • Low distortion: <0.1% @ 1kHz, 0dB • TTL, CMOS compatible logic inputs • Wide bandwidth: DC to > 20kHz • Complete decoder implementation in one IChip ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG # 28-Pin Plastic Dual In-Line Package (DIP) DESCRIPTION 0 to +70°C NE5241N SOT117-2 28-Pin Small Outline Large (SOL) Package 0 to +70°C NE5241D SOT136-1 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VCC Analog supply voltage VDD Logic supply voltage TA Operating ambient temperature range TSTG TJ TSOLD Lead temperature (soldering 60 sec) RATING UNIT +15 V +7 V 0 to +70 °C Storage temperature range –65 to +150 °C Junction temperature –65 to +150 °C +300 °C 48 70 °C/W °C/W Thermal impedance θJA March 19, 1992 N package D package 1 853-1602 06126 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 PIN DESCRIPTIONS PIN # SYMBOL DESCRIPTION 1 MULTI OUT 1 2 VCC Multiplier output, channel 1 3 VARZ 1 Variable impedance, channel 1 4 OUT 1 Main output, channel 1 5 FEEDBACK 1 Summing amp input, channel 1 6 INT IN 1 Integrator amp input, channel 1 7 EM FILTER IN 1 Emphasis filter buffer input, channel 1 8 EM FILTER OUT 1 Emphasis filter driver output, channel 1 9 SS FILTER IN 1 Step-size filter buffer input, channel 1 10 SS FILTER OUT 1 Step-size filter driver output, channel 1 11 VDD Logic supply voltage 12 SS Step-size data input 13 AD Audio data input 14 EM Emphasis data input 15 CK Data clock input 16 VREF Reference voltage bypass 17 REX Variable impedance reference resistor 18 DGND Digital ground 19 SS FILTER OUT 2 Step-size filter driver output, channel 2 20 SS FILTER IN 2 Step-size filter buffer input, channel 2 21 EM FILTER OUT 2 Emphasis filter driver output, channel 2 22 EM FILTER IN 2 Emphasis filter buffer input, channel 2 Analog supply voltage 23 INT IN 2 Integrator amp input, channel 2 24 FEEDBACK 2 Summing amp input, channel 2 25 OUT 2 Main output, channel 2 26 VARZ 2 Variable impedance, channel 2 27 AGND 28 MULT OUT 2 March 19, 1992 Analog ground Multiplier output, channel 2 2 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DC ELECTRICAL CHARACTERISTICS All specifications are at TA=25°C, VDD=5V, VCC=12V. Test circuit Figure 1. SYMBOL PARAMETER TEST CONDITIONS LIMITS Min Typ Max UNIT VCC Analog supply voltage 10.8 12 13.2 VDD Digital supply voltage 4.7 5 5.3 V ICC Analog supply current 25 40 mA IDD Digital supply current 12 20 mA VIH HIGH level input voltage VIL LOW level input voltage IIH HIGH level input current Pins SS, AD, EM = 2V IIL LOW level input current Pins SS, AD, EM = 0.8V tS Data setup time 150 tH Data hold time 150 IB Control signal buffer bias current 10 Integrating amp gain 22 2.0 V V Pins SS, AD, EM 0.8 V 1 10 µA 1 5 µA ns ns 30 nA dB AC ELECTRICAL CHARACTERISTICS All specifications are at TA=25°C, VDD=5V, VCC=12V, Audio data rate = 204kHz. 0dB is defined as 0.775VRMS. Test circuit Figure 4. SYMBOL PARAMETER TEST CONDITIONS Output voltage (reference level)1 LIMITS UNIT Min Typ Max –6 –4.5 –2.5 dBu 0.2 1.2 dB Channel balance (reference level)1 Channel balance change2 20% < SS < 80% 0.2 1.0 dB Channel balance change2 10% < SS < 90% 0.4 1.5 dB error3 20% < SS < 80% 0.5 3.0 dB Step-size tracking error3 10% < SS < 90% 1.0 4.0 dB Step-size tracking Headroom4 13 Noise5 20Hz – 20kHz –80 –78 dBu Noise5 CCIR/ARM –89 –85 dBu Mute noise6 CCIR/ARM –93 –88 dBu Dynamic range7 98 THD Total harmonic distortion1 0dB (ref level) 0.8 0.2 % THD Total harmonic distortion8 +13dB (max level) 0.13 0.5 % Variable de-emph calibration error9 8kHz EM = 40% –1 0.2 1 dB Freq. response error 2kHz EM = 10% –1.8 0.2 1.5 dB Freq. response error 12kHz EM = 60% –2.3 0.25 2.3 dB Freq. response error 15kHz EM = 70% –2.5 0.5 2.5 dB Dynamic offset, emphasis10 AC measurement –43 –30 dB Dynamic offset, step-size11 AC measurement –39 –24 dB 1kHz 75 Channel separation dB NOTES: Test patterns referred to are produced by the Dolby Cat. No. 346 ADM Test Data Generator. 1. Dolby ADM reference level, Dolby test pattern 00. This is 10dB below the nominal 100% modulation level. 2. The channel balance may change over the operating range. This specification is the channel balance change from the intial channel balance which was measured at reference level. 3. The gain should change by 36.12dB as the step-size data is changed from 20% to 80% duty cycle, or 48.16dB as the data changes from 10% to 90%. The tracking error is the amount by which the gain change deviates from the desired value. 4. This is headroom over Dolby ADM reference level. 5. Idling data patterns, Dolby test pattern 02 with respect to test 01. 6. Muted data patterns, Dolby test pattern 04. 7. Difference between output voltage plus headroom, and CCIR/ARM weighted mute noise level. 8. Test level is 13dB over Dolby ADM reference level. Dolby test pattern 08. 9. Measured at 8.00kHz, with emphasis data at 40% duty cycle. This may be trimmed to zero by adjusting the resistor at Pin 17. 10. Dolby test pattern 48 relative to test 00. Duty cycle alternates from 10 to 70%. 11. Dolby test pattern 49 relative to test 00. Duty cycle alternates from 10 to 70%. March 19, 1992 3 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 desirable to place a ground plane under the NE5241. This reduces the inevitable cross-talk of the digital data (with several volts of swing) into the audio (which has a noise level on the order of 40µV). A ground plane is necessary to obtain the ultimate in noise performance. APPLICATIONS INFORMATION The application diagram shows the complete Dolby ADM decoder using the NE5241. The decoder is followed by a line driving amplifier, which, depending on the application, may not be necessary. For best frequency response accuracy, the following parts should be tight tolerance: R13 to R21 should be 1%, and C13 to C20 should be 2.5%. The variable de-emphasis pole position may be trimmed by adjusting the value of R17. The variable impedance Pins 3 and 26 are very sensitive to noise pickup. Keep the lead to C15 and C18 as short as possible. Excessive stray capacitance on the multiplier output, Pins 1 and 28, will adversely affect performance. Keep the leads to R13 and R19 short. It is The timing diagram illustrates how the data is clocked into the NE5241. The two audio channels share the three data input lines: audio data, step-size data, and emphasis data. During the low-to-high clock transition, the data is clocked into channel 1. During the high-to-low clock transition, the data is clocked into channel 2. The data must be stable during the clock transition. TIMING DIAGRAM CLOCK tS tH AUDIO DATA STEP-SIZE DATA EMPHASIS DATA CH 1 CH 2 CH 1 CH 2 Figure 2. Timing Diagram March 19, 1992 4 CH 1 SR01022 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 BLOCK DIAGRAM AND TEST CIRCUIT R1 4.3k R2 43k C1 0.47µF R3 360k C2 47nF R15 4.87k C3 4.7nF R13 4.99k VDD 11 R4 4.3k R5 43k R6 360k C4 0.47µF C5 47nF C6 4.7nF 10 8 R14 499k C13 0.1µF 7 9 1 C14 10nF 5 6 INTEGRATOR AMP SUMMING AMP 22dB 12 4 R16 VOUT 6.34k CH.A + eX VDD SSD – 14dB C15 220pF NE5241 C16 3.9nF 3 AD SBD 2 13 REFERENCE GENERATOR REX VH INPUT LOGIC 14 VR 16 VREF VL 27 AGND CK VCC 17 220µF R17 118k C17 15 26 SUMMING AMP eX DGND INTEGRATOR AMP + – 18 19 21 22 20 28 23 NOTE: One channel of the application shown with external components. 25 R18 6.34k VOUT CH.B C19 3.9nF 24 SR01023 Figure 3. Block Diagram and Test Circuit March 19, 1992 C18 220pF 5 Philips Semiconductors Product specification Dolby ADM digital audio decoder NE5241 DOLBY ADM DECODER R1 4.3k R2 43k C1 0.47µF DATA INPUT IC R3 360k C2 47nF C3 4.7nF R4 4.3k R5 43k R6 360k C4 0.47µF C5 47nF C6 4.7nF 10 8 R14 499 R22 1k C14 10nF R13 4.99k 7 1nF 0.1µF R15 4.87k MULT OUT 1 INT FEED– IN 1 BACK 1 14 EM 15 CK EMPHASIS DATA DATA CLOCK 12VDC 5VDC 2 11 27 18 17 R17 118k + 4 OUT 1 VARZ 3 C15 220pF 22µF C16 3.9nF R26 22k 16 NE5241 VCC 1 C24 CH OUT 6.3k 13 AD AUDIO DATA R24 100 – 9 EM SS FILTER IN 1 SS EM FILTER 12 SS OUT 1 STEP-SIZE DATA LINE DRIVE AMPLIFIER 100µF VDD AGND VARZ C18 220pF DGND FILTER IN 2 EM SS REX FILTER OUT 2 SS EM 19 21 R10 4.3k C10 0.47µF 22 20 R11 43k C11 47nF R12 360k OUT 2 MULT OUT 2 28 R19 4.99k INT FEED– IN 2 BACK 2 23 24 C7 0.47µF R8 43k C18 3.9nF C26 22µF + R25 100 – 4.87k CH 2 OUT R27 22k R21 499 10nF R7 4.3k 6.3k 1nF 0.1µF C12 4.7nF 2 R23 1k R9 360k C8 47nF C9 4.7nF SR01024 Figure 4. NE5241 Application Circuit March 19, 1992 6