74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 02 — 18 September 2007 Product data sheet 1. General description The 74LVC1G3157 is a low-power, low-voltage, high-speed Si-gate CMOS device. The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z). Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features ■ Wide supply voltage range from 1.65 V to 5.5 V ■ Very low ON resistance: ◆ 7.5 Ω (typical) at VCC = 2.7 V ◆ 6.5 Ω (typical) at VCC = 3.3 V ◆ 6 Ω (typical) at VCC = 5 V ■ Switch current capability of 32 mA ■ Break-before-make switching ■ High noise immunity ■ CMOS low power consumption ■ TTL interface compatibility at 3.3 V ■ Latch-up performance meets requirements of JESD 78 Class I ■ ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V ■ Control input accepts voltages up to 5.5 V ■ Multiple package options ■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number 74LVC1G3157GW Package Temperature range Name Description Version −40 °C to +125 °C plastic surface-mounted package; 6 leads SOT363 SC-88 74LVC1G3157GV −40 °C to +125 °C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G3157GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74LVC1G3157GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 4. Marking Table 2. Marking Type number Marking code 74LVC1G3157GW YJ 74LVC1G3157GV YJ 74LVC1G3157GM YJ 74LVC1G3157GF YJ 5. Functional diagram Y1 S Z S 6 1 Y1 Z 4 Y0 3 Y0 001aac354 Fig 1. Logic symbol 001aac355 Fig 2. Logic diagram 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 2 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74LVC1G3157 74LVC1G3157 Y1 1 6 S GND 2 5 VCC Y0 3 4 Z Y1 1 6 S GND 2 5 VCC Y0 3 4 Z Transparent top view 001aac356 Fig 3. Pin configuration SOT363 and SOT457 001aac357 Fig 4. Pin configuration SOT886 74LVC1G3157 Y1 1 6 S GND 2 5 VCC Y0 3 4 Z 001aaf546 Transparent top view Fig 5. Pin configuration SOT891 6.2 Pin description Table 3. Pin description Symbol Pin Description Y1 1 independent input or output GND 2 ground (0 V) Y0 3 independent input or output Z 4 common output or input VCC 5 supply voltage S 6 select input 7. Functional description Table 4. Function table[1] Input S Channel on L Y0 H Y1 [1] H = HIGH voltage level; L = LOW voltage level. 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 3 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] VI input voltage IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V ISK switch clamping current VI < −0.5 V or VI > VCC + 0.5 V [2] VSW switch voltage enable and disable mode VSW > −0.5 V or VSW < VCC + 0.5 V Min Max Unit −0.5 +6.5 V −0.5 +6.5 V −50 - mA - ±50 mA −0.5 VCC + 0.5 V ISW switch current - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [3] [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. [3] For SC-88 and SC-74 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate Conditions Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V enable and disable mode [1] 0 - VCC V −40 - +125 °C VCC = 1.65 V to 2.7 V [2] - - 20 ns/V VCC = 2.7 V to 5.5 V [2] - - 10 ns/V [1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit for the voltage drop across the switch. [2] Applies to control signal levels. 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 4 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter HIGH-level input voltage VIH −40 °C to +85 °C Conditions VCC = 1.65 V to 1.95 V LOW-level input voltage Min Max Min Max Unit 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3 V to 3.6 V 2.0 - - 2.0 - V 0.7VCC - - 0.7VCC - V VCC = 4.5 V to 5.5 V VIL −40 °C to +125 °C Typ[1] VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 3 V to 3.6 V - - 0.8 - 0.8 V 0.3VCC V VCC = 4.5 V to 5.5 V 0.35VCC V - - 0.3VCC - ±0.1 ±2 - ±10 µA II input leakage current pin S; VI = 5.5 V or GND; VCC = 0 V to 5.5 V [2] IS(OFF) OFF-state leakage current VI = VIH or VIL; VCC = 5.5 V; see Figure 6 [2] - ±0.1 ±5 - ±20 µA IS(ON) ON-state leakage current VI = VIH or VIL; VCC = 5.5 V; see Figure 7 [2] - ±0.1 ±5 - ±20 µA ICC supply current VI = 5.5 V or GND; VSW = GND or VCC; IO = 0 A; VCC = 1.65 V to 5.5 V [2] - 0.1 10 - 40 µA ∆ICC additional pin S; VI = VCC − 0.6 V; IO = 0 A; supply current VCC = 5.5 V; VSW = GND or VCC [2] - 5 500 - 5000 µA CI input capacitance - 2.5 - - - pF CS(OFF) OFF-state capacitance - 6.0 - - - pF CS(ON) ON-state capacitance - 18 - - - pF [1] Typical values are measured at Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 5 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.1 Test circuits VCC VIL or VIH S Y0 1 Z Y1 2 switch switch S 1 VIH 2 VIL IS VO VI GND 001aac358 VI = VCC or GND and VO = GND or VCC. Fig 6. Test circuit for measuring OFF-state leakage current VCC VIL or VIH IS S Y0 1 Z Y1 2 switch S 1 VIH 2 VIL switch VI VO GND 001aac359 VI = VCC or GND and VO = open circuit. Fig 7. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(peak) Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 34.0 130 - 195 Ω ISW = 8 mA; VCC = 2.3 V to 2.7 V - 12.0 30 - 45 Ω ISW = 12 mA; VCC = 2.7 V - 10.4 25 - 38 Ω ISW = 24 mA; VCC = 3 V to 3.6 V - 7.8 20 - 30 Ω ISW = 32 mA; VCC = 4.5 V to 5.5 V - 6.2 15 - 23 Ω ON resistance (peak) VI = GND to VCC; see Figure 8 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 6 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(rail) Parameter ON resistance (rail) −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max ISW = 4 mA; VCC = 1.65 V to 1.95 V - 8.2 18 - 27 Ω ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.1 16 - 24 Ω ISW = 12 mA; VCC = 2.7 V - 6.9 14 - 21 Ω ISW = 24 mA; VCC = 3 V to 3.6 V - 6.5 12 - 18 Ω ISW = 32 mA; VCC = 4.5 V to 5.5 V - 5.8 10 - 15 Ω ISW = 4 mA; VCC = 1.65 V to 1.95 V - 10.4 30 - 45 Ω ISW = 8 mA; VCC = 2.3 V to 2.7 V - 7.6 20 - 30 Ω ISW = 12 mA; VCC = 2.7 V - 7.0 18 - 27 Ω ISW = 24 mA; VCC = 3 V to 3.6 V - 6.1 15 - 23 Ω - 4.9 10 - 15 Ω ISW = 4 mA; VCC = 1.65 V to 1.95 V - 26.0 - - - Ω VI = GND; see Figure 8 VI = VCC; see Figure 8 ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC [2] ISW = 8 mA; VCC = 2.3 V to 2.7 V - 5.0 - - - Ω ISW = 12 mA; VCC = 2.7 V - 3.5 - - - Ω ISW = 24 mA; VCC = 3 V to 3.6 V - 2.0 - - - Ω ISW = 32 mA; VCC = 4.5 V to 5.5 V - 1.5 - - - Ω [1] Typical values are measured at Tamb = 25 °C and nominal VCC. [2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 7 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 10.3 ON resistance test circuit and graphs mna673 40 RON (Ω) 30 VSW V switch VCC VIL or VIH S Y0 1 Z Y1 2 (1) S 1 VIL 2 VIH 20 switch (2) (3) 10 (4) (5) VI ISW GND 0 0 1 2 3 4 5 VI (V) 001aac360 RON = VSW / ISW. (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 8. Test circuit for measuring ON resistance 001aaa712 55 RON (Ω) Fig 9. Typical ON resistance as a function of input voltage; Tamb = 25 °C 001aaa708 15 RON (Ω) 45 13 35 11 (4) (3) (2) (1) (1) (2) 25 9 (3) (4) 15 7 5 5 0 0.4 0.8 1.2 1.6 2.0 0 0.5 VI (V) (1) Tamb = 125 °C. (2) Tamb = 85 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (4) Tamb = −40 °C. 2.0 2.5 Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V 74LVC1G3157_2 Product data sheet 1.5 VI (V) (1) Tamb = 125 °C. Fig 10. ON resistance as a function of input voltage; VCC = 1.8 V 1.0 © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 8 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 001aaa709 13 001aaa710 10 RON (Ω) RON (Ω) 11 8 (1) (1) 9 (2) (2) 6 (3) (3) 7 (4) (4) 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 0 1 2 3 4 VI (V) (1) Tamb = 125 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (4) Tamb = −40 °C. Fig 12. ON resistance as a function of input voltage; VCC = 2.7 V Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V 001aaa711 7 RON (Ω) 6 5 (1) (2) (3) 4 (4) 3 0 1 2 3 4 5 VI (V) (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 9 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter propagation delay tpd enable time ten −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V - - 2 - 3.0 ns VCC = 2.3 V to 2.7 V - - 1.2 - 2.0 ns VCC = 2.7 V - - 1.0 - 1.5 ns VCC = 3 V to 3.6 V - - 0.8 - 1.5 ns VCC = 4.5 V to 5.5 V - - 0.6 - 1.0 ns VCC = 1.65 V to 1.95 V 1.0 8.7 14 1.0 14.0 ns VCC = 2.3 V to 2.7 V 1.0 5.3 7.5 1.0 7.5 ns VCC = 2.7 V 1.0 4.9 6.0 1.0 6.0 ns VCC = 3 V to 3.6 V 0.5 4.0 5.5 0.5 5.5 ns 0.5 3.0 4.0 0.5 4.0 ns VCC = 1.65 V to 1.95 V 2.5 6.0 8.5 2.5 8.5 ns VCC = 2.3 V to 2.7 V 2.0 4.4 6.0 2.0 6.0 ns VCC = 2.7 V 1.5 4.2 5.0 1.5 5.0 ns VCC = 3 V to 3.6 V 1.5 3.6 4.5 1.5 4.5 ns VCC = 4.5 V to 5.5 V 0.8 2.9 3.5 0.8 3.5 ns VCC = 1.65 V to 1.95 V 0.5 - - 0.5 - ns VCC = 2.3 V to 2.7 V 0.5 - - 0.5 - ns VCC = 2.7 V 0.5 - - 0.5 - ns VCC = 3 V to 3.6 V 0.5 - - 0.5 - ns VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - ns Z to Yn or Yn to Z; see Figure 15 S to Yn; see Figure 16 [2][3] [4] VCC = 4.5 V to 5.5 V disable time tdis break-before-make time tb-m −40 °C to +125 °C Unit Typ[1] S to Yn; see Figure 16 [5] [6] see Figure 17 [1] Typical values are measured at Tamb = 25 °C and nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPLZ and tPHZ. [6] Break-before-make specified by design. 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 10 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits VI Yn or Z input VM VM GND tPLH tPHL VOH Z or Yn output VM VM VOL 001aac361 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. Input (Yn or Z) to output (Z or Yn) propagation delays VI S input VM GND tPLZ tPZL VCC Yn output LOW to OFF OFF to LOW VM VX VOL tPZH tPHZ VOH Yn VY output HIGH to OFF OFF to HIGH VM GND switch enabled switch disabled switch enabled 001aac362 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 11 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer VCC VI G VO RL 0.5VCC S Y0 Z Y1 CL GND 001aac367 a. Test circuit VI 0.5VI 0.9VO 0.9VO VO t b-m 001aac368 b. Input and output measurement points Fig 17. Test circuit for measuring break-before-make timing VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 18. Load circuit for switching times 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 12 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Table 11. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 50 pF 500 Ω open GND 2VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 50 pF 500 Ω open GND 2VCC 2.7 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2VCC 3 V to 3.6 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2VCC 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2VCC 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C. Symbol Parameter Conditions THD total harmonic distortion fi = 600 Hz to 20 kHz; RL = 600 Ω; CL = 50 pF; VI = 0.5 V (p-p); see Figure 19 f(-3dB) αiso Qinj −3 dB frequency response isolation (OFF-state) charge injection Min Typ Max Unit VCC = 1.65 V - 0.260 - % VCC = 2.3 V - 0.078 - % VCC = 3.0 V - 0.078 - % VCC = 4.5 V - 0.078 - % VCC = 1.65 V - 200 - MHz VCC = 2.3 V - 300 - MHz VCC = 3.0 V - 300 - MHz VCC = 4.5 V - 300 - MHz RL = 50 Ω; CL = 5 pF; see Figure 20 RL = 50 Ω; CL = 5 pF; fi = 10 MHz; see Figure 21 VCC = 1.65 V - −42 - dB VCC = 2.3 V - −42 - dB VCC = 3.0 V - −40 - dB VCC = 4.5 V - −40 - dB VCC = 1.8 V - 3.3 - pC VCC = 2.5 V - 4.1 - pC VCC = 3.3 V - 5.0 - pC VCC = 4.5 V - 6.4 - pC VCC = 5.5 V - 7.5 - pC CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; fi = 1 MHz; RL = 1 MΩ; see Figure 22 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 13 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 11.3 Test circuits 0.5VCC VCC VIL or VIH 0.1 µF S Y0 1 Z Y1 2 S 1 VIL 2 VIH RL 10 µF switch D CL 600 Ω fi switch GND 001aac363 Fig 19. Test circuit for measuring total harmonic distortion 0.5VCC VCC VIL or VIH fi 0.1 µF S Y0 1 Z Y1 2 RL switch S 1 VIL 2 VIH switch CL 50 Ω dB GND 001aac364 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB. Fig 20. Test circuit for measuring the frequency response when switch is in ON-state 0.5VCC 0.5VCC VCC RL RL VIL or VIH fi 0.1 µF S Y0 1 Z Y1 2 switch S 1 VIH 2 VIL switch CL 50 Ω dB GND 001aac365 Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 14 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer VCC S Y0 1 Z Y1 2 switch Rgen VI G VO RL CL Vgen GND 001aac366 a. Test circuit logic (S) off input on VO off ∆VO 001aac478 b. Input and output pulse definitions Qinj = ∆VO × CL. ∆VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 22. Test circuit for measuring charge injection 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 15 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 12. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 23. Package outline SOT363 (SC-88) 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 16 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A1 bp c D E e HE Lp Q v w y 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 24. Package outline SOT457 (SC-74) 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 17 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 25. Package outline SOT886 (XSON6) 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 18 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 26. Package outline SOT891 (XSON6) 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 19 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G3157_2 20070918 Product data sheet - 74LVC1G3157_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name when appropriate. Added type number 74LVC1G3157GF (XSON6 package). Section 1 “General description”: Added: Schmitt trigger action at the enable input. • Section 2 “Features”: Added: Switch handling capability of 32 mA. • Section 8 “Limiting values”: Added: Derating factors of the applicable packages. • Section 10 “Static characteristics”: Changed: Maximum values of ON resistance (peak) parameters and graphics. Changed: Conditions for input leakage and supply current. Changed: Conditions for OFF-state and ON-state leakage current. • Section 11 “Dynamic characteristics”: Changed: Typical values of the charge injection. 74LVC1G3157_1 20050207 Product data sheet - 74LVC1G3157_2 Product data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 20 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74LVC1G3157_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 18 September 2007 21 of 22 74LVC1G3157 NXP Semiconductors 2-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuits . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 September 2007 Document identifier: 74LVC1G3157_2