INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4012B gates Dual 4-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4012B gates Dual 4-input NAND gate DESCRIPTION The HEF4012B provides the positive dual 4-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. Fig.1 Functional diagram. HEF4012BP(N): 14-lead DIL; plastic HEF4012BD(F): 14-lead DIL; ceramic (cerdip) (SOT27-1) (SOT73) HEF4012BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES see Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4012B gates Dual 4-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V TYPICAL EXTRAPOLATION FORMULA SYMBOL TYP MAX 70 135 ns 43 ns + (0,55 ns/pF) CL tPHL 25 50 ns 14 ns + (0,23 ns/pF) CL 20 35 ns 12 ns + (0,16 ns/pF) CL Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 15 VDD V Dynamic power 5 tTLH 70 140 ns 43 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 25 50 ns 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL TYPICAL FORMULA FOR P (µW) 1100 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 4400 fi + ∑ (foCL) × package (P) 15 12 900 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3