INTEGRATED CIRCUITS DATA SHEET TDA8004AT IC card interface Product specification Supersedes data of 2000 Feb 29 2004 May 10 Philips Semiconductors Product specification IC card interface TDA8004AT FEATURES APPLICATIONS • 3 or 5 V supply for the IC (GND and VDD) • IC card readers for banking • Step-up converter for VCC generation (separately powered with a 5 V ±10% supply, VDDP and PGND) • Electronic payment • 3 specific protected half duplex bidirectional buffered I/O lines (C4, C7 and C8) • Pay TV. • Identification • VCC regulation (5 or 3 V ±5% on 2 × 100 nF or 1 × 100 nF and 1 × 220 nF multilayer ceramic capacitors with low ESR, ICC < 65 mA at 4.5 V < VDDP < 6.5 V, current spikes of 40 nAs up to 20 MHz, with controlled rise and fall times, filtered overload detection approximately 90 mA) GENERAL DESCRIPTION The TDA8004AT is a complete low cost analog interface for asynchronous 3 or 5 V smart cards. It can be placed between the card and the microcontroller with very few external components to perform all supply protection and control functions. • Thermal and short-circuit protections on all card contacts • Automatic activation and deactivation sequences (initiated by software or by hardware in the event of a short-circuit, card take-off, overheating or supply drop-out) • Enhanced ESD protection on card side (>6 kV) • 26 MHz integrated crystal oscillator • Clock generation for the card up to 20 MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals) with synchronous frequency changes • Non-inverted control of RST via pin RSTIN • ISO 7816, GSM11.11 and EMV (payment systems) compatibility • Supply supervisor for spikes killing during power-on and power-off • One multiplexed status signal OFF. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8004AT SO28 2004 May 10 DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm 2 VERSION SOT136-1 Philips Semiconductors Product specification IC card interface TDA8004AT QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage VDDP step-up supply voltage IDD supply current 2.7 − 6.5 V 4.5 5 6.5 V inactive mode; VDD = 3.3 V; fXTAL = 10 MHz − − 1.2 mA active mode; VDD = 3.3 V; fXTAL = 10 MHz; no load − − 1.5 mA inactive mode; VDDP = 5 V; fXTAL = 10 MHz − − 0.1 mA active mode; VDDP = 5 V; fXTAL = 10 MHz; no load − − 18 mA DC ICC< 65 mA 4.75 − 5.25 V AC current spikes of 40 nAs 4.65 − 5.25 V DC ICC < 65 mA 2.85 − 3.15 V AC current spikes of 40 nAs 2.76 − 3.20 V Vi(ripple)(p-p) peak-to-peak ripple voltage on VCC from 20 kHz to 200 MHz − − 350 mV ICC − − 65 mA IDDP supply current step-up converter Card supply VCC output voltage including ripple 5 V card 3 V card output current VCC from 0 to 5 or to 3 V General fCLK card clock frequency 0 − 20 MHz tde deactivation cycle duration 60 80 100 µs Ptot continuous total power dissipation − − 0.56 W Tamb ambient temperature −25 − +85 °C 2004 May 10 Tamb = −25 to +85 °C 3 Philips Semiconductors Product specification IC card interface TDA8004AT BLOCK DIAGRAM VDDP VDD 100 nF 100 nF 21 6 100 nF handbook, full pagewidth S1 7 S2 5 4 PGND SUPPLY STEP-UP CONVERTER INTERNAL REFERENCE Vref INTERNAL OSCILLATOR 2.5 MHz 8 VUP 100 nF VOLTAGE SENSE ALARM OFF RSTIN CMDVCC 5V/3V EN1 CLKUP EN2 23 PVCC 20 VCC GENERATOR 19 17 VCC 14 CGND EN5 3 RST BUFFER 16 CLOCK BUFFER 15 RST SEQUENCER CLKDIV1 CLKDIV2 EN4 1 2 HORSEQ CLOCK CIRCUITRY 10 9 CLK PRES PRES CLK XTAL1 XTAL2 AUX1UC EN3 24 25 OSCILLATOR THERMAL PROTECTION 27 I/O TRANSCEIVER 13 I/O TRANSCEIVER 12 I/O TRANSCEIVER 11 AUX1 TDA8004AT AUX2UC I/OUC 28 26 22 18 GND n.c. FCE658 All capacitors are mandatory. Fig.1 Block diagram. 2004 May 10 4 AUX2 I/O 100 nF 100 nF Philips Semiconductors Product specification IC card interface TDA8004AT PINNING SYMBOL PIN I/O DESCRIPTION CLKDIV1 1 I control with CLKDIV2 for choosing CLK frequency CLKDIV2 2 I control with CLKDIV1 for choosing CLK frequency 5V/3V 3 I control signal for selecting VCC = 5 V (HIGH) or VCC = 3 V (LOW) PGND 4 supply S2 5 I/O VDDP 6 supply S1 7 I/O capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be connected between pins S1 and S2) VUP 8 O output of step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be connected to PGND) PRES 9 I card presence contact input (active LOW); if PRES or PRES is true, then the card is considered as present PRES 10 I card presence contact input (active HIGH); if PRES or PRES is true, then the card is considered as present I/O 11 I/O data line to and from card (C7) (internal 10 kΩ pull-up resistor connected to VCC) AUX2 12 I/O auxiliary line to and from card (C8) (internal 10 kΩ pull-up resistor connected to VCC) AUX1 13 I/O CGND 14 supply CLK 15 O clock to card (C3) RST 16 O card reset (C2) VCC 17 O supply for card (C1); decouple to CGND with 2 × 100 nF or 1 × 100nF and 1 × 220 nF capacitors with ESR < 100 mΩ (with 220 nF, the noise margin on VCC will be higher) n.c. 18 − not connected power ground for step-up converter capacitance connection for step-up converter (a 100 nF capacitor with ESR < 100 mΩ must be connected between pins S1 and S2) power supply voltage for step-up converter auxiliary line to and from card (C4) (internal 10 kΩ pull-up resistor connected to VCC) ground for card signals CMDVCC 19 I start activation sequence input from microcontroller (active LOW) RSTIN 20 I card reset input from microcontroller (active HIGH) VDD 21 supply supply voltage GND 22 supply OFF 23 O NMOS interrupt to microcontroller (active LOW) with 20 kΩ internal pull-up resistor connected to VDD (refer section “Fault detection”) ground XTAL1 24 I crystal connection or input for external clock XTAL2 25 O crystal connection (leave open circuit if an external clock source is used) I/OUC 26 I/O microcontroller data I/O line (internal 10 kΩ pull-up resistor connected to VDD) AUX1UC 27 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to VDD) AUX2UC 28 I/O auxiliary line to and from microcontroller (internal 10 kΩ pull-up resistor connected to VDD) 2004 May 10 5 Philips Semiconductors Product specification IC card interface TDA8004AT FUNCTIONAL DESCRIPTION Throughout this document, it is assumed that the reader is familiar with ISO7816 norm terminology. Power supply CLKDIV1 1 28 AUX2UC CLKDIV2 2 27 AUX1UC 5V/3V 3 26 I/OUC PGND 4 25 XTAL2 S2 5 24 XTAL1 VDDP 6 The supply pins for the IC are VDD and GND. VDD should be in the range from 2.7 to 6.5 V. All interface signals with the microcontroller are referenced to VDD; therefore be sure the supply voltage of the microcontroller is also at VDD. All card contacts remain inactive during powering up or powering down. The sequencer is not activated until VDD reaches Vth2 + Vhys(th2) (see Fig.3). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. For generating a 5 V ±5% VCC supply to the card, an integrated voltage doubler is incorporated. This step-up converter should be separately supplied by VDDP and PGND (from 4.5 to 6.5 V). Due to large transient currents, the 2 × 100 nF capacitors of the step-up converter should have an ESR of less than 100 mΩ, and be located as near as possible to the IC. 23 OFF 22 GND S1 7 TDA8004AT 21 VDD VUP 8 PRES 9 20 RSTIN PRES 10 19 CMDVCC The supply voltages VDD and VDDP may be applied to the IC in any time sequence. If a voltage between 7 and 9 V is available within the application, this voltage may be tied to pin VUP, thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor between pins S1 and S2 may be omitted. 18 n.c. I/O 11 AUX2 12 17 VCC AUX1 13 16 RST CGND 14 15 CLK FCE659 Voltage supervisor This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.3)). As long as VDD is less than Vth2 + Vhys(th2), the IC will remain inactive whatever the levels on the command lines. This also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys(th2). The system controller should not attempt to start an activation sequence during this time. Fig.2 Pin configuration. When VDD falls below Vth2, a deactivation sequence of the contacts is performed. 2004 May 10 6 Philips Semiconductors Product specification IC card interface TDA8004AT Vth2 + Vhys(th2) VDD Vth2 tW tW ALARM (internal signal) FCE660 Fig.3 Alarm as a function of VDD (tW = 10 ms). Clock circuitry In the other cases, it is guaranteed between 45% and 55% of the period. The clock signal (CLK) to the card is either derived from a clock signal input on pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence (see Fig.5). The frequency may be chosen at fXTAL, 1⁄2fXTAL, 1⁄4fXTAL or 1⁄8fXTAL via pins CLKDIV1 and CLKDIV2. The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. If the signal applied to XTAL1 is controlled by the microcontroller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. In the case of fXTAL, the duty factors are dependent on the signal at XTAL1. Table 1 In order to reach a 45% to 55% duty factor on pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period. CLKDIV1 CLKDIV2 0 0 1⁄ 8fXTAL 1 1⁄ 4fXTAL 1 1 1⁄ 2fXTAL 1 0 0 If a crystal is used with fXTAL, the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. 2004 May 10 Clock circuitry definition 7 CLK fXTAL Philips Semiconductors Product specification IC card interface TDA8004AT I/O circuitry Inactive state The three data lines I/O, AUX1 and AUX2 are identical. After power-on reset, the circuit enters the inactive state. A minimum number of circuits are active while waiting for the microcontroller to start a session. The Idle state is realized by data lines I/O and I/OUC being pulled HIGH via a 10 kΩ resistor (I/O to VCC and I/OUC to VDD). • All card contacts are inactive (approximately 200 Ω to GND) I/O is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC ≠ VDD. • I/OUC, AUX1UC and AUX2UC are high impedance (10 kΩ pull-up resistor connected to VDD) The first line on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which then becomes the slave. • Voltage generators are stopped • XTAL oscillator is running • Voltage supervisor is active. After a time delay td(edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus transmitting the logic 0 present on the master line. Activation sequence After power-on and, after the internal pulse width delay, the microcontroller may check the presence of the card with the signal OFF (OFF = HIGH while CMDVCC is HIGH means that the card is present; OFF = LOW while CMDVCC is HIGH means that no card is present). When the master line returns to logic 1, the P transistor on the slave line is turned on during the time delay td(edge) and then both lines return to their Idle states. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9VCC on a 80 pF load. At the end of the active pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the load current (see Fig.4). The following sequence then occurs (see Fig.5): The maximum frequency on these lines is 1 MHz. • CMDVCC is pulled LOW (t0) If the card is in the reader (which is the case if PRES or PRES is true), the microcontroller may start a card session by pulling CMDVCC LOW. • The voltage doubler is started (t1 ~ t0) FCE661 6 Vo (V) • VCC rises from 0 to 5 or 3V with a controlled slope (t2 = t1 + 1⁄23T) (I/O, AUX1 and AUX2 follow VCC with a slight delay); T is 64 times the period of the internal oscillator, approximately 25 µs 12 Io (mA) (1) • I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (2) • CLK is applied to the C3 contact (t4) 8 4 • RST is enabled (t5 = t1 + 7T). The clock may be applied to the card in the following way: Set RSTIN HIGH before setting CMDVCC LOW, and reset it LOW between t3 and t5; CLK will start at this moment. RST will remain LOW until t5, where RST is enabled to be the copy of RSTIN. After t5, RSTIN has no further action on CLK. This is to allow a precise count of CLK pulses before toggling RST. 4 2 0 20 0 40 t (ns) 0 60 If this feature is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3, and after t5, RSTIN may be set HIGH in order to get the Answer To Request (ATR) from the card. (1) Current. (2) Voltage. Fig.4 I/O, AUX1 and AUX2 output voltage and current as a function of time during a LOW-to-HIGH transition. 2004 May 10 8 Philips Semiconductors Product specification IC card interface TDA8004AT tact OSC_INT/64 CMDVCC VUP t1 t2 VCC ATR I/O high - Z t3 t4 t5 CLK RSTIN RST t0 FCE662 Fig.5 Activation sequence. Active state With all these layout precautions, noise should be at an acceptable level, and jitter on C3 should be less than 100 ps. Refer to Application Note AN97036 for specimen layouts. When the activation sequence is completed, the TDA8004AT will be in the active state. Data is exchanged between the card and the microcontroller via the I/O lines. The TDA8004AT is designed for cards without VPP (this is the voltage required to program or erase the internal non-volatile memory). Deactivation sequence When a session is completed, the microcontroller sets the CMDVCC line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Fig.6): Depending on the layout and on the application test conditions (for example with an additional 1 pF cross capacitance between C2/C3 and C2/C7) it is possible that C2 is polluted with high frequency noise from C3. In this case, it will be necessary to connect a 220 pF capacitor between C2 and CGND. • RST goes LOW → (t11 = t10) • CLK is stopped LOW → (t12 = t11 + 1⁄2T); where T is approximately 25 µs • I/O, AUX1 and AUX2 are output into high-impedance state → (t13 = t11 + T) (10 kΩ pull-up resistor connected to VCC) It is recommended to: 1. Keep track C3 as far as possible from other tracks 2. Have straight connection between CGND and C5 (the 2 capacitors on C1 should be connected to this ground track) • VCC falls to zero → (t14 = t11 + 1⁄23T); the deactivation sequence is completed when VCC reaches its inactive state 3. Avoid ground loops between CGND, PGND and GND • VUP falls to zero → (t15 = t11 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain pulled up to VDD via a 10 kΩ resistor. 4. Decouple VDDP and VDD separately; if the 2 supplies are the same in the application, then they should be connected in star on the main track. 2004 May 10 9 Philips Semiconductors Product specification IC card interface TDA8004AT tde OSC_INT/64 CMDVCC t10 t15 VUP t14 VCC t13 I/O high - Z t12 CLK RST t11 FCE663 Fig.6 Deactivation sequence. Fault detection When the system controller sets CMDVCC back to HIGH, it may sense OFF again in order to distinguish between a hardware problem or a card extraction. If a supply voltage drop on VDD is detected whilst the card is activated, then an emergency deactivation will be performed, but OFF remains HIGH. The following fault conditions are monitored by the circuit: • Short-circuit or high current on VCC • Removing card during transaction • VDD dropping • Overheating. Depending on the type of card presence switch within the connector (normally closed or normally open), and on the mechanical characteristics of the switch, a bouncing may occur on presence signals at card insertion or withdrawal. There are two different cases (see Fig.7) 1. CMDVCC HIGH: (outside a card session) then, OFF is LOW if the card is not in the reader, and HIGH if the card is in the reader. A supply voltage drop on VDD is detected by the supply supervisor which generates an internal power-on reset pulse, but does not act upon OFF. The card is not powered-up, so no short-circuit or overheating is detected. There is no debounce feature in the device, so the software has to take it into account; however, the detection of card take off during active phase, which initiates an automatic deactivation sequence is done on the first True/ False transition on PRES or PRES, and is memorized until the system controller sets CMDVCC HIGH. 2. CMDVCC LOW: (within a card session) then, OFF falls LOW if the card is extracted, or if a short-circuit has occurred on VCC, or if the temperature on the IC has become too high. As soon as the fault is detected, an emergency deactivation is automatically performed (see Fig.8). 2004 May 10 So, the software may take some time waiting for presence switches to be stabilized without causing any delay on the necessary fast and normalized deactivation sequence. 10 Philips Semiconductors Product specification IC card interface TDA8004AT PRES OFF CMDVCC VCC Deactivation caused by cards withdrawal Fig.7 Deactivation caused by short circuit FCE665 Behaviour of OFF, CMDVCC, PRES and VCC (see also application note AN97036 for software decision algorithm on OFF signal). tde OSC_INT/64 OFF t10 PRES t14 VCC t13 I/O high - Z t12 CLK RST t11 FCE664 Fig.8 Emergency deactivation sequence. VCC regulator The VCC buffer is able to deliver up to 65 mA continuously (at 5V if 5V/3V is HIGH or 3 V if 5V/3V is LOW). It has an internal overload detection at approximately 90 mA. This detection is internally filtered, allowing spurious current pulses up to 200 mA to be drawn by the card without causing a deactivation (the average current value must stay below 65 mA). For VCC accuracy reasons, a 100 nF capacitor with an ESR < 100 mΩ should be tied to CGND near pin 17, and a 100 nF (or better 220 nF) with same ESR should be tied to CGND near to the C1 contact. 2004 May 10 11 Philips Semiconductors Product specification IC card interface TDA8004AT LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD, VDDP supply voltage −0.3 +7 V Vn1 voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, CMDVCC and OFF −0.3 +7 V Vn2 voltage on card contact pins PRES, PRES, I/O, RST, AUX1, AUX2 and CLK −0.3 +7 V Vn3 voltage on pins VUP, S1 and S2 − +9 V Tstg IC storage temperature −55 +125 °C Ptot continuous total power dissipation − 0.56 W Tj junction temperature − 150 °C Ves1 electrostatic voltage on pins I/O, RST, VCC, AUX1, CLK, AUX2, PRES and PRES −6 +6 kV Ves2 electrostatic voltage on all other pins −2 +2 kV Tamb = −25 to +85 °C Note 1. All card contacts are protected against any short with any other card contact. HANDLING Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM; 1500 Ω; 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground. THERMAL RESISTANCE SYMBOL Rth(j-a) 2004 May 10 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 12 VALUE UNIT 70 K/W Philips Semiconductors Product specification IC card interface TDA8004AT CHARACTERISTICS VDD = 3.3 V; VDDP = 5 V; Tamb = 25 °C; all parameters remain within limits but are only statistically tested for the temperature range; fXTAL = 10 MHz; unless otherwise specified; all currents flowing into the IC are positive. When a parameter is specified as a function of VDD or VCC it means their actual value at the moment of measurement. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Temperature ambient temperature −25 − +85 °C VDD supply voltage 2.7 − 6.5 V VDDP supply voltage for the voltage doubler 4.5 5 6.5 V Vo(VUP) output voltage on pin VUP from step-up converter − 5.5 − V Vi(VUP) input voltage to be applied on VUP in order to block the step-up converter 7 − 9 V IDD supply current inactive mode − − 1.2 mA active mode; fCLK = fXTAL; CL = 30 pF − − 1.5 mA inactive mode − − 0.1 mA ICC = 0 − − 18 mA ICC = 65 mA Tamb Supplies IDDP supply current step-up converter active mode; ICC = 0; fCLK = fXTAL; CL = 30 pF − − 150 mA Vth2 threshold voltage on VDD (falling) 2.2 − 2.4 V Vhys(th2) hysteresis on Vth2 50 − 150 mV tW width of the internal ALARM pulse 6 − 20 ms inactive mode − 0.1 − +0.1 V inactive mode; ICC = 1 mA − 0.1 − +0.4 V 5 V card 4.75 − 5.25 V 3 V card 2.85 − 3.15 V 5 V card 4.65 − 5.25 V 3 V card 2.76 − 3.15 V 5 V card 4.65 − 5.25 V 3 V card 2.76 − 3.20 V − − 350 mV Card supply voltage; note 1 VCC output voltage including ripple active mode; ICC < 65 mA DC active mode; single current pulse of −100 mA; 2 µs active mode; current pulses of 40 nAs with ICC < 200 mA; t < 400 ns Vi(ripple)(p-p) 2004 May 10 peak-to-peak ripple voltage on VCC from 20 kHz to 200 MHz 13 Philips Semiconductors Product specification IC card interface SYMBOL TDA8004AT PARAMETER ICC output current SR slew rate CONDITIONS MIN. TYP. MAX. UNIT from 0 to 5 or 3 V − − 65 mA VCC short-circuit to ground − − 120 mA up 0.09 0.18 0.27 V/µs down 0.09 0.21 0.27 V/µs depending on specification − of crystal or resonator used − 15 pF 2 − 26 MHz Crystal connections (pins XTAL1 and XTAL2) Cext external capacitors on pins XTAL1 and XTAL2 fi(XTAL) crystal input frequency VIH(XTAL) HIGH-level input voltage on XTAL1 0.8VDD − VDD + 0.2 V VIL(XTAL) LOW-level input voltage on XTAL1 −0.3 − +0.2VDD V Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC) GENERAL td(edge) delay between falling edge on pins I/OUC and I/O (or I/O and I/OUC) and width of active pull-up pulse − 200 − ns fI/O(max) maximum frequency on data lines − − 1 MHz Ci input capacitance on data lines − − 10 pF DATA LINES; PINS I/O, AUX1 AND AUX2 (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VCC) HIGH-level output voltage on data lines no DC load 0.9VCC − VCC + 0.1 V IOH = −40 µA 0.75VCC − VCC + 0.1 V VOL LOW-level output voltage on data lines I = 1 mA − − 300 VIH HIGH-level input voltage on data lines 1.8 − VCC + 0.3 V VIL LOW-level input voltage on data lines −0.3 − +0.8 V Vinactive voltage on data lines outside a session no load − − 0.1 V II/O = 1 mA − − 0.3 V Iedge current from data lines when active pull-up active VOH = 0.9VCC ; Co = 80 pF −1 − − mA ILIH input leakage current HIGH on data lines VIH = VCC − − 10 µA IIL LOW-level input current on data lines VIL = 0 V − − 600 µA tt(DI) input transition times on data lines from VIL max to VIH min − − 1 µs tt(DO) output transition times on data lines Co = 80 pF, no DC load; 10% to 90% from 0 to VCC (see Fig.9) − − 0.1 µs VOH mV DATA LINES; PINS I/OUC, AUX1UC AND AUX2UC (WITH 10 KΩ PULL-UP RESISTOR CONNECTED TO VDD) VOH 2004 May 10 HIGH-level output voltage on data lines no DC load 0.9VDD − VDD + 0.2 V IOH = −40 µA 0.75VDD − VDD + 0.2 V 14 Philips Semiconductors Product specification IC card interface SYMBOL PARAMETER TDA8004AT CONDITIONS MIN. TYP. MAX. UNIT − − 300 HIGH-level input voltage on data lines 0.7VDD − VDD + 0.3 V VIL LOW-level input voltage on data lines 0 − 0.3VDD V ILIH input leakage current HIGH on data lines VIH = VDD − − 10 µA IIL LOW-level input on data lines VIL = 0 V Rpu(int) internal pull-up resistance between data lines and VDD tt(DI) input transition times on data lines tt(DO) output transition times on data lines VOL LOW-level output voltage on data lines VIH I = 1 mA mV − − 600 µA 9 11 13 kΩ from VIL max to VIH min − − 1 µs Co = 30 pF; 10% to 90% from 0 to VDD (see Fig.9) − − 0.1 µs 2.2 − 3.2 MHz no load 0 − 0.1 V Io = 1 mA Internal oscillator fosc(int) frequency of internal oscillator Reset output to the card (pin RST) Vo(inactive) output voltage in inactive mode 0 − 0.3 V td(RSTIN-RST) delay between pins RSTIN and RST RST enabled − − 2 µs IOL = 200 µA 0 − 0.3 V VOL LOW-level output voltage VOH HIGH-level output voltage IOH = −200 µA 0.9VCC − VCC V tr, tf rise and fall times Co = 250 pF − − 0.1 µs Clock output to the card (pin CLK) Vo(inactive) output voltage in inactive mode no load 0 − 0.1 V Io = 1 mA 0 − 0.3 V VOL LOW-level output voltage IOL = 200 µA 0 − 0.3 V IOH = −200 µA 0.9VCC − VCC V 0 − 20 MHz − − 8 ns VOH HIGH-level output voltage fCLK card clock frequency tr, tf rise and fall times CL = 35 pF; note 2 δ duty factor (except for fXTAL) CL = 35 pF; note 2 45 − 55 % SR slew rate (rise and fall) CL = 35 pF 0.2 − − V/ns Logic inputs (pins CLKDIV, CLKDIV2,PRES, PRES, CMDVCC, RSTIN and 5V/3V); note 3 VIL LOW-level input voltage − − 0.3VDD V VIH HIGH-level input voltage 0.7VDD − − V ILIL input leakage current LOW 0 < VIL < VDD − − 5 µA ILIH input leakage current HIGH 0 < VIH < VDD − − 5 µA − 0.4 V OFF output (pin OFF is an open-drain with an internal 20 kΩ pull-up resistor to VDD) VOL 2004 May 10 LOW-level output voltage IOL = 2 mA 15 − Philips Semiconductors Product specification IC card interface SYMBOL VOH TDA8004AT PARAMETER CONDITIONS MIN. IOH = −15 µA HIGH-level output voltage TYP. MAX. UNIT 0.75VDD − − V Protections Tsd shut-down temperature − 135 − °C ICC(sd) shut-down current at VCC − − 110 mA − 180 220 µs Timing tact activation sequence duration see Fig.5 tde deactivation sequence duration see Fig.6 60 80 100 µs t3 start of the window for sending CLK to the card see Fig.5 − − 130 µs t5 end of the window for sending CLK to the card see Fig.5 140 − − µs Notes 1. To meet these specifications VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR with values of either 100 nF or one 100 nF and one 220 nF. t1 2. The transition times and duty factor definitions are shown in Fig.9; δ = -------------t1 + t2 3. PRES and CMDCC are active LOW; RSTIN and PRES are active HIGH; for CLKDIV1 and CLKDIV2 see Table 1. tr tf 90% 90% VOH (VOH + VOL)/2 10% 10% t1 VOL t2 Fig.9 Definition of output transition times. 2004 May 10 16 FCE666 Philips Semiconductors Product specification IC card interface TDA8004AT APPLICATION DIAGRAM VDD for the TDA8004 must be the same as controller supply voltage, CLKDIV1, CLKDIV2, RSTIN, PRES, PRES, AUXUC, I/OUC, AUX2UC, RFU1, CMDVCC, OFF should be referenced to VDD and also XTAL1 if driven by external clock. More application information on application report AN97036 CLKDIV1 CLKDIV2 5V/3V 100 nF 10 µF +5 V GNDP S2 VDDP 100 nF These capacitors must be placed near the IC and have low ESR (less than 1 cm). S1 VUP 100 nF PRES PRES I/O AUX2 AUX1 100 kΩ +3.3 V CGND 1 28 2 27 3 26 4 26 5 24 6 23 7 22 TDA8004AT 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AUX2UC AUX1UC I/OUC XTAL2 XTAL1 33 pF 3.3 V POWERED MICROCONTROLLER OFF GND VDD RSTIN 100 nF +3.3 V CMDVCC n.c. +3.3 V VCC RST CLK 100 nF Straight and short connections between CGND, C5 and capacitors GND (no loop). One 100 nF with low ESR near pin 17. CARD READ (NORMALLY CLOSED TYPE) 200 nF C5 C1 C6 C2 C7 C3 C8 C4 One 100 nF or 220 nF with low ESR near C1 contact (less than 1 cm). C3 should be routed far from C2, C7, C4 and C8 and, better, surrounded with ground tracks. K1 K2 fce667 Fig.10 Application diagram. 2004 May 10 17 Philips Semiconductors Product specification IC card interface TDA8004AT PACKAGE OUTLINE SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013 2004 May 10 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 18 Philips Semiconductors Product specification IC card interface TDA8004AT To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON-T and SSOP-T packages – for packages with a thickness ≥ 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 May 10 19 Philips Semiconductors Product specification IC card interface TDA8004AT Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 May 10 20 Philips Semiconductors Product specification IC card interface TDA8004AT DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 May 10 21 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R63/02/pp22 Date of release: 2004 May 10 Document order number: 9397 750 13142