INTEGRATED CIRCUITS DATA SHEET TDA9853H I2C-bus controlled economic BTSC stereo decoder and audio processor Product specification File under Integrated Circuits, IC02 2000 Dec 11 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H FEATURES • Voltage Controlled Amplifier (VCA) noise reduction circuit • Stereo or mono selectable at the AF outputs • Stereo pilot PLL circuit with ceramic resonator • Automatic pilot cancellation • I2C-bus transceiver. GENERAL DESCRIPTION Audio processor The TDA9853H is a bipolar-integrated BTSC stereo decoder and audio processor for application in TV sets, VCRs and multimedia PCs. • Selector for internal and external signals (line in) • Automatic Volume Level (AVL) control (control range +6 to −15 dB) • Volume control (control range +12 to −63 dB) • Mute control via I2C-bus • 4 fixed tone settings. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION TDA9853H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 × 14 × 2.2 mm 2000 Dec 11 2 VERSION SOT205-1 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 7.8 8 9 V ICC supply current 25 33 45 mA Vo(rms) output voltage (RMS value) composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); fmod = 300 Hz − 500 − mV αcsL,R stereo channel separation L and R 14% modulation; fL = 300 Hz; fR = 3 kHz 15 20 − dB THDL,R total harmonic distortion L and R 100% modulation L or R; fmod = 1 kHz − 0.2 1 % S/N signal-to-noise ratio at line out mono via I2C-bus; referenced to 500 mV and at AF output output signal; volume 0 dB 50 60 − dB 73 − dBA 2 − − V CCIR 468-2 weighted; quasi peak DIN noise weighting filter (RMS value) − VI, O(rms) signal handling (RMS value) AVL AVL control range −15 − +6 dB Gc volume control range −63 − +12 dB Llinear linear tone control − 0 − dB Lbass(max) tone control with maximum bass referenced to linear position; fmod = 20 Hz 10 12 − dB Lbass(min) tone control with minimum bass referenced to linear position; fmod = 20 Hz 3.5 5 − dB Ltreble(max) tone control with maximum treble referenced to linear position; fmod = 20 kHz 6 8 − dB Ltreble(min) referenced to linear position; fmod = 20 kHz − −1.5 − dB tone control with minimum treble 2000 Dec 11 THD < 0.5% 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... C4 composite baseband input C1 COMP 4 C5 C6 CER CMO CSS LOR LIR CAV VAR VIR TC1R TC2R BCR 43 5 6 25 26 29 23 24 21 Q1 R1 C2 CP2 CP1 2 3 CPH 42 DEMATRIX AND MODE SELECT L+R STEREO DECODER C7 C8 AUTOMATIC VOLUME AND LEVEL CONTROL INPUT SELECT L−R 4 FDI 35 C10 C9 C11 20 VOLUME RIGHT CONTROL TONE RIGHT CONTROL VOLUME LEFT CONTROL TONE LEFT CONTROL C12 19 18 OUTR TDA9853H R2 FDO 33 R3 DETECTOR AND VOLTAGE CONTROLLED AMPLIFIER 32 31 30 BPU CW TW FILTER AND REFERENCE SUPPLY 41 28 36 27 9 VCAP AGND Vref 7 8 LOL LIL I2C-BUS TRANSCEIVER 40 39 38 37 RFR 16 11 10 13 VAL VIL TC1L TC2L BCL 14 Philips Semiconductors C3 I2C-bus controlled economic BTSC stereo decoder and audio processor BLOCK DIAGRAM handbook, full pagewidth 2000 Dec 11 External Input Right (EIR) OUTL 15 MAD C23 C22 C21 C20 C19 C18 C17 R4 VCC External Input Left (EIL) SDA DGND C16 C15 C14 C13 MHB789 Product specification TDA9853H Fig.1 Block diagram. SCL Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H Component list Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1. COMPONENT VALUE TYPE C1 2.2 µF electrolytic C2 220 nF foil REMARK 63 V C3 2.2 µF electrolytic C4 220 nF foil C5 2.2 µF electrolytic 63 V C6 2.2 µF electrolytic 63 V 63 V C7 2.2 µF electrolytic 63 V C8 4.7 µF electrolytic 63 V ±10% C9 2.2 µF electrolytic 63 V C10 3.3 nF foil C11 150 pF foil C12 56 nF foil C13 56 nF foil C14 150 pF foil C15 3.3 nF foil C16 2.2 µF electrolytic 63 V C17 2.2 µF electrolytic 63 V C18 100 µF electrolytic 16 V C19 100 µF electrolytic 16 V C20 10 µF electrolytic 63 V C21 1 µF electrolytic 63 V C22 4.7 nF foil C23 22 nF foil R1 3.3 kΩ R2 15 kΩ R3 1.3 kΩ R4 100 kΩ Q1 2000 Dec 11 5 CSB503F58 radial leads CSB503JF958 alternative as SMD Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor PINNING TDA9853H SYMBOL PIN SYMBOL PIN DESCRIPTION DESCRIPTION VIR 24 volume control input; right channel n.c. 1 not connected LOR 25 line output; right channel CP2 2 connector 2 for pilot detector capacitor LIR 26 line input; right channel CP1 3 connector 1 for pilot detector capacitor Vref 27 reference voltage (0.5VCC) COMP 4 composite input signal VCAP 28 CMO 5 capacitor for DC-decoupling mono capacitor for electronic filtering of supply CSS 6 capacitor for DC-decoupling stereo CAV 29 capacitor for AVL RFR 7 resistor for filter reference TW 30 capacitor timing LIL 8 line input; left channel CW 31 LOL 9 line output; left channel capacitor for VCA and band-pass filter lower corner frequency VIL 10 volume control input; left channel BPU 32 VAL 11 AVL output; left channel band-pass filter upper corner frequency n.c. 12 not connected FDO 33 fixed de-emphasis output TC1L 13 treble capacitor 1; left channel TC2L 14 treble capacitor 2; left channel BCL 15 bass capacitor; left channel OUTL 16 left channel output n.c. 17 not connected OUTR 18 right channel output BCR 19 bass capacitor; right channel TC2R 20 treble capacitor 2; right channel TC1R 21 treble capacitor 1; right channel n.c. 22 not connected VAR 23 AVL output; right channel 2000 Dec 11 6 n.c. 34 not connected FDI 35 fixed de-emphasis input AGND 36 analog ground DGND 37 digital ground SDA 38 serial data input/output MAD 39 programmable address bit (module address) SCL 40 serial clock input VCC 41 supply voltage CPH 42 capacitor for phase detector CER 43 ceramic resonator n.c. 44 not connected Philips Semiconductors Product specification 34 n.c. 35 FDI 36 AGND TDA9853H 37 DGND 38 SDA 39 MAD 40 SCL 41 VCC 42 CPH handbook, full pagewidth 43 CER 44 n.c. I2C-bus controlled economic BTSC stereo decoder and audio processor n.c. 1 33 FDO CP2 2 32 BPU CP1 3 31 CW COMP 4 30 TW CMO 5 29 CAV CSS 6 RFR 7 27 Vref LIL 8 26 LIR LOL 9 25 LOR TDA9853H 28 VCAP n.c. 22 TC1R 21 TC2R 20 BCR 19 OUTR 18 n.c. 17 OUTL 16 BCL 15 23 VAR TC2L 14 VAL 11 TC1L 13 24 VIR n.c. 12 VIL 10 MHB790 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Automatic volume level control Stereo decoder The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from an input voltage range between 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and because of changes in the programme material; this function can be switched off. To avoid audible plops during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay times can be changed via the I2C-bus. The composite signal is fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is applied to the Volume Controlled Amplifier (VCA) circuit. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. Mode selection The L − R signal is fed via the internal VCA circuit to the dematrix/switching circuit. Mode selection is achieved via the I2C-bus (see Table 9). Integrated filters The filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. The filter frequencies are controlled by the filter reference circuit via the external resistor R4. The dematrix outputs can be muted via the I2C-bus (see Table 14). 2000 Dec 11 7 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H Audio processor TREBLE FUNCTION SELECTOR Two external capacitors C15 = 3.3 nF and C14 = 150 pF for each channel in combination with a linear operational amplifier and internal resistors provide a treble range of +8 dB for high treble and −1.5 dB for low treble. The selector enables the selection of either the internal line output signals LOR and LOL (dematrix output) or the external line input signals LIR and LIL (see Table 16). The input signal capability of the line inputs (LIR/LIL) is 2 V (RMS). The output of the selector is DC-coupled to the automatic volume level control circuit. MUTE The mute function can be activated independently with the last step of volume control at the left or right output. By setting the general mute bit GMU the audio outputs OUTL and OUTR are muted. VOLUME The volume control range is from +12 dB to −63 dB in steps of 1 dB and ends with a mute step (see Table 8). Balance control is achieved by the independent volume control of each channel. BASS FUNCTION A single external 56 nF capacitor for each channel in combination with a linear operational amplifier and internal resistors provides a bass range of +12 dB for high bass and +5 dB for low bass. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 9.5 V VCC ≤ 9 V −0.3 +VCC V VCC > 9 V −0.3 +9 V 0 VCC V ambient temperature −20 +70 °C Tstg storage temperature −65 +150 °C Ves electrostatic handling voltage note 1 −200 +200 V note 2 −2000 +2000 V VCC supply voltage VSDA, VSCL voltage at pins SDA and SCL referenced to GND Vn voltage of all other pins to GND Tamb Notes 1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually 0.75 µH + 10 Ω). 2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Dec 11 PARAMETER CONDITIONS thermal resistance from junction to ambient 8 in free air VALUE UNIT 70 K/W Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H CHARACTERISTICS All voltages are measured relative to GND; VCC = 8 V; Rs = 600 Ω; AC-coupled; RL = 10 kΩ; CL = 2.5 nF; fmod = 1 kHz mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); pilot 50 mV (RMS); Gv = 0 dB; linear tone control; AVL off; Tamb = 25 °C; see Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCC supply voltage 7.8 8 9 V ICC supply current 25 33 45 mA Vref internal reference voltage at pin Vref 0.45VCC 0.5VCC Vi(max)(rms) maximum input voltage (RMS value) 2 − − V Zi input impedance 20 25 32 kΩ 9 − − dB 0.55VCC V Input stage Stereo decoder HR headroom for L + R, L and R Vpil(rms) nominal stereo pilot voltage (RMS value) − 50 − mV Vth(on)(rms) pilot threshold voltage, stereo on (RMS value) − − 35 mV Vth(off)(rms) pilot threshold voltage, stereo off (RMS value) 15 − − mV hys hysteresis − 2.5 − dB Vo(rms) output voltage (RMS value) 100% modulation L + R; fmod = 300 Hz − 500 − mV αcs(L,R) stereo channel separation L and R 14% modulation; fL = 300 Hz; fR = 3 kHz 15 20 − dB THDL,R total harmonic distortion L and R 100% modulation L or R; fmod = 1 kHz − 0.2 1 % S/N signal-to-noise ratio at line output and AF output mono via I2C-bus; referenced to 500 mV output signal CCIR 468-2 weighted; quasi peak 50 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA 63 − − dB αmute fmod = 300 Hz; THD < 15% mute attenuation at LOL, LOR, 100% modulation L + R; VAL and VAR fmod = 300 Hz; mute via bit E6 Stereo decoder, oscillator (VCXO); note 1 fo nominal VCXO output frequency (32fH) with nominal ceramic resonator − 503.5 − kHz ∆ffr spread of free-running frequency with nominal ceramic resonator 500 − 507 kHz ∆fcr capture range frequency nominal pilot ±190 ±265 − Hz 2000 Dec 11 9 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor SYMBOL PARAMETER TDA9853H CONDITIONS MIN. TYP. MAX. UNIT Audio control part; input pins VIL and VIR to pins OUTL and OUTR VO DC output voltage 0.45VCC 0.5VCC 0.55VCC V Zi volume input impedance 25 30 38 kΩ Zo output impedance − 80 120 Ω RL output load resistance 5 − − kΩ CL output load capacitance 0 − 2.5 nF Vi(max)(rms) maximum input voltage (RMS value) THD < 0.5% tbf 2 − V − 0.05 − % Gv = 10 dB − 110 220 µV Gv = 0 dB − 33 50 µV mute position − 10 − µV maximum boost − 12 − dB maximum attenuation − 63 − dB − 1 − dB − − 0.5 dB THD total harmonic distortion 1 V (RMS) input voltage Vno noise output voltage CCIR 468-2 weighted; quasi peak Gc volume control range Gstep step resolution step error between adjoining step ∆Ga attenuator set error Gv = +12 to −15 dB and Gv = −16 to −63 dB; note 2 Gv = +12 to −50 dB − − 2 dB Gv = −51 to −63 dB − − 3 dB Gv = +12 to −50 dB − − 2 dB ∆GL gain tracking error αm mute attenuation 80 − − dB VDC(OS) DC step offset between any adjacent step Gv = +12 to 0 dB − 0.2 10 mV Gv = 0 to −63 dB − − 5 mV DC step offset between any step to mute Gv = +12 to 0 dB − 2 15 mV Gv = −1 to −63 dB − 1 10 mV Tone control part Llinear linear tone control − 0 − dB Lbass(max) tone control with maximum bass referenced to linear position; fmod = 20 Hz 10 12 − dB Lbass(min) tone control with minimum bass referenced to linear position; fmod = 20 Hz 3.5 5 − dB Ltreble(max) tone control with maximum treble referenced to linear position; fmod = 20 kHz 6 8 − dB Ltreble(min) tone control with minimum treble referenced to linear position; fmod = 20 kHz − −1.5 − dB 2000 Dec 11 10 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor SYMBOL PARAMETER TDA9853H CONDITIONS MIN. TYP. MAX. UNIT VCA Is nominal timing current for nominal release rate of VCA detector Is can be measured at pin TW via current meter connected to 0.5VCC + 1 V 6.5 8 9.5 µA Relrate nominal detector release rate nominal timing current and external capacitor values − 125 − dB/s maximum boost; note 3 5 6 7 dB maximum attenuation; note 3 14 15 16 dB − 1.5 − dB maximum boost; note 3 − 0.1 − V maximum attenuation; note 3 − 1.125 − V 160 200 250 mV Automatic volume level control Gv voltage gain Gstep equivalent step width between the input stages (soft switching system) Vi(rms) input voltage (RMS value) Vo(AVL)(rms) output voltage in AVL operation (RMS value) Voffset(DC) DC offset voltage between different gain steps voltage at pin CAV − 6 to 5.83 V or 5.83 to 5.61 V or 5.61 to 4.83 V or 4.83 to 2.1 V; note 4 − 20 mV Ratt discharge resistors for attack time constant AT1 = 0; AT2 = 0; note 5 340 420 520 Ω AT1 = 1; AT2 = 0; note 5 590 730 910 Ω AT1 = 0; AT2 = 1; note 5 0.96 1.2 1.5 kΩ AT1 = 1; AT2 = 1; note 5 1.7 2.1 2.6 kΩ Idec charge current for decay time 2 2.4 µA − 30 − µA 16 20 25 kΩ Vi = 1 V; fi = 1 kHz 70 76 − dB Vi = 1 V; fi = 12.5 kHz 70 76 − dB THD < 0.5% − 2 − V − 0 − dB − 500 − mV − dB 120 Ω normal mode; CCD = 0; note 6 1.6 Power-on speed-up; CCD = 1; note 6 Selector internal and external Zi input impedance αs input isolation of one selected source to the other input Vi(max)(rms) maximum input voltage (RMS value) Gv voltage gain, selector Line output; pins LOL and LOR Vo(rms) nominal output voltage (RMS value) HRo output headroom 9 − Zo output impedance − 80 VO DC output voltage 0.45VCC 0.5VCC RL output load resistance 5 − − kΩ CL output load capacitance − − 2.5 nF 2000 Dec 11 100% modulation 11 0.55VCC V Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor SYMBOL PARAMETER TDA9853H CONDITIONS MIN. TYP. MAX. UNIT Monitor output; pins VAL and VAR VO DC output voltage − 0.5VCC − V RL output load resistance 5 − − kΩ CL output load capacitance − − 2.5 nF − VCAP − 0.7 − V increasing supply voltage − − 2.5 V decreasing supply voltage − tbf − V increasing supply voltage − tbf − V V with 100 Ω in series Muting at power supply voltage drop for OUTR and OUTL ∆VCC supply voltage drop for mute active Power-on reset; note 7 VPOR(start) VPOR(end) Digital part start of reset voltage end of reset voltage (I2C-bus pins); note 8 VIH HIGH-level input voltage 3 − VCC(9) VIL LOW-level input voltage −0.3 − +1.5 V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current −10 − +10 µA VOL LOW-level output voltage − − 0.4 V IIL = 3 mA Notes 1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change of the resonator supplier is possible, but the resonator specification must be close to the specified ones. 2. 1.5 dB step error between −15 and −16 dB. 3. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off. 4. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB. 5. Attack time constant = CCAV × Ratt with CCAV = C8 (see Fig.1). –G1 6. –G2 ---------- --------20 20 – 10 C CAV × 0.76 V 10 Decay time = --------------------------------------------------------------------------------I dec a) Example: CCAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s. 7. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position. 8. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification. Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). 9. Maximum 9 V if VCC > 9 V. 2000 Dec 11 12 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H MHB791 12 handbook, full pagewidth gain (dB) (1) 8 (2) (3) 4 0 (4) −4 10 (1) (2) (3) (4) 102 103 Maximum bass. Maximum treble. Minimum bass. Minimum treble. Fig.3 Tone control. 2000 Dec 11 13 104 f (Hz) 105 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S SLAVE ADDRESS Table 1 R/W A DATA P Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION S START condition; generated by the master Standard SLAVE ADDRESS (MAD) 1011011; pin MAD not connected Pin programmable SLAVE ADDRESS 1011010; pin MAD connected to ground R/W logic 1 (read); generated by the master A acknowledge; generated by the slave DATA slave transmits an 8-bit data word AN acknowledge not; generated by the master P STOP condition; generated by the master Table 2 AN Definition of the transmitted bytes after read condition MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Y Y Y Y Y Y PONR STP Table 3 Bit functions of Table 2 BIT FUNCTION STP stereo pilot identification (stereo received = 1) PONR Power-on reset; if PONR = 1, then Power-on reset is detected Y indefinite I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS R/W A SUBADDRESS A Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION S START condition Standard SLAVE ADDRESS 101 101 1; pin MAD not connected Pin programmable SLAVE ADDRESS 101 101 0; pin MAD connected to ground R/W logic 0 (write) A acknowledge; generated by the slave SUBADDRESS (SAD) see Table 5 DATA see Table 6 P STOP condition 2000 Dec 11 14 DATA A P Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress and auto-increment of subaddress in accordance with the order of Table 5 is performed. Table 5 Subaddress definition (second byte after slave address) MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1(1) D0(1) Volume right 0 0 0 0 0 0 0 0 Volume left 0 0 0 0 0 0 0 1 Control 1 0 0 0 0 0 0 1 0 Control 2 0 0 0 0 0 0 1 1 Note 1. Significant subaddress bits. Table 6 Data definition (third byte after slave address) MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Volume right 0 B6 B5 B4 B3 B2 B1 B0 Volume left 0 C6 C5 C4 C3 C2 C1 C0 Control 1 0 E6 E5 E4 E3 E2 E1 E0 Control 2 0 0 0 F4 F3 F2 F1 F0 Table 7 Bit functions of Table 6 BITS SYMBOL FUNCTION B0 to B6 VR0 to VR6 volume control right C0 to C6 VL0 to VL6 volume control left E0 STEREO mode selection for line out E1 GMU mute control for OUTL and OUTR E2 AVLON AVL on/off E3 CCD increased AVL decay current on/off E4 and E5 AT1 and AT2 attack time at AVL E6 LMU line out mute on/off F0 and F1 TONE selection between four fixed tone controls F2 MODE selection between intern and extern F3 MONO forced mono on/off at OUTL and OUTR F4 LITO linear tone control on/off 2000 Dec 11 15 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor Table 8 TDA9853H Volume setting DATA FUNCTION Gv (dB) V6 V5 V4 V3 V2 V1 V0 12 1 1 1 1 0 1 1 11 1 1 1 1 0 1 0 10 1 1 1 1 0 0 1 9 1 1 1 1 0 0 0 8 1 1 1 0 1 1 1 7 1 1 1 0 1 1 0 6 1 1 1 0 1 0 1 5 1 1 1 0 1 0 0 4 1 1 1 0 0 1 1 3 1 1 1 0 0 1 0 2 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 −1 1 1 0 1 1 1 0 −2 1 1 0 1 1 0 1 −3 1 1 0 1 1 0 0 −4 1 1 0 1 0 1 1 −5 1 1 0 1 0 1 0 −6 1 1 0 1 0 0 1 −7 1 1 0 1 0 0 0 −8 1 1 0 0 1 1 1 −9 1 1 0 0 1 1 0 −10 1 1 0 0 1 0 1 −11 1 1 0 0 1 0 0 −12 1 1 0 0 0 1 1 −13 1 1 0 0 0 1 0 −14 1 1 0 0 0 0 1 −15 1 1 0 0 0 0 0 −16 1 0 1 1 1 1 1 −17 1 0 1 1 1 1 0 −18 1 0 1 1 1 0 1 −19 1 0 1 1 1 0 0 −20 1 0 1 1 0 1 1 −21 1 0 1 1 0 1 0 −22 1 0 1 1 0 0 1 −23 1 0 1 1 0 0 0 −24 1 0 1 0 1 1 1 −25 1 0 1 0 1 1 0 2000 Dec 11 16 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H DATA FUNCTION Gv (dB) V6 V5 V4 V3 V2 V1 V0 −26 1 0 1 0 1 0 1 −27 1 0 1 0 1 0 0 −28 1 0 1 0 0 1 1 −29 1 0 1 0 0 1 0 −30 1 0 1 0 0 0 1 −31 1 0 1 0 0 0 0 −32 1 0 0 1 1 1 1 −33 1 0 0 1 1 1 0 −34 1 0 0 1 1 0 1 −35 1 0 0 1 1 0 0 −36 1 0 0 1 0 1 1 −37 1 0 0 1 0 1 0 −38 1 0 0 1 0 0 1 −39 1 0 0 1 0 0 0 −40 1 0 0 0 1 1 1 −41 1 0 0 0 1 1 0 −42 1 0 0 0 1 0 1 −43 1 0 0 0 1 0 0 −44 1 0 0 0 0 1 1 −45 1 0 0 0 0 1 0 −46 1 0 0 0 0 0 1 −47 1 0 0 0 0 0 0 −48 0 1 1 1 1 1 1 −49 0 1 1 1 1 1 0 −50 0 1 1 1 1 0 1 −51 0 1 1 1 1 0 0 −52 0 1 1 1 0 1 1 −53 0 1 1 1 0 1 0 −54 0 1 1 1 0 0 1 −55 0 1 1 1 0 0 0 −56 0 1 1 0 1 1 1 −57 0 1 1 0 1 1 0 −58 0 1 1 0 1 0 1 −59 0 1 1 0 1 0 0 −60 0 1 1 0 0 1 1 −61 0 1 1 0 0 1 0 −62 0 1 1 0 0 0 1 −63 0 1 1 0 0 0 0 Mute 0 1 0 1 1 1 1 2000 Dec 11 17 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor Table 9 Mode setting FUNCTION MODE LOL Left LOR right TDA9853H Table 14 Line out mute setting READABLE BIT SETTING BIT D0/STP E0/STEREO logic 1 (stereo received) 1 Mono mono logic 1 (stereo received) 0 Mono mono logic 0 (no stereo received) 1 Mono mono logic 0 (no stereo received) 0 FUNCTION DATA MUTE LINE OUTPUT E6 Line output mute 1 Line output active 0 Table 15 Tone setting FUNCTION TONE DATA F1 F0 Maximum bass and maximum treble 1 1 1 0 DATA Maximum bass and minimum treble 0 1 E1 Minimum bass and maximum treble 0 1 Minimum bass and minimum treble 0 Forced mute at OUTR and OUTL No forced mute at OUTR and OUTL 0 Table 10 Mute setting FUNCTION MUTE CONTROL FOR OUTR AND OUTL Table 16 Selector setting Table 11 AVLON bit setting FUNCTION DATA MODE INTERNAL/EXTERNAL F2 FUNCTION DATA AVL E2 External left and right 1 Automatic volume control on 1 Internal left and right 0 Automatic volume control off 0 Table 17 Mono setting Table 12 CCD bit setting FUNCTION DATA AVL CURRENT E3 Increased load current 1 Load current for normal AVL decay time 0 FUNCTION DATA MONO AT OUTL AND OUTR F3 Forced mono 1 No forced mono 0 Table 18 Linear setting Table 13 AVL attack time; see Chapter “Characteristics” note 5 FUNCTION DATA Ratt (Ω) E5 E4 420 0 0 730 0 1 1200 1 0 2100 1 1 2000 Dec 11 18 FUNCTION DATA MODE TONE F4 Linear 1 Tone 0 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H INTERNAL PIN CONFIGURATIONS + 2 3 + 8.5 kΩ 12 kΩ 3.5 kΩ MHB793 MHB792 Fig.4 Pin 2: CP2. Fig.5 Pin 3: CP1. 4 + 5, 6 25 kΩ + 25 kΩ 10 kΩ 50 pF 10 kΩ MHB795 25 kΩ 100 pF MHB794 Fig.6 Pin 4: COMP. Fig.7 Pin 5: CMO; pin 6: CSS. 8, 26 4V + 1 kΩ + 20 kΩ MHB796 MHB797 7 Fig.8 Pin 7: RFR. 2000 Dec 11 Fig.9 Pin 8: LIL; pin 26: LIR. 19 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H 4 V 10, 24 9, 25 + 4V + 30 kΩ 4V MHB798 MHB799 Fig.10 Pin 9: LOL; pin 25: LOR. + Fig.11 Pin 10: VIL; pin 24: VIR. 11, 23 4 V 4V 13, 14 20, 21 + + 80 Ω 5.4 kΩ 12 kΩ MHB801 MHB800 Fig.13 Pin 13: TC1L; pin 14: TC2L; pin 20: TC2R; pin 21: TC1R. Fig.12 Pin 11: VAL; pin 23: VAR. 2000 Dec 11 20 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H 4 V 15, 19 + 16, 18 + 28.5 kΩ 80 Ω 9.5 kΩ 4V MHB803 MHB802 Fig.14 Pin 15: BCL; pin 19: BCR. Fig.15 Pin 16: OUTL; pin 18: OUTR. 27 + 3.4 kΩ 28 4.7 kΩ 300 Ω 3.4 kΩ 5 kΩ MHB805 MHB804 Fig.16 Pin 27: Vref. Fig.17 Pin 28: VCAP. 29 30 + + MHB807 MHB806 Fig.18 Pin 29: CAV. 2000 Dec 11 Fig.19 Pin 30: TW. 21 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H + 35 31 + + 6 kΩ 16 kΩ 32 MHB808 MHB809 Fig.20 Pin 31: CW. Fig.21 Pin 32: BPU; pin 35: FDI. 38 33 1.8 kΩ + MHB810 MHB811 Fig.22 Pin 33: FDO. Fig.23 Pin 38: SDA. 5 V 40 39 1.8 kΩ + 1.8 kΩ MHB812 MHB813 Fig.24 Pin 39: MAD (I2C-bus address switch). 2000 Dec 11 Fig.25 Pin 40: SCL. 22 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H 42 4V + 41 + MHB814 10 kΩ 10 kΩ MHB815 Fig.26 Pin 41: VCC. Fig.27 Pin 42: CPH. 43 + 3 kΩ MHB816 Fig.28 Pin 43: CER. 2000 Dec 11 23 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1 c y X 33 A 23 34 22 ZE e E HE A A2 (A 3) A1 wM θ bp Lp pin 1 index 44 L 12 detail X 1 11 ZD e v M A wM bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.60 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 14.1 13.9 1 19.2 18.2 19.2 18.2 2.35 2.0 1.2 0.3 0.15 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT205-1 133E01 2000 Dec 11 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-08-01 99-12-27 24 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2000 Dec 11 TDA9853H 25 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Dec 11 26 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder and audio processor TDA9853H DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Dec 11 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/01/pp28 Date of release: 2000 Dec 11 Document order number: 9397 750 07474