INTEGRATED CIRCUITS FB2040A 8-bit Futurebus+ transceiver Product specification IC19 Data Handbook 1995 May 25 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A • Compatible with IEEE Futurebus+ or proprietary BTL backplanes • Controlled output ramp and multiple GND pins minimize ground FEATURES • 8-bit BTL transceivers • Separate I/O on TTL A-port • Inverting • Drives heavily loaded backplanes with equivalent load bounce • Each BTL driver has a dedicated Bus GND for a signal return • Glitch-free power up/power down operation • Low ICC current • Tight output skew • Supports live insertion • Pins for the optional JTAG boundary scan function are provided • High density packaging in plastic Quad Flat Pack impedances down to 10Ω. • High drive 100mA BTL open collector drivers on B-port • Allows incident wave switching in heavily loaded backplane buses • Reduced BTL voltage swing produces less noise and reduces power consumption • Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity QUICK REFERENCE DATA SYMBOL TYPICAL UNIT tPLH tPHL Propagation delay AIn to Bn 4.4 3.1 ns tPLH tPHL Propagation delay Bn to AOn 3.4 3.2 ns COB Output capacitance (B0 – B7 only) IOL Output current (B0 – B7 only) ICC PARAMETER 4 pF 100 mA Standby 4 AIn to Bn (outputs Low or High) 4 Bn to AOn (outputs Low) 22 Bn to AOn (outputs High) 12 Supply current mA ORDERING INFORMATION PACKAGES COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C DRAWING NUMBER 52-pin Plastic Quad Flat Pack (QFP) FB2040BB SOT379-1 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. PARAMETER SYMBOL VCC Supply voltage VIN Input voltage IIN Input current RATING UNIT -0.5 to +7.0 V AI0 – AI7, OEB0, OEB1, OEA -1.2 to +7.0 B0 – B7 -1.2 to +5.5 V -18 to +5.0 mA -0.5 to +VCC V VOUT Voltage applied to output in High output state IOUT O Current applied to output in Low output state Tamb Operating free-air temperature range -40 to ++85 °C TSTG Storage temperature -65 to +150 °C 1995 May 25 2 A0 – A7 48 B0 – B7 200 mA 853-1801 15279 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A B0/B0 TMS (option) BUS GND TCK (option) BUS VCC OEB1 OEA OEB0 BIAS V LOGIC VCC AI0 AO0 AO1 PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 BUS GND LOGIC GND 1 39 AI1 2 38 B1 AI2 3 37 BUS GND AO2 4 36 B2 LOGIC GND 5 8-Bit Transceiver 35 BUS GND AO3 6 FB2040A 34 B3 LOGIC GND 7 33 BUS GND AI3 8 32 B4 AI4 9 31 BUS GND AO4 10 30 B5 LOGIC GND 11 29 BUS GND AO5 12 28 B6 LOGIC GND 13 27 BUS GND 52-lead PQFP NC AI7 BUS VCC TDI (option) AO7 B7 SG00076 or if OEB1 is High, the B-port is inactive and is at the level of the backplane signal. DESCRIPTION The FB2040A is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2040A is an inverting transceiver. To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 2.5V. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time. The B-port has two output enables, OEB0 and OEB1. When OEB0 is High and OEB1 is Low the output is enabled. When OEB0 is Low 1995 May 25 TDO (option) AI6 BG GND BG VCC AO6 AI5 LOGIC GND 14 15 16 17 18 19 20 21 22 23 24 25 26 3 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A PIN DESCRIPTION SYMBOL PIN NUMBER TYPE AI0 – AI7 51, 2, 3, 8, 9, 14, 18, 24 Input NAME AND FUNCTION AO0 – AO7 50, 52, 4, 6, 10, 12, 16, 20 Output B0 – B7 40, 38, 36, 34, 32, 30, 28, 26 I/O OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low OEA 47 Input Enables the A outputs when High Data inputs (TTL) 3-state outputs (TTL) Data inputs/Open Collector outputs. High current drive (BTL) BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V) LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V) BUS VCC 23, 43 Power Positive supply voltage LOGIC VCC 49 Power Positive supply voltage BG VCC 17 Power Band Gap threshold voltage reference BG GND 19 GND Band Gap threshold voltage reference ground BIAS V 48 Power Live insertion pre-bias pin TMS 42 Input Test Mode Select (optional, if not implemented then no-connect) TCK 44 Input Test Clock (optional, if not implemented then no-connect) TDI 22 Input Test Data In (optional, if not implemented then shorted to TDO) TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI) NC 25 NC No Connect FUNCTION TABLE MODE AIn to Bn Disable Bn out outputs uts Bn to AOn Disable AOn outputs H** = B* = INPUTS OUTPUTS AIn Bn* OEB0 OEB1 OEA AOn Bn* L — H L L Z H** H — H L L Z L L — H L H L H** H — H L H H L X X L X X X H** X X X H X X H** X L L X H H Input X H X H H L Input X L X H H H Input X H L X H L Input — X X X L Z X Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. 1995 May 25 4 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC Supply voltage VIH High-level in input ut voltage VIL Low-level in input ut voltage IIK Input clamp current IOH High-level output current IOL Low-level out output ut current COB Output capacitance on B port Tamb Operating free-air temperature range 1995 May 25 LIMITS PARAMETER MIN NOM MAX 4.5 5.0 5.5 Except B0–B7 2.0 B0 – B7 1.62 UNIT V V 1.55 Except B0–B7 0.8 B0 – B7 1.47 V -18 mA AO0 – AO7 -3 mA AO0 – AO7 24 B0 – B7 100 0 5 mA 5 pF +70 °C Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A LOGIC DIAGRAM FOR FB2040 OEB0 OEB1 OEA 46 45 47 40 AI0 AO0 51 50 38 AI1 AO1 2 AO2 3 TTL Levels AO3 8 AO4 BTL Levels 9 AO5 14 AO6 18 AO7 TMS TCK TDI TDO NC = LOGIC VCC = LOGIC GND = = BUS VCC BUS GND = BIAS V = = BG VCC BG GND = B6 16 26 AI7 B5 12 28 AI6 B4 10 30 AI5 B3 6 32 AI4 B2 4 34 AI3 B1 52 36 AI2 B0 24 B7 20 42 44 22 21 (Future JTAG Boundary Scan option) 25 49 1, 5, 7, 11, 13, 15 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48 17 19 SG00077 1995 May 25 6 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT IOH High level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA IOFF Power-off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA VOH High-level output voltage VOL Low-level output voltage VIK Input clamp voltage AO0 – AO73 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA AO0 – AO73 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA B0 – B7 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA 2.5 .75 2.85 V 0.33 0.5 1.0 1.10 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15 VCC = MIN, II = IIK -1.2 V µA II Input current at maximum input voltage OEB0, OEB1, OEA, AI0–AI7 VCC = MAX, VI = GND or 5.5V ±50 IIH High level in ut current High-level input OEB0, OEB1, OEA, AI0–AI7 VCC = MAX, VI = 2.7V 20 B0 – B7 VCC = MAX, VI = 2.1V 100 OEB0, OEB1, OEA, AI0–AI7 VCC = MAX, VI = 0.5V -20 B0 – B7 VCC = MAX, VI = 0.75V -100 IIL Low-level Low level in input ut current V µA µA IOZH Off-state output current AO0 – AO7 VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current AO0 – AO7 VCC = MAX, VO = 0.5V -50 µA IOS Short-circuit output current4 AO0 – AO7 only VCC = MAX, VO = 0.0V -150 mA ICCZ (standby) VCC = MAX 19 30 ICCB, AIn to Bn VCC = MAX, outputs Low or High 40 60 ICCA, Bn to AOn VCC = MAX, outputs Low 22 35 ICCA, Bn to AOn VCC = MAX, outputs High 19 35 ICC Supply current (total) -30 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25°C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 4. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS should be performed last. 1995 May 25 7 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A AC ELECTRICAL CHARACTERISTICS A PORT LIMITS SYMBOL PARAMETER Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω TEST CONDITION Tamb = 0 to 70°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX 3.4 3.2 5.0 4.9 1.6 1.6 5.6 5.3 ns 5.0 5.0 1.5 1.5 5.5 5.5 ns tPLH tPHL Propagation delay, Bn to AOn Waveform 1, 2 1.8 1.6 tPZH tPZL Output enable time, OEA to AOn Waveform 4, 5 1.0 1.0 tPHZ tPLZ Output disable time, OEA to AOn Waveform 4, 5 1.5 1.5 3.3 3.3 4.8 5.4 1.2 1.3 5.0 5.9 ns tTLH tTHL Transition time, AOn Port (10% to 90% or 90% to 10%) Test Circuit and Waveforms 1.5 1.5 2.2 2.4 3.5 3.5 1.0 1.0 4.5 4.5 ns 0.4 1.0 1.0 ns tSK(o) Output skew between receivers in same package1 Waveform 3 B PORT LIMITS SYMBOL PARAMETER tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 9Ω TEST CONDITION Tamb = 0 to 70°C, VCC = 5V±10%, CD = 30pF, RU = 9Ω UNIT Waveform 1, 2 2.9 1.6 4.4 3.3 5.0 4.8 2.3 1.5 5.5 5.1 ns Enable/disable time, OEB0 to Bn Waveform 2 2.9 1.9 4.7 3.5 5.9 5.1 2.6 1.8 7.8 5.7 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 3.0 1.7 5.3 3.2 6.3 4.8 2.7 1.5 8.0 5.7 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.4 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 1.0 1.0 ns tSK(o) Output skew between drivers in same package1 Waveform 3 0.3 SYMBOL PARAMETER TEST CONDITION RU = 16.5Ω tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL RU = 16.5Ω UNIT Waveform 1, 2 3.0 1.7 4.5 3.3 6.4 4.8 2.3 1.6 6.9 5.1 ns Enable/disable time, OEB0 to Bn Waveform 2 3.0 2.0 4.8 3.5 6.0 5.2 2.7 1.9 7.9 5.7 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 3.1 1.8 5.4 3.3 6.4 4.9 2.8 1.6 8.1 5.7 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.5 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 0.3 1.0 1.0 ns tSK(o) Output skew between drivers in same package1 Waveform 3 NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 1995 May 25 8 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A AC WAVEFORMS VM AIn, Bn OEB1 AIn, Bn OEB0 VM tPLH VM tPHL VM AOn, Bn VM tPHL VM tPLH AOn, Bn Waveform 1. Propagation Delay for Data or Output Enable to Output VM VM Waveform 2. Propagation Delay for Data or Output Enable to Output VM AIn, Bn tSK(o) AOn, Bn VM Waveform 3. Output Skews OEA tPZH AOn OEA VM VM VM VOH -0.3V AOn OV Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM tPLZ VM VOL +0.3V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. 1995 May 25 VM tPZL tPHZ 9 SG00078 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A TEST CIRCUIT AND WAVEFORMS VCC BIAS V VIN RL VOUT PULSE GENERATOR tW 90% 7.0V NEGATIVE PULSE RT CL VM VM 10% D.U.T. RL 10% tTHL (tf) tTLH (tr) tTHL VM (tr) (tf) VIN 90% VM 10% Test Circuit for 3-State Outputs on A Port LOW V tTLH 90% POSITIVE PULSE VIN 90% 10% tW LOW V VM = 1.55V for Bn, VM = 1.5V for all others. Input Pulse Definitions SWITCH POSITION TEST SWITCH tPLZ, tPZL All other closed open VCC BIAS V VIN 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.5ns 2.5ns tW tTLH tTHL RU D.U.T. RT CD Test Circuit for Outputs on B Port DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. SG00059 1995 May 25 10 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm 1995 May 25 11 SOT379-1 Philips Semiconductors Product specification 8-bit Futurebus+ transceiver FB2040A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1995 May 25 12 Date of release: 08-98