PHILIPS SAA6721E

INTEGRATED CIRCUITS
DATA SHEET
SAA6721E
SXGA RGB to TFT graphics engine
Preliminary specification
File under Integrated Circuits, IC02
1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
CONTENTS
8.4
1
FEATURES
1.1
1.2
1.3
1.4
1.5
1.6
1.7
RGB video input
YUV video input
Video processing
On screen display
Video output
Memory interface
Miscellaneous
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING INFORMATION
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.4
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.7
7.8
7.8.1
7.8.2
7.8.3
7.9
7.9.1
7.9.2
Data path
System clocks
Input interface clock (VCLK)
Memory interface clock (MCLKI)
I2C-bus interface clock (SCL)
System clock (CLK)
TFT panel clock (PCLK)
RGB input port
YUV input port
TFT output port
Single pixel mode
Double pixel mode
Memory port
SDRAM memory configuration
SGRAM memory configuration
I2C-bus interface
De-interlacing algorithms
Static mesh mode
Spatial filtering
Temporal filtering
Scaling algorithm
Upscaling
Downscaling
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.6
8.6.1
8.6.2
8.6.3
8.7
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.9
8.10
8.11
8.11.1
8.11.2
8.11.3
8.12
8.13
8.13.1
8.13.2
8.13.3
Video mode and synchronization signal
detection
Memory interface and de-interlacer unit
Memory interface limitations
Initialization of external memory
Frame and field memory
Frame recovery
Scaling
Downscaling
Upscaling
Upscaler transition function
Panning unit
Overlay port
Overlay insertion
Sync generation
Data sampling
OVCLK gating
Colour space matrix
Colour correction
On screen display
OSD generals
OSD window
OSD character matrix
Temporal dithering (frame rate controller)
Output interface
General
Frame generation
Timing reference signals
9
LIMITING VALUES
10
CHARACTERISTICS
11
TIMING CHARACTERISTICS
12
APPLICATION INFORMATION
13
PACKAGE OUTLINE
14
SOLDERING
14.1
8
SYSTEM DESCRIPTION
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Programming registers
Clock management
Clock generation and multiplexing
Clock divider
RGB/YUV input interface
Sampling mode
RGB data sampling
Clamp pulse generation
Gain correction pulse generation
YUV data sampling
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
1999 May 11
14.2
14.3
14.4
14.5
2
15
DEFINITIONS
16
LIFE SUPPORT APPLICATIONS
17
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
1
1.1
SAA6721E
FEATURES
RGB video input
• Digital single (24-bit) or dual (48-bit) channel RGB input
• Data input of sampled RGB data with a pixel frequency
of maximum 150 MHz
• Free definable data acquisition offsets and vertical
window size in single pixel increments, horizontal
window size in double pixel increments
1.4
• Character based internal On Screen Display (OSD)
• Programmable character matrix sizes of either
24 × 24 pixels (42 characters available) or
12 × 16 pixels (128 characters available)
• Programmable pulses for ADC clamping and ADC gain
correction
• Detection of presence of sync signals, and of their
polarities
• Programmable width and height of the OSD window,
built from maximum 1152 characters
• Support for auto-adjustment functions for sample clock
frequency, phase, vertical and horizontal sample offset,
as well as colour adjustment
• 8 different colours for foreground and background
inclusive transparent colours
• Overlay port for external OSD controller.
• Maximum supported resolution of 1280 × 1024 dots
Super Extended Graphics Adapter (SXGA)
1.5
• Support for detection of the applied graphics mode
(multi-sync).
1.2
• Generation of synchronization and validation signals for
the Thin Film Transistor (TFT) display
YUV video input
• Frame rate control (temporal dithering) for displaying
true colour graphics on high colour displays
• YUV 4 : 4 : 4, YUV 4 : 2 : 2, YUV 4 : 2 : 2 with CCIR 656
codes, YUV 4 : 1 : 1 input of interlaced and
non-interlaced digital video data
• Free programmable timing for displays of several
manufacturers.
• Maximum picture resolution of 1024 × 1024 pixels for
interlaced or non-interlaced video
1.6
• Input of video data at maximum 75 MHz
Memory interface
• Support of both 1M × 16 SDRAM, 256k × 32 SGRAM or
128k × 32 SGRAM devices
• Free definable data acquisition offsets and window in
double pixel or single line increments
• Maximum memory clock frequency of 125 MHz
• YUV to RGB colour space conversion.
• Scalable memory size built of either 2, 3 or 4 SDRAM,
or of 1 or 2 SGRAM devices
Video processing
• Special mode for operation without external memory.
• Colour correction Look-Up Table (LUT)
• Phase correct up and downscaling of the RGB data
1.7
• Fully programmable scaling ratios
Miscellaneous
• Internal Phase-Locked Loop (PLL) for memory and
panel clock generation from the system clock
• Independent horizontal and vertical scaling engine
• Free definable position of the scaled input picture inside
the output picture with programmable border colour
• I2C-bus interface with 2 selectable addresses
• Boundary scan test circuit and Joint Test Action Group
(JTAG) test controller.
• De-interlacing unit for digital YUV video data
• Zoom up to full-screen resolution of the de-interlaced
YUV video stream via the main scaler.
1999 May 11
Video output
• Single pixel/clock (24-bit) or double pixel/clock (48-bit)
digital RGB output
• Pin sharing between YUV and RGB input port
1.3
On screen display
3
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
2
SAA6721E
The SAA6721E must be embedded into a system
containing a microcontroller with an I2C-bus serial
interface. For multi-sync capabilities a frame buffer built
from SGRAM or SDRAM is needed. The size of this frame
buffer depends on the maximum resolution and bandwidth
needed for the application. For converting the analog RGB
stream into a digital data stream one or two ADCs with
3 channels each for R, G and B are needed. If the YUV
input is used, a video front-end chip such as the SAA7113
must be used in front of the YUV port.
GENERAL DESCRIPTION
The SAA6721E is a graphics engine, which converts
digital RGB or YUV data into video signals suitable for TFT
displays. It supports SXGA input resolution as well as true
colour. Independent horizontal and vertical up and
downscaling can display the input data arbitrarily on the
connected TFT display. Multi-sync capability allows the
applied graphics mode to be detected.
Overlay signals can be generated either by an internal
OSD generator or supplied via the overlay port from an
external OSD controller.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
V
IDDD
digital supply current
−
600
840
mA
Vi
input voltages
Vo
output voltages memory port
LVTTL compatible
output voltages TFT port
CMOS compatible
Tamb
4
LVTTL compatible
ambient temperature
0
−
70
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
SAA6721E
1999 May 11
NAME
DESCRIPTION
VERSION
BGA292
plastic ball grid array package; 292 balls; body 27 × 27 × 1.75 mm
SOT489-1
4
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
AUTO
ADJUSTMENT
CONTROLLER
VCLK
TDO
TMS
TDI
RST
TCLK
OVACT
TRST
OVB2
to
OVB0
OVHS
OVCLK
I2C-BUS
INTERFACE
frequency,
phase and
colour
information
RGB
raw data
VVS
INT
SAD
GLOBAL CONTROL
UNIT
JTAG
CONTROLLER
LINE MEMORY
VHS
CLAMP
UP
SCALER
GAINC
5
VPA7 to VPA0
COLOUR
CORRECTION
OSD
OVERLAY
PORT
PANNING
UNIT
YUV
RGB/YUV
INPUT
INTERFACE
SXGA RGB to TFT graphics engine
input frame size and
sync information
MODE/SYNC
DETECTION
BLOCK DIAGRAM
SDA
SCL
Philips Semiconductors
5
handbook, full pagewidth
1999 May 11
OVA2 to OVA0 OVVS
RGB
VPB7 to VPB0
ON
SCREEN
DISPLAY
SAA6721E
VPC7 to VPC0
PAR7 to PAR0
TEMPORAL
DITHERING
PAG7 to PAG0
PAB7 to PAB0
VPD7 to VPD0
RGB/YUV
data
VPE7 to VPE0
VPF7 to VPF0
MCLKI
÷2
CLK
PBR7 to PBR0
DOWN
SCALER
OUTPUT
INTERFACE
MEMORY INTERFACE
PBB7 to PBB0
PVS
DE-INTERLACER
memory
clock
PBG7 to PBG0
PHS
PDE
PLL
DIVIDER
panel
clock
PCLK
BA
A10
to
A0
RAS
CAS
Fig.1 Block diagram.
WE MCLKO
VSSD
VDDD
VDD(PLL)
VSS(PLL)
SAA6721E
DQ63 DQM
to
DQ0
Preliminary specification
MHB241
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
6
SAA6721E
PINNING INFORMATION
MHB242
handbook, halfpage
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
SAA6721E
1
2
3
4
5
6
7
8
9
10 12 14 16 18 20
11 13 15 17 19
Fig.2 Pin configuration.
Table 1
SYMBOL
PIN
PORT
I/O(1)
DESCRIPTION
VCLK
N1
RGB/YUV input
input
RGB/YUV sample clock
VVS
M3
RGB/YUV input
input
RGB/YUV vertical sync
VHS
M2
RGB/YUV input
input
RGB/YUV horizontal sync
VPA7
C7
RGB/YUV input
input
VPA6
A6
RGB/YUV input
input
video input port A;
RGB port 0 red channel or YUV port luminance
VPA5
B6
RGB/YUV input
input
VPA4
C6
RGB/YUV input
input
VPA3
A5
RGB/YUV input
input
VPA2
D5
RGB/YUV input
input
VPA1
B5
RGB/YUV input
input
VPA0
C5
RGB/YUV input
input
1999 May 11
6
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
VPB7
PIN
A4
PORT
RGB/YUV input
I/O(1)
DESCRIPTION
input
VPB6
B4
RGB/YUV input
input
VPB5
C4
RGB/YUV input
input
VPB4
A3
RGB/YUV input
input
VPB3
B3
RGB/YUV input
input
VPB2
C3
RGB/YUV input
input
VPB1
A2
RGB/YUV input
input
VPB0
B2
RGB/YUV input
input
VPC7
B1
RGB/YUV input
input
VPC6
C2
RGB/YUV input
input
VPC5
C1
RGB/YUV input
input
VPC4
D3
RGB/YUV input
input
VPC3
D2
RGB/YUV input
input
VPC2
D1
RGB/YUV input
input
VPC1
E3
RGB/YUV input
input
VPC0
E2
RGB/YUV input
input
VPD7
E4
RGB/YUV input
input
VPD6
E1
RGB/YUV input
input
VPD5
F3
RGB/YUV input
input
VPD4
F2
RGB/YUV input
input
VPD3
F1
RGB/YUV input
input
VPD2
G3
RGB/YUV input
input
VPD1
G2
RGB/YUV input
input
VPD0
G4
RGB/YUV input
input
VPE7
G1
RGB/YUV input
input
VPE6
H3
RGB/YUV input
input
VPE5
H2
RGB/YUV input
input
VPE4
H1
RGB/YUV input
input
VPE3
J2
RGB/YUV input
input
VPE2
J4
RGB/YUV input
input
VPE1
J1
RGB/YUV input
input
VPE0
K3
RGB/YUV input
input
VPF7
K2
RGB/YUV input
input
VPF6
K1
RGB/YUV input
input
VPF5
L1
RGB/YUV input
input
VPF4
L4
RGB/YUV input
input
VPF3
L2
RGB/YUV input
input
VPF2
L3
RGB/YUV input
input
VPF1
M1
RGB/YUV input
input
VPF0
M4
RGB/YUV input
input
1999 May 11
SAA6721E
video input port B;
RGB port 0 green channel or YUV port chrominance
video input port C;
RGB port 0 blue channel or YUV port chrominance
video input port D;
RGB port 1 red channel or YUV data qualifier port
(VPD7 = CREF clock gating signal;
VPD6 = HREF active horizontal video)
video input port E; RGB port 1 green channel
video input port F; RGB port 1 blue channel
7
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
CLAMP
PIN
PORT
SAA6721E
I/O(1)
DESCRIPTION
N2
RGB/YUV input
GAINC
N3
RGB/YUV input
output
gain correction pulse for analog-to-digital converter
PCLK
Y13
panel interface
output
panel clock
PVS
V12
panel interface
output
panel vertical sync
PHS
W12 panel interface
output
panel horizontal sync
PDE
U12
panel interface
output
panel data enable
PAR7
P1
panel interface
output
panel port A red channel
PAR6
P4
panel interface
output
PAR5
P2
panel interface
output
PAR4
P3
panel interface
output
PAR3
R1
panel interface
output
PAR2
R2
panel interface
output
PAR1
R3
panel interface
output
PAR0
T1
panel interface
output
PAG7
T4
panel interface
output
PAG6
T2
panel interface
output
PAG5
T3
panel interface
output
PAG4
U1
panel interface
output
PAG3
U2
panel interface
output
PAG2
V1
panel interface
output
PAG1
V2
panel interface
output
PAG0
W1
panel interface
output
PAB7
Y1
panel interface
output
PAB6
W2
panel interface
output
PAB5
Y2
panel interface
output
PAB4
V3
panel interface
output
PAB3
W3
panel interface
output
PAB2
Y3
panel interface
output
PAB1
V4
panel interface
output
PAB0
Y4
panel interface
output
PBR7
V5
panel interface
output
PBR6
W5
panel interface
output
PBR5
Y5
panel interface
output
PBR4
V6
panel interface
output
PBR3
W6
panel interface
output
PBR2
Y6
panel interface
output
PBR1
V7
panel interface
output
PBR0
W7
panel interface
output
1999 May 11
output
clamp pulse for analog-to-digital converter
panel port A green channel
panel port A blue channel
panel port B red channel
8
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
SAA6721E
I/O(1)
PIN
PORT
Y7
panel interface
output
PBG6
V8
panel interface
output
PBG5
W8
panel interface
output
PBG4
Y8
panel interface
output
PBG3
V9
panel interface
output
PBG2
W9
panel interface
output
PBG1
U9
panel interface
output
PBG0
Y9
panel interface
output
PBB7
V10
panel interface
output
PBB6
W10 panel interface
output
PBB5
Y10
panel interface
output
PBB4
Y11
panel interface
output
PBB3
U11
panel interface
output
PBB2
W11 panel interface
output
PBB1
V11
panel interface
output
PBB0
Y12
panel interface
output
SCL
V18
I2C-bus
input
I2C-bus interface clock line
SDA
W18
input/output
I2C-bus interface data line
SAD
Y17
input
I2C-bus address select: 0 = 74H, 1 = 76H
OVCLK
Y16
overlay
output
overlay port clock
OVVS
W16 overlay
output
overlay port vertical sync
OVHS
V15
overlay
output
overlay port horizontal sync
OVACT
V16
overlay
input
overlay port pixel active
OVA0
Y14
overlay
input
overlay port input pixel A
OVA1
V13
overlay
input
OVA2
W13 overlay
input
OVB0
Y15
overlay
input
OVB1
V14
overlay
input
OVB2
W14 overlay
input
MCLKO
A17
memory interface
output
memory clock output
RAS
A18
memory interface
output
memory Row Address Strobe (RAS) signal (active LOW)
memory interface
output
memory Column Address Strobe (CAS) signal
(active LOW)
PBG7
CAS
C17
interface
DESCRIPTION
panel port B green channel
panel port B blue channel
overlay port input pixel B
WE
D16
memory interface
output
memory Write Enable (WE) signal (active LOW)
DQM
T17
memory interface
output
memory data mask (active LOW)
1999 May 11
9
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
PIN
PORT
SAA6721E
I/O(1)
A0
A20
memory interface
output
A1
C20
memory interface
output
A2
D20
memory interface
output
A3
E19
memory interface
output
DESCRIPTION
memory address bus
A4
F18
memory interface
output
A5
E17
memory interface
output
A6
E18
memory interface
output
A7
C19
memory interface
output
A8
C18
memory interface
output
A9
D18
memory interface
output
A10
B19
memory interface
output
BA
A19
memory interface
output
memory bank select
DQ0
M20 memory interface
input/output
memory data bus
DQ1
M19 memory interface
input/output
DQ2
N20
memory interface
input/output
DQ3
N19
memory interface
input/output
DQ4
P19
memory interface
input/output
DQ5
R19
memory interface
input/output
DQ6
T20
memory interface
input/output
DQ7
T19
memory interface
input/output
DQ8
T18
memory interface
input/output
DQ9
R18
memory interface
input/output
DQ10
P18
memory interface
input/output
DQ11
P17
memory interface
input/output
DQ12
N18
memory interface
input/output
DQ13
M18 memory interface
input/output
DQ14
M17 memory interface
input/output
DQ15
L19
memory interface
input/output
DQ16
E20
memory interface
input/output
DQ17
F20
memory interface
input/output
DQ18
G20 memory interface
input/output
DQ19
H20
memory interface
input/output
DQ20
J20
memory interface
input/output
DQ21
K19
memory interface
input/output
DQ22
K20
memory interface
input/output
DQ23
L20
memory interface
input/output
DQ24
K17
memory interface
input/output
DQ25
K18
memory interface
input/output
DQ26
J19
memory interface
input/output
DQ27
J18
memory interface
input/output
DQ28
H19
memory interface
input/output
1999 May 11
10
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
PIN
PORT
SAA6721E
I/O(1)
DQ29
H18
memory interface
input/output
DQ30
G18 memory interface
input/output
DQ31
F19
memory interface
input/output
DQ32
A12
memory interface
input/output
DQ33
B12
memory interface
input/output
DQ34
A13
memory interface
input/output
DQ35
B13
memory interface
input/output
DQ36
A14
memory interface
input/output
DQ37
B14
memory interface
input/output
DQ38
A15
memory interface
input/output
DQ39
B15
memory interface
input/output
DQ40
A16
memory interface
input/output
DQ41
C15
memory interface
input/output
DQ42
C14
memory interface
input/output
DQ43
D14
memory interface
input/output
DQ44
C13
memory interface
input/output
DQ45
C12
memory interface
input/output
DQ46
D12
memory interface
input/output
DQ47
C11
memory interface
input/output
DQ48
B7
memory interface
input/output
DQ49
A7
memory interface
input/output
DQ50
B8
memory interface
input/output
DQ51
A8
memory interface
input/output
DQ52
B9
memory interface
input/output
DESCRIPTION
memory data bus
DQ53
A9
memory interface
input/output
DQ54
B10
memory interface
input/output
DQ55
A10
memory interface
input/output
DQ56
B11
memory interface
input/output
DQ57
A11
memory interface
input/output
DQ58
D10
memory interface
input/output
DQ59
C10
memory interface
input/output
DQ60
D9
memory interface
input/output
DQ61
C9
memory interface
input/output
DQ62
C8
memory interface
input/output
DQ63
D7
memory interface
input/output
TCLK
U19
JTAG test controller
input
JTAG test controller clock; note 2
TRST
W17
input
JTAG test controller reset (active LOW); note 2
TDI
U18
input
JTAG test data input; note 2
TMS
V19
input
JTAG test mode select; note 2
TDO
W19
output
JTAG test data output
1999 May 11
11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
CLK
PIN
PORT
Y19
miscellaneous
SAA6721E
I/O(1)
DESCRIPTION
input
system and panel clock
RST
Y20
input
system reset (active LOW)
INT
Y18
output
mode detection interrupt (active LOW)
MCLKI
W20
input
memory clock input
−
−
digital ground supply
−
−
digital supply voltage
−
−
ground supply for internal PLL circuitry
VSSD
A1
D4
D8
D13
D17
H4
H17
N4
N17
U4
U8
U13
U17
VDDD
D6
D11
D15
F4
F17
K4
L17
R4
R17
U6
U10
U15
VSS(PLL)
V17
VDD(PLL)
U16
−
−
supply voltage for internal PLL circuitry
n.c.
B16
−
−
not connected
n.c.
B17
−
−
not connected
n.c.
B18
−
−
not connected
n.c.
B20
−
−
not connected
n.c.
C16
−
−
not connected
n.c.
D19
−
−
not connected
n.c.
G17 −
−
not connected
n.c.
G19 −
−
not connected
n.c.
J3
−
−
not connected
n.c.
J17
−
−
not connected
1999 May 11
12
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
n.c.
PIN
L18
I/O(1)
PORT
−
SAA6721E
DESCRIPTION
−
not connected
n.c.
P20
−
−
not connected
n.c.
R20
−
−
not connected
n.c.
U3
−
−
not connected
n.c.
U5
−
−
not connected
n.c.
U7
−
−
not connected
n.c.
U14
−
−
not connected
n.c.
U20
−
−
not connected
n.c.
V20
−
−
not connected
n.c.
W4
−
−
not connected
n.c.
W15 −
−
not connected
Notes
1. Generally all inputs are 5 V tolerant TTL inputs. All outputs are CMOS, except the memory interface ports, which are
LVTTL compatible.
2. Connect to ground when not using the JTAG controller.
7
7.1
FUNCTIONAL DESCRIPTION
7.2
Data path
7.2.1
INPUT INTERFACE CLOCK (VCLK)
This clock is used for sampling the incoming RGB or YUV
data stream. In RGB mode this clock varies from
25 to 150 MHz in single ADC mode. If two ADCs are used
the RGB input clock is between 12.5 and 75 MHz. In YUV
mode the clock lies in the range of approximately 30 MHz.
The clocks are generated from external devices.
Input video data is sampled either as RGB data in single
pixels from only one ADC or in double pixels in interleaved
format from two ADCs. Alternatively the input interface can
sample interlaced or non-interlaced YUV data. The clock
for sampling the data will always be provided from external
circuitry. The video stream will be adapted from the input
frame rate to the output frame rate needed by the panel.
Therefore a frame buffer built of SDRAMs or SGRAMs is
used. If the panel supports the incoming frame rate from
the RGB port, the adaption can be done without external
memory. If the video stream is in interlaced format the
memory interface activates its de-interlacing unit.
The RGB clock can be generated by the external ADCs or
an external video PLL. The YUV clock must be generated
by the video decoder which also provides the YUV video
data.
7.2.2
If zooming must be performed the upscaler behind the
memory interface will be enabled. For downscaling the
downscaler in front of the memory interface in the data
path will be used. A colour correction can be done via a
look-up table. The resulting video stream can now be
positioned elsewhere in the output data stream by the
panning unit. If an external OSD controller is embedded
into the system, its OSD window will be put into the video
stream by the OSD overlay port. Additionally the internal
OSD will be inserted in the next stage. The temporal
dithering allows true colour pictures to be displayed on
high colour panels. The output interface provides the
timing and control signals necessary for the connected
panel.
1999 May 11
System clocks
MEMORY INTERFACE CLOCK (MCLKI)
The memory clock is the synchronous clock for the
external frame buffer. Depending on the bandwidth
needed by the application, and the connected SDRAM or
SGRAM devices, the clock varies from 83 to 125 MHz.
It can be generated internally by the PLL from the system
clock (CLK), or by an external quartz oscillator.
If the internal PLL is used, the memory clock frequency
can be derived from the following formula:
f_system
f_memory = ------------------------ × 16
N
Where N = pre-divider ratio and f_system = clock at
pin CLK.
13
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.2.3
SAA6721E
Therefore ports VPD7 to VPD0, VPE7 to VPE0, and
VPF7 to VPF0 are also needed.
I2C-BUS INTERFACE CLOCK (SCL)
This clock drives the interface to the external
microcontroller. Its frequency range is from
100 kHz to 1 MHz.
7.2.4
The VPA/B/C ports are sampled on the rising edge of the
RGB input clock (VCLK), and the VPD/E/F ports on the
falling edge (see Fig.3).
SYSTEM CLOCK (CLK)
The synchronization pulses from the graphics card are
used to identify the frame outline. The vertical
synchronization pulse is connected to pin VVS, and the
horizontal synchronization pulse is connected to pin VHS.
This clock is used to drive the internal PLL. The frequency
range is from 24 to 50 MHz.
7.2.5
TFT PANEL CLOCK (PCLK)
For calibrating the connected Analog-to-Digital Converter
(ADC) the SAA6721E delivers a clamp pulse at
pin CLAMP, and a gain correction pulse at pin GAINC
(see Fig.4).
This clock is the timing reference for the panel.
The frequency is the same as the system clock, or it can
be generated from the internal PLL by using the following
formula:
The sample window of the RGB input port is controlled by
four counters; horizontal and vertical offset, and horizontal
and vertical window size.
f_system 32
f_tft = ------------------------ × -----N
M
Where N = pre-divider ratio and M = post-divider ratio.
7.3
The offset counters start at the inactive or second edge of
their corresponding synchronization signal.
RGB input port
The RGB input port can operate in two modes; single pixel
mode (24 bits) and double pixel mode (48 bits). For single
pixel mode only ports VPA7 to VPA0, VPB7 to VPB0, and
VPC7 to VPC0 are internally sampled. For double pixel
mode two pixels must be provided at the RGB input port.
handbook, full pagewidth
VCLK
VPA/B/C
VPD/E/F
MHB243
Fig.3 RGB input port timing.
1999 May 11
14
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
VHS
blanking
RGB data
GAINC
CLAMP
MHB244
Fig.4 Clamp and gain correction pulses.
7.4
YUV 4 : 4 : 4 data can be applied at VPA7 to VPA0 (Y),
VPB7 to VPB0 (U), and VPC7 to VPC0 (V). Input data is
sampled with respect to the clock at pin VCLK if pin VPD7
(CREF) is asserted.
YUV input port
The YUV input port supports interlaced video streams and
provides an easy connection to most common decoder
ICs. It consists of the luminance port VPA7 to VPA0, the
chrominance port VPB7 to VPB0, and eventually
VPC7 to VPC0, which are CCIR 601 level compatible
(Y: 16 to 235, and UV: 16 to 240).
The start of active video data in a line is marked by the
rising edge at pin VPD6 (HREF) and the end of valid video
data is marked by the falling edge at pin VPD6. Figure 5
illustrates this at a YUV 4 : 2 : 2 example.
Supported at this port are the formats YUV 4 : 1 : 1,
YUV 4 : 2 : 2 and YUV 4 : 2 : 2 with CCIR 656 codes
(see Table 2).
handbook, full pagewidth
VCLK
CREF
HREF
Y7 to Y0
XX
Y0
Y1
Y2
Y3
...
Y5
Y6
Y719
XX
UV7 to UV0 XX
U0
V0
U2
V2
...
V716
U718
V718
XX
MHB245
Fig.5 CREF and HREF timing.
1999 May 11
15
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 2
SAA6721E
YUV input formats
SIGNAL
4 : 1 : 1 FORMAT
4 : 2 : 2 FORMAT
CCIR 656
Y7
Y07
Y17
Y27
Y37
Y07
Y17
U07
Y07
V07
Y17
Y6
Y06
Y16
Y26
Y36
Y06
Y16
U06
Y06
V06
Y16
Y5
Y05
Y15
Y25
Y35
Y05
Y15
U05
Y05
V05
Y15
Y4
Y04
Y14
Y24
Y34
Y04
Y14
U04
Y04
V04
Y14
Y3
Y03
Y13
Y23
Y33
Y03
Y13
U03
Y03
V03
Y13
Y2
Y02
Y12
Y22
Y32
Y02
Y12
U02
Y02
V02
Y12
Y1
Y01
Y11
Y21
Y31
Y01
Y11
U01
Y01
V01
Y11
Y0
Y00
Y10
Y20
Y30
Y00
Y10
U00
Y00
V00
Y10
UV7
U07
U05
U03
U01
U07
V07
X
X
X
X
UV6
U06
U04
U02
U00
U06
V06
X
X
X
X
UV5
V07
V05
V03
V01
U05
V05
X
X
X
X
UV4
V06
V04
V02
V00
U04
V04
X
X
X
X
UV3
X
X
X
X
U03
V03
X
X
X
X
UV2
X
X
X
X
U02
V02
X
X
X
X
UV1
X
X
X
X
U01
V01
X
X
X
X
UV0
X
X
X
X
U00
V00
X
X
X
X
1⁄
Data frequency
1⁄
2VCLK
For YUV 4 : 4 : 4 the Y, U, and V components are available
in parallel.
VCLK
sampled. The decoding of odd and even fields is done with
HREF. In CCIR 656 data streams the included codes are
used for identifying even and odd frames, blanking and
active video data. The codes start with the byte sequence
FF 00 00, followed by the reference code byte;
see Figs 6 and 7.
If non-interlaced video data is applied, it is treated as odd
fields. Interlaced video data is sampled odd field,
even field, odd field, even field, etc. If there are equal
subsequent frames, only the first of these frames will be
handbook, full pagewidth
2VCLK
VCLK
Y7 to Y0 XX
FF
00
00
SAV
U0
Y0
V0
Y1
...
MHB246
Fig.6 CCIR 656 SAV code.
handbook, full pagewidth
VCLK
Y7 to Y0
...
U718
Y718
V718
Y719
FF
00
00
EAV
XX
MHB247
Fig.7 CCIR 656 EAV code.
1999 May 11
16
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
The CCIR 656 code byte contains vertical and horizontal
blanking as well as odd and even field information, the
protection bits P3 to P0 are ignored.
Table 3
7.5.2
The double pixel mode is used for direct connection of TFT
panels with double pixel input. Both output ports are used.
The first pixel is applied at port A, and the second at port B.
CCIR 656 code byte
MSB
7.6
LSB
7
6
5
4
3
2
1
0
1
F(1)
V(2)
H(3)
P3
P2
P1
P0
DOUBLE PIXEL MODE
Memory port
The memory port connects the SAA6721E to the external
frame buffer. This frame memory can be built from either
1M × 16 SDRAM or 256k × 32 SGRAM devices.
Supported are RAM devices with clock frequencies up to
125 MHz. This clock can be provided either by the internal
PLL, or externally be applied to pin MCLKI.
Notes
1. F = 0: odd field (field 1); F = 1: even field (field 2).
2. V = 0: in active field lines; V = 1: in field blanking.
3. H = 0: SAV (Start of Active Video);
H = 1: EAV (End of Active Video).
The memory data bus is split into 4 ports:
port 0 (DQ0 to DQ15), port 1 (DQ16 to DQ31),
port 2 (DQ32 to DQ47) and port 3 (DQ48 to DQ63).
The sample window of the YUV input port is controlled by
four counters; horizontal and vertical offset, and horizontal
and vertical window size. The vertical offset counter starts
counting from the inactive or second edge of its
corresponding reference signal. The horizontal offset
counter starts with the active edge of the HREF signal.
To adapt the external memory to the needs of the
application by means of memory size and bandwidth, it is
possible to scale the external memory by using only the
number of subsequent ports needed to build up the frame
buffer and to achieve the memory bandwidth. As a second
step for bandwidth optimization several speed grades of
memory devices can be used.
7.5
TFT output port
7.6.1
The TFT output port consists of two pixel ports (A and B),
each containing red, green and blue colour information
with a resolution of 8 bits per colour. The first pixel port is
mapped to PAR7 to PAR0, PAG7 to PAG0, and
PAB7 to PAB0. The second port is mapped to
PBR7 to PBR0, PBG7 to PBG0, and PBB7 to PBB0.
SDRAMs are available in sizes from 16 Mbits. For this
application a wide data bus is required, so that at least
1M × 16 devices must be used. To achieve the desired
bandwidth, 2 to 4 devices must be used in parallel, which
results in a frame buffer size of 4 to 8 Mbytes. But only half
of this memory will be used by the SAA6721E.
The vertical and horizontal synchronization signals are
mapped to pins PVS and PHS. A data validation signal
framing visible pixels is available at pin PDE.
The memory port of the SAA6721E can be divided into
4 SDRAM channels. Each channel is 16 bits wide, and
provides in High Speed Channel (HSC) mode with a
125 MHz memory clock and an effective bandwidth of
228 Mbits/s. A Medium Speed Channel (MSC) with a
100 MHz memory clock gives an effective bandwidth of
182 Mbits/s, 91% effective bandwidth assumed.
All of the above mentioned signals are synchronized to the
output clock at pin PCLK. The active edge of this clock is
programmable.
7.5.1
SINGLE PIXEL MODE
Table 4 gives the channel configuration for several input
and panel resolutions.
The single pixel mode is designed to support TFT panels
with single pixel input, and for direct connection of panel
link transmitters. Only the first pixel port PAR7 to PAR0,
PAG7 to PAG0, and PAB7 to PAB0 is used. The data is
applied at double the frequency in comparison to the
double pixel output mode.
1999 May 11
SDRAM MEMORY CONFIGURATION
17
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 4
SAA6721E
SDRAM channel configurations
INPUT
RESOLUTION
SVGA (800 × 600)
60 Hz
75 Hz
XGA (1024 × 768)
60 Hz
75 Hz
SXGA (1280 × 1024)
60 Hz
75 Hz
Panel
2 Mbits frame buffer needed
3 Mbits frame buffer needed
4 Mbits frame buffer needed
XGA(1)
288 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
319 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
411 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
452 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
475 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
540 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
SXGA(2)
307 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
337 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
435 Mbits/s
bandwidth;
2 × HSC or
3 × MSC
476 Mbits/s
bandwidth;
3 × HSC or
3 × MSC
624 Mbits/s
bandwidth;
3 × HSC or
4 × MSC
705 Mbits/s
bandwidth;
4 × HSC or
4 × MSC
Notes
1. 36 MHz clock frequency.
2. 50 MHz clock frequency.
7.6.2
Each channel gives, in HSC mode with 125 MHz clock
frequency, an effective bandwidth of 456 Mbits/s; and in
MSC mode, with 100 MHz clock speed, an effective
bandwidth of 364 Mbits/s.
SGRAM MEMORY CONFIGURATION
SGRAM devices organized to 256k × 32 bits are available,
and feature the wide data bus for high speed applications.
With these devices a frame buffer can be built, without
wasting memory because of bandwidth. In case of
SGRAM usage, the memory data bus of the SAA6721E
can be split into 2 channels of 32 bits each.
Table 5
Table 5 gives the channel configuration for several input
and panel resolutions.
SGRAM channel configurations
INPUT
RESOLUTION
SVGA (800 × 600)
60 Hz
75 Hz
XGA (1024 × 768)
60 Hz
75 Hz
SXGA (1280 × 1024)
60 Hz
75 Hz
Panel
2 Mbits frame buffer needed
3 Mbits frame buffer needed
4 Mbits frame buffer needed
XGA(1)
288 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
319 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
411 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
452 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
475 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
540 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
SXGA(2)
307 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
337 Mbits/s
bandwidth;
1 × HSC or
1 × MSC
435 Mbits/s
bandwidth;
1 × HSC or
2 × MSC
476 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
624 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
705 Mbits/s
bandwidth;
2 × HSC or
2 × MSC
Notes
1. 36 MHz clock frequency.
2. 50 MHz clock frequency.
1999 May 11
18
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.7
SAA6721E
The device address of the SAA6721E must then be sent
with the desired I/O direction.
I2C-bus interface
This serial interface consists of only two signals, the serial
clock line (SCL) and the serial data line (SDA).
The maximum supported frequency on this bus is 1 MHz.
Spikes with a maximum pulse length of 50 ns are
suppressed by the internal input filter.
If the SAA6721E reads its device address, it
acknowledges this by sending a single bit ACK to the
master. If write mode was selected, the master sends the
register address to be written and then the data bytes.
If read mode was selected, the SAA6721E sends the data
bytes starting from the last address accessed either by
write command or the next address at a read command.
The SAA6721E operates as a slave and cannot initiate
any data transfer, so the clock line is always input. Via the
data line, data is transmitted and received, so this pin must
be input/output. The SCL and SDA lines are driven by
open-drain stages and pull-up resistors. When a logic 0 is
applied, the bus is set to ground level via the output
buffers. When a logic 1 is applied, the output buffer
switches to 3-state and the pull-up resistors pull the bus up
to +5 V.
All byte transfers are acknowledged from the receiving
device. The data transfer is aborted by sending a STOP
condition, when SDA changes from LOW to HIGH when
SCL is HIGH (see Fig.9).
If a new address has to be read or written, it is possible to
send a new START condition without a preceding STOP
condition. In this case the bus is still occupied by the
master, and it can initiate a new data transfer. This is
useful for read activities, where at first the register address
must be sent in write mode and after that a read command
will be sent to read data from this and following addresses.
Data transfer changes on SDA are allowed only when SCL
is LOW. Data is sampled on the positive edge of SCL.
In Idle state the output buffers are in 3-state, and the bus
is HIGH. A data transfer must be initiated by an I2C-bus
master device. This is done by sending a START condition
when SDA changes from HIGH to LOW when SCL is HIGH
(see Fig.8).
handbook,SCL
full pagewidth
A6
SDA
A5
A4
A3
A2
A1
A0
R/W
ACK
R7
R6
R5
MHB248
acknowledge
START condition
Fig.8 Start of a data transfer.
handbook, full
pagewidth
SCL
SDA
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
acknowledge/
not acknowledge
A/A
STOP condition
MHB249
Fig.9 End of a data transfer.
1999 May 11
19
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
The missing even line in an odd frame will be calculated by
interpolation from the corresponding even lines in the even
fields before and after. The odd line handling is done in the
same way.
If the data transfer was a read transfer and the master was
receiver, the master must not generate an acknowledge
before the STOP condition.
7.8
De-interlacing algorithms
7.9
The SAA6721E features several de-interlacing algorithms
for processing interlaced video data. Depending on the
algorithm different memory bandwidths and field
memories are needed.
7.8.1
The SAA6721E features different scaling engines for up
and downscaling, for both horizontal and vertical
processing. The horizontal scaling engines are
independent from each other. The vertical scaling engines
share the line buffer, so they cannot operate in parallel.
STATIC MESH MODE
This mode allows de-interlacing without any image
processing and filtering. A field store for 2 fields is
necessary. De-interlacing is achieved by simply putting
lines together in the right order from the odd and even
fields in the field store and generating the output frame.
7.8.2
7.9.1
UPSCALING
The upscaling engine is used for enlarging the incoming
video frames. It can be used for zooming both RGB and
YUV video data. The magnification can be programmed
individually for horizontal and vertical scaling.
The maximum scaling factor for both directions is 64.
SPATIAL FILTERING
The implemented filter algorithm (see Fig.10) uses
interpolation with pixel enhancement, based on a free
programmable transition function. It is therefore possible
to define the transition between two calculated pixels to
obtain different sharpness characteristics. This transition
function must be defined in the 7 bits × 64 look-up table,
with a number ranging from 0 to 64. Different functions can
be programmed for horizontal and vertical scaling.
The spatial filtering mode requires 2 field memories, but
only one memory is used at a time. For the calculation of
the whole frame from an odd field, the missing even lines
are interpolated from the odd lines before and after.
Processing of the even field is done in the same way.
7.8.3
Scaling algorithm
TEMPORAL FILTERING
The filtering algorithm needs 4 field memories and will be
applied temporally to subsequent fields.
intensity of
output pixel O
handbook, full pagewidth
A
B
MHB250
100% A,
0% B
(3)
(2)
(1)
O
0% A,
100% B
100% A,
0% B
0% A,
100% B
(1) The linear interpolation results in smoothing the sharp edges of the original picture if a pixel must be calculated.
(2) Some kind of 1⁄x function results in sharper edges, because of the smaller transition interval.
(3) Phase correct pixel repetition can be done with this function.
Fig.10 Interpolation function definition.
1999 May 11
20
ratio between
input pixels A, B
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.9.2
SAA6721E
After writing to all registers the internal reset can be
released. There are some registers (mainly offset
counters) that can be changed during data processing
without an internal reset. All accesses to the on screen
display can be done during data processing.
DOWNSCALING
The downscaling engine is used for reducing the incoming
RGB data stream, i.e. for displaying high resolution input
frames on panels with a smaller resolution. The scaling
ratio can be programmed independently for both horizontal
and vertical downscaling units. The algorithm uses pixel
accumulation, achieving a minimum scaling factor of 1⁄64.
Table 6
I2C-bus device address
MSB
8
SYSTEM DESCRIPTION
8.1
0
LSB
1
1
1
0
1
SAD
R/W
Programming registers
Bit SAD = 0 the address is 74H, while bit SAD = 1 the
address is 76H.
The SAA6721E is a highly integrated device with many
features. To get the desired functionality and performance
it must be programmed correctly. In general, before
programming, the device must be switched to the internal
reset state to prevent unwanted functions while changing
the registers.
Table 7
Table 7 shows the programming model.
Programming register overview
ADDRESS R/W
D7
D6
D5
D4
D3
D2
D1
D0
State
0
R
reserved
1
R
reserved
2
3
R/W iic_test_register[7 to 0]
R
intr
RGB mode detection
4
R
5
R
6
R
7
R
8
R
pos_
vsync
pos_
hsync
no_
vsync
v_lines[7 to 0]
v_lines[10 to 8]
h_clocks[7 to 0]
h_clocks[11 to 8]
RGB auto-adjustment
9
W
10
W
11
W
12
W
13
W
ref_colour[7 to 0]
14
R
ref_pixel_red[7 to 0]
15
R
ref_pixel_green[7 to 0]
16
R
ref_pixel_blue[7 to 0]
17
R
black_lines[7 to 0]
18
R
black_pixels[7 to 0]
1999 May 11
ref_line[7 to 0]
ref_line[10 to 8]
ref_pixel[7 to 0]
ref_pixel[11 to 8]
21
no_
hsync
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
19
R
20
R
21
R
22
R
23
R
D7
D6
SAA6721E
D5
D4
D3
D2
D1
D0
black_
pixels[8]
non_black_lines[7 to 0]
non_black_lines[10 to 8]
non_black_pixels[7 to 0]
non_black_pixels[11 to 8]
General configuration
24
W
25
W
intr_clear
single_
no_
adc_mode memory_
mode
memory_
init
reset_
reset_
input_path memory_
path
reset_
proc_path
yuv_clk_
mux
csm_
bypass
frc_on
power_
down
pre_div_
half_clock
post_div_
half_clock
pll_enable pll_pclk
blank_
screen
Clock distribution
26
W
por_mclk
pre_div_
enable
post_div_
enable
27
W
pre_div_clock_p_high[3 to 0]
pre_div_clock_p_low[3 to 0]
28
W
pre_div_clock_n_high[3 to 0]
pre_div_clock_n_low[3 to 0]
29
W
30
W
post_div_clock_p_high[3 to 0]
post_div_clock_p_low[3 to 0]
31
W
post_div_clock_n_high[3 to 0]
post_div_clock_n_low[3 to 0]
32
W
pll_mclk
pre_div_clock_n_offs[3 to 0]
post_div_clock_n_offs[3 to 0]
Input interface
33
W
34
W
35
W
36
W
37
W
38
W
39
W
40
W
41
W
42
W
43
W
clamp_on[7 to 0]
44
W
clamp_off[7 to 0]
45
W
gainc_on_delay[7 to 0]
46
W
gainc_off_delay[7 to 0]
1999 May 11
rgb_interl_ in_form_
on
on
field_
reverse
rgb_proc_ adc_
on
sample_
seq
gainc_pol
clamp_pol vs_pol
yuv_field_mode
[1 and 0]
yuv_input_mode
[1 and 0]
yuv_href_
pol
v_offset[7 to 0]
v_offset[10 to 8]
h_offset[7 to 0]
h_offset[11 to 8]
v_length[7 to 0]
v_length[10 to 8]
h_length[7 to 0]
h_length[11 to 8]
22
hs_pol
yuv_cref_
pol
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
D7
D6
SAA6721E
D5
D4
D3
D2
D1
D0
blue_prog
colour_
correction
_on
Colour correction
47
W
red_prog
48
W
colour_index[7 to 0]
49
W(1)
colour_value[7 to 0]
green_
prog
Memory interface/de-interlacing unit
50
W
yuv422_
mode
data_width[1 and 0]
deint_mode[1 and 0]
51
W
52
W
SDRAM_burst_length_code[2 to 0]
SDRAM_burst_length[3 to 0]
53
W
CAS_latency[2 to 0]
t_RCD[3 to 0]
54
W
t_RRD[3 to 0]
t_RP[3 to 0]
55
W
t_WR[3 to 0]
t_RC[3 to 0]
56
W
field1_row[7 to 0]
57
W
58
W
field1_column[7 to 0]
59
W
field2_row[7 to 0]
60
W
61
W
field2_column[7 to 0]
62
W
field3_row[7 to 0]
63
W
64
W
field3_column[7 to 0]
65
W
field4_row[7 to 0]
66
W
67
W
field4_column[7 to 0]
68
W
frame_length[7 to 0]
69
W
70
W
71
W
72
W
blank_colour_red[7 to 0]
73
W
blank_colour_green[7 to 0]
74
W
blank_colour_blue[7 to 0]
burst_seq_length[3 to 0]
field1_row[10 to 8]
field2_row[10 to 8]
field3_row[10 to 8]
field4_row[10 to 8]
frame_length[10 to 8]
line_length[7 to 0]
line_length[11 to 8]
Scaler
75
W
76
W
77
W
78
W
79
W
1999 May 11
down_v_
scaler_
mem
up_v_
up_h_
up_v_
coeff_prog coeff_prog scaler_on
up_h_
scaler_on
up_v_incr[7 to 0]
up_v_incr[11 to 8]
up_v_corr[6 to 0]
up_h_incr[7 to 0]
23
down_v_
scaler_on
down_h_
scaler_on
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
80
W
81
W
82
W
83
W
84
W
85
W
86
W
87
W(1)
D7
D6
SAA6721E
D5
D4
D3
D2
D1
D0
up_h_incr[11 to 8]
up_h_corr[6 to 0]
down_v_incr[5 to 0]
down_v_corr[6 to 0]
down_h_incr[5 to 0]
down_h_corr[6 to 0]
coeff_index[5 to 0]
coeff_value[6 to 0]
Panning unit
88
W
pic_v_offset[7 to 0]
89
W
90
W
91
W
92
W
93
W
94
W
95
W
96
W
border_colour_red[7 to 0]
97
W
border_colour_green[7 to 0]
98
W
border_colour_blue[7 to 0]
pic_v_offset[10 to 8]
pic_h_offset[7 to 0]
pic_h_offset[11 to 8]
out_v_size[7 to 0]
out_v_size[10 to 8]
out_h_size[7 to 1]
0
out_h_size[11 to 8]
OSD overlay port
99
W
ovl_clk_
pol
ovl_act_
pol
100
W
ovl_hs_start[7 to 0]
101
W
102
W
103
W
104
W
ovl_hs_latency[7 to 0]
105
W
ovl_h_length[7 to 0]
106
W
107
W
108
W
109
W
110
W
ovl_vs_
pol
clk_
gating_on
sample_
edge
ovl_
syncs_
active
ovl_hs_start[10 to 8]
ovl_hs_length[7 to 0]
ovl_hs_length[10 to 8]
ovl_h_length[10 to 8]
ovl_v_offset[7 to 0]
ovl_v_offset[10 to 8]
ovl_v_length[7 to 0]
ovl_v_length[10 to 8]
111
W
112
W
113
W
ovl_colour0_red[7 to 0]
114
W
ovl_colour0_green[7 to 0]
115
W
ovl_colour0_blue[7 to 0]
1999 May 11
ovl_hs_
pol
ovl_vs_start[7 to 0]
ovl_vs_start[10 to 8]
24
ovl_
insert_
active
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
D7
D6
SAA6721E
D5
116
W
ovl_colour1_red[7 to 0]
117
W
ovl_colour1_green[7 to 0]
118
W
ovl_colour1_blue[7 to 0]
119
W
ovl_colour2_red[7 to 0]
120
W
ovl_colour2_green[7 to 0]
121
W
ovl_colour2_blue[7 to 0]
122
W
ovl_colour3_red[7 to 0]
123
W
ovl_colour3_green[7 to 0]
124
W
ovl_colour3_blue[7 to 0]
125
W
ovl_colour4_red[7 to 0]
126
W
ovl_colour4_green[7 to 0]
127
W
ovl_colour4_blue[7 to 0]
128
W
ovl_colour5_red[7 to 0]
129
W
ovl_colour5_green[7 to 0]
130
W
ovl_colour5_blue[7 to 0]
131
W
ovl_colour6_red[7 to 0]
132
W
ovl_colour6_green[7 to 0]
133
W
ovl_colour6_blue[7 to 0]
134
W
ovl_colour7_red[7 to 0]
135
W
ovl_colour7_green[7 to 0]
136
W
ovl_colour7_blue[7 to 0]
D4
D3
D2
D1
D0
On screen display
137
W
138
W
139
W
140
W
141
W
142
W
osd_v_size[5 to 0]
143
W
osd_h_size[5 to 0]
144
W
osd_fg_colour0_red[7 to 0]
145
W
osd_fg_colour0_green[7 to 0]
146
W
osd_fg_colour0_blue[7 to 0]
147
W
osd_fg_colour1_red[7 to 0]
148
W
osd_fg_colour1_green[7 to 0]
149
W
osd_fg_colour1_blue[7 to 0]
150
W
osd_fg_colour2_red[7 to 0]
151
W
osd_fg_colour2_green[7 to 0]
152
W
osd_fg_colour2_blue[7 to 0]
153
W
osd_fg_colour3_red[7 to 0]
1999 May 11
zoom2
char_size
osd_v_offset[7 to 0]
osd_v_offset[10 to 8]
osd_h_offset[7 to 0]
osd_h_offset[11 to 8]
25
osd_
active
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
D7
D6
D5
154
W
osd_fg_colour3_green[7 to 0]
155
W
osd_fg_colour3_blue[7 to 0]
156
W
osd_fg_colour4_red[7 to 0]
157
W
osd_fg_colour4_green[7 to 0]
158
W
osd_fg_colour4_blue[7 to 0]
159
W
osd_fg_colour5_red[7 to 0]
160
W
osd_fg_colour5_green[7 to 0]
161
W
osd_fg_colour5_blue[7 to 0]
162
W
osd_fg_colour6_red[7 to 0]
163
W
osd_fg_colour6_green[7 to 0]
164
W
osd_fg_colour6_blue[7 to 0]
165
W
osd_fg_colour7_red[7 to 0]
166
W
osd_fg_colour7_green[7 to 0]
167
W
osd_fg_colour7_blue[7 to 0]
168
W
osd_bg_colour0_red[7 to 0]
169
W
osd_bg_colour0_green[7 to 0]
170
W
osd_bg_colour0_blue[7 to 0]
171
W
osd_bg_colour1_red[7 to 0]
172
W
osd_bg_colour1_green[7 to 0]
173
W
osd_bg_colour1_blue[7 to 0]
174
W
osd_bg_colour2_red[7 to 0]
175
W
osd_bg_colour2_green[7 to 0]
176
W
osd_bg_colour2_blue[7 to 0]
177
W
osd_bg_colour3_red[7 to 0]
178
W
osd_bg_colour3_green[7 to 0]
179
W
osd_bg_colour3_blue[7 to 0]
180
W
osd_bg_colour4_red[7 to 0]
181
W
osd_bg_colour4_green[7 to 0]
182
W
osd_bg_colour4_blue[7 to 0]
183
W
osd_bg_colour5_red[7 to 0]
184
W
osd_bg_colour5_green[7 to 0]
185
W
osd_bg_colour5_blue[7 to 0]
186
W
osd_bg_colour6_red[7 to 0]
187
W
osd_bg_colour6_green[7 to 0]
188
W
osd_bg_colour6_blue[7 to 0]
189
W
osd_bg_colour7_red[7 to 0]
190
W
osd_bg_colour7_green[7 to 0]
191
W
osd_bg_colour7_blue[7 to 0]
192
W
osd_fg_
colour7_
transp
1999 May 11
osd_fg_
colour6_
transp
SAA6721E
osd_fg_
colour5_
transp
D4
osd_fg_
colour4_
transp
26
D3
osd_fg_
colour3_
transp
D2
osd_fg_
colour2_
transp
D1
osd_fg_
colour1_
transp
D0
osd_fg_
colour0_
transp
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
D7
D6
SAA6721E
D5
D4
D3
D2
D1
D0
193
W
osd_fg_
colour7_
alpha
osd_fg_
colour6_
alpha
osd_fg_
colour5_
alpha
osd_fg_
colour4_
alpha
osd_fg_
colour3_
alpha
osd_fg_
colour2_
alpha
osd_fg_
colour1_
alpha
osd_fg_
colour0_
alpha
194
W
osd_bg_
colour7_
transp
osd_bg_
colour6_
transp
osd_bg_
colour5_
transp
osd_bg_
colour4_
transp
osd_bg_
colour3_
transp
osd_bg_
colour2_
transp
osd_bg_
colour1_
transp
osd_bg_
colour0_
transp
195
W
osd_bg_
colour7_
alpha
osd_bg_
colour6_
alpha
osd_bg_
colour5_
alpha
osd_bg_
colour4_
alpha
osd_bg_
colour3_
alpha
osd_bg_
colour2_
alpha
osd_bg_
colour1_
alpha
osd_bg_
colour0_
alpha
On screen display window
196
W
cursor_row[5 to 0]
197
W
cursor_column[5 to 0]
198
W
199
W(1)
char_appearance
[1 and 0]
char_bg_colour[2 to 0]
char_fg_colour[2 to 0]
char_code[6 to 0]
On screen display character matrix
200
201
W
char_code[6 to 0]
W(1) char_def[7 to 0]
TFT display interface
202
W
203
W
line_sync
204
W
h_len_blank[7 to 0]
205
W
206
W
207
W
208
W
209
W
210
W
211
W
212
W
213
W
214
W
215
W
216
W
217
W
218
W
219
W
220
W
221
W
1999 May 11
sync_de_
act
out_if_
enable
vsync_pol
hsync_pol de_pol
clk_pol
single_
pixel_
output
blank_tft
sync_
mode
border_
ctrl
active_ctrl
blank_ctrl
h_len_blank[10 to 8]
h_len_border[7 to 0]
h_len_border[10 to 8]
h_len_active[7 to 0]
h_len_active[10 to 8]
v_end[7 to 0]
v_end[10 to 8]
v_start[7 to 0]
v_start[10 to 8]
v_active[7 to 0]
v_active[10 to 8]
h_vs_start[7 to 0]
h_vs_start[10 to 8]
h_vs_end[7 to 0]
h_vs_end[10 to 8]
h_hs_start[7 to 0]
h_hs_start[10 to 8]
27
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
ADDRESS R/W
222
W
223
W
224
W
225
W
226
W
227
W
228
W
229
W
230
W
231
W
232
W
233
W
D7
D6
SAA6721E
D5
D4
D3
D2
D1
D0
h_hs_end[7 to 0]
h_hs_end[10 to 8]
h_de_start[7 to 0]
h_de_start[10 to 8]
h_de_end[7 to 0]
h_de_end[10 to 8]
h_active_start[7 to 0]
h_active_start[10 to 8]
v_vs_end[7 to 0]
v_vs_end[10 to 8]
h_max_len[7 to 0]
h_max_len[10 to 8]
Note
1. Register does not work with register address auto-increment, but with incrementing the address on which the
operation is performed.
Table 8
Detailed description of programming registers
NAME
SUBADDRESS
R/W
DATA
State
IIC TEST REGISTER
IIC test register
2
R/W D7 to D0
STATE REGISTER
Interrupt state
3
R
D0
Interrupt active
logic 0
Interrupt not active
logic 1
RGB mode detection
SYNC DETECT REGISTER
Hsync presence
4
R
D0
Hsync present
logic 0
Hsync not present
logic 1
Vsync presence
D1
Vsync present
logic 0
Vsync not present
logic 1
Hsync polarity
D2
Negative Hsync
logic 0
Positive Hsync
logic 1
Vsync polarity
D3
Negative Vsync
logic 0
Positive Vsync
logic 1
1999 May 11
28
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
5 and 6
R
D10 to D0
7 and 8
R
D11 to D0
9 and 10
W
D10 to D0
11 and 12
W
D11 to D0
13
W
D7 to D0
14
R
D7 to D0
15
R
D7 to D0
16
R
D7 to D0
17
R
D7 to D0
18 and 19
R
D8 to D0
20 and 21
R
D10 to D0
22 and 23
R
D11 to D0
VERTICAL FRAME RESOLUTION
Number of lines between two Vsyncs
HORIZONTAL FRAME RESOLUTION
Number of clocks between two Hsyncs
RGB auto adjustment
REFERENCE LINE POSITION
Reference line for auto adjustment measurements
REFERENCE PIXEL POSITION
Reference pixel for auto adjustment measurements
REFERENCE COLOUR
Colour for selecting black or non-black pixels
REFERENCE PIXEL COLOUR RED COMPONENT
Red colour component of reference pixel
REFERENCE PIXEL COLOUR GREEN COMPONENT
Green colour component of reference pixel
REFERENCE PIXEL COLOUR BLUE COMPONENT
Blue colour component of reference pixel
BLACK LINES COUNTER
Number of black lines after Vsync
BLACK PIXELS COUNTER
Number of black pixels after Hsync
NON-BLACK LINES COUNTER
Number of non-black lines after Vsync
NON-BLACK PIXELS COUNTER
Number of non-black pixels after Hsync
1999 May 11
29
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
24
W
DATA
General configuration
CONFIGURATION REGISTER 1
Processing reset state
Processing path not in reset state
D0
logic 0
Processing path in reset state
logic 1
Memory reset state
D1
Memory path not in reset state
logic 0
Memory path in reset state
logic 1
Input reset state
D2
Input path not in reset state
logic 0
Input path in reset state
logic 1
External memory initialization
D3
No external memory initialization
logic 0
Start external memory initialization
logic 1
External memory configuration
D4
External memory present
logic 0
No external memory present
logic 1
External ADC configuration
D5
2 ADCs connected
logic 0
1 ADC connected
logic 1
Interrupt acknowledge
D6
No acknowledge
logic 0
Reset interrupt output to logic 1
logic 1
CONFIGURATION REGISTER 2
Output interface Power-down mode
25
W
D0
Normal processing
logic 0
All outputs of output interface at LOW level
logic 1
Blank screen
D1
Normal data processing
logic 0
Blank screen generation after memory interface
logic 1
Output temporal dithering
D2
No temporal dithering of output data stream
logic 0
Temporal dithering of output data
logic 1
Colour space conversion matrix
D3
Conversion YUV to RGB enabled
logic 0
Straight RGB processing enabled
logic 1
YUV processing clock multiplexer
D4
Clock will be applied at pin VCLK
logic 0
Clock will be applied at pin MCLKI
logic 1
1999 May 11
30
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
26
W
DATA
Clock distribution
CLOCK MULTIPLEXING
Memory clock generation
Memory clock is taken from pin MCLKI
Memory clock is
1⁄
2
logic 0
PLL clock
logic 1
Panel clock generation
D1
Panel clock is equal system clock
logic 0
Panel clock is generated by PLL clock and post-divider
logic 1
PLL activation
D2
PLL disabled
logic 0
PLL enabled
logic 1
PLL post-divider precision
1⁄
2
clock precision disabled
1⁄
2
clock precision enabled
D3
logic 0
logic 1
PLL pre-divider precision
1⁄
2
clock precision disabled
1⁄
2
clock precision enabled
D0
D4
logic 0
logic 1
PLL post-divider activation
D5
PLL post-divider disabled
logic 0
PLL post-divider enabled
logic 1
PLL pre-divider activation
D6
PLL pre-divider disabled
logic 0
PLL pre-divider enabled
logic 1
External memory clock multiplexer
D7
Enable memory clock
logic 0
Use system clock as external memory clock
logic 1
PRE-DIVIDER P-COUNTER
Pre-divider p-counter programming
27
W
D7 to D0
28
W
D7 to D0
29
W
D3 to D0
30
W
D7 to D0
31
W
D7 to D0
32
W
D3 to D0
PRE-DIVIDER N-COUNTER
Pre-divider n-counter programming
PRE-DIVIDER N-OFFSET
Pre-divider n-counter offset programming
POST-DIVIDER P-COUNTER
Post-divider p-counter programming
POST-DIVIDER N-COUNTER
Post-divider n-counter programming
POST-DIVIDER N-OFFSET
Post-divider n-counter offset programming
1999 May 11
31
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
33
W
DATA
Input interface
GENERAL PROGRAMMING
Hsync polarity
Hsync is active LOW, line starts at rising edge of pin VHS
Hsync is active HIGH, line starts at falling edge of pin VHS
Vsync polarity
D0
logic 0
logic 1
D1
Vsync is active LOW, line starts at rising edge of pin VVS
Vsync is active HIGH, line starts at falling edge of pin VVS
Clamp pulse polarity
logic 0
logic 1
D2
Pulse is active LOW
logic 0
Pulse is active HIGH
logic 1
Gain correction pulse polarity
D3
Pulse is active LOW
logic 0
Pulse is active HIGH
logic 1
ADC sample sequence
D4
ADC 0 is sampled first after Hsync (video input port A, B, C)
ADC 1 is sampled first after Hsync (video input port D, E, F)
RGB/YUV processing mode
logic 0
logic 1
D5
YUV processing enabled
logic 0
RGB processing enabled
logic 1
Input interface activation
D6
No data sampling
logic 0
Data sampling enabled
logic 1
Interlaced RGB mode
D7
Non-interlaced RGB processing
logic 0
Interlaced RGB processing
logic 1
1999 May 11
32
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
34
W
DATA
INTERLACED MODE PROGRAMMING
YUV CREF polarity
D0
YUV clock qualifier is active LOW
logic 0
YUV clock qualifier is active HIGH
logic 1
YUV HREF polarity
D1
Active data qualifier is active LOW
logic 0
Active data qualifier is active HIGH
logic 1
YUV format
D3 and D2
CCIR 656
D3 = 0 and D2 = 0
4 : 1 : 1 format
D3 = 0 and D2 = 1
4 : 2 : 2 format
D3 = 1 and D2 = 0
4 : 4 : 4 format
D3 = 1 and D2 = 1
YUV field sampling mode
D5 and D4
All incoming frames are captured
D5 = 0 and D4 = 0
Capture alternating fields only
D5 = 0 and D4 = 1
Capture odd fields only
D5 = 1 and D4 = 0
Capture even fields only
D5 = 1 and D4 = 1
Field reverse flag
D6
Keep original odd field identification
logic 0
Change field identification
logic 1
VERTICAL SAMPLE OFFSET
Vertical sample offset from Vsync
35 and 36
W
D10 to D0
37 and 38
W
D11 to D0
39 and 40
W
D10 to D0
41 and 42
W
D11 to D0
43
W
D7 to D0
44
W
D7 to D0
45
W
D7 to D0
46
W
D7 to D0
HORIZONTAL SAMPLE OFFSET
Horizontal sample offset from Hsync
VERTICAL SAMPLE LENGTH
Vertical sample window length
HORIZONTAL SAMPLE LENGTH
Horizontal sample window length
CLAMP PULSE START
Start of clamp pulse after active edge of Hsync
CLAMP PULSE END
End of clamp pulse after active edge of Hsync
GAIN CORRECTION PULSE START DELAY
Delay of start of GAINC pulse from first edge of Hsync
GAIN CORRECTION PULSE END DELAY
Delay of end of pulse GAINC from second edge of Hsync
1999 May 11
33
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
47
W
DATA
Colour correction
PROGRAMMING SELECTOR, ACTIVATION
Colour correction activation
Straight colour processing
D0
logic 0
Colour substitution enabled
logic 1
Blue component programming
D1
Red component correction colour writing disabled
logic 0
Red component correction colour writing enabled
logic 1
Green component programming
D2
Red component correction colour writing disabled
logic 0
Red component correction colour writing enabled
logic 1
Red component programming
D3
Red component correction colour writing disabled
logic 0
Red component correction colour writing enabled
logic 1
COLOUR INDEX FOR LOOK-UP TABLE WRITING
Colour component look-up table index
48
W
D7 to D0
49
W
D7 to D0
50
W
D1 and D0
COLOUR VALUE FOR LOOK-UP TABLE WRITING
Colour component substitution value
Memory interface/de-interlacing unit
GENERAL CONFIGURATION
De-interlacing mode
No de-interlacing
D1 = 0 and D0 = 0
De-interlacing without filtering
D1 = 0 and D0 = 1
De-interlacing with spatial filtering
D1 = 1 and D0 = 0
De-interlacing with temporal filtering
D1 = 1 and D0 = 1
External memory data bus width
D3 and D2
32 bits (two 16-bit channels)
D3 = 0 and D2 = 0
48 bits (three 16-bit channels)
D3 = 0 and D2 = 1
64 bits (four 16-bit channels)
D3 = 1 and D2 = 0
do not use
D3 = 1 and D2 = 1
Internal data path width
D4
RGB and YUV 4 : 4 : 4 processing
logic 0
YUV 4 : 2 : 2, YUV 4 : 1 : 1 and CCIR 656 processing
logic 1
ACCESS BURST LENGTH
Number of bursts per read/write access to SDRAM
51
W
D3 to D0
52
W
D3 to D0
SDRAM BURST LENGTH
SDRAM burst length
SDRAM initialization code for burst length
1999 May 11
D6 to D4
34
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
53
W
DATA
SDRAM TIMING PARAMETER 1; SEE TABLE 14
Active to read or write delay (tRCD) in clocks
CAS latency (CL) in clocks
D3 to D0
D6 to D4
SDRAM TIMING PARAMETER 2; SEE TABLE 14
Precharge command period (tRP) in clocks
54
W
Active bank A to active band B command (tRRD) in clocks
D3 to D0
D7 to D4
SDRAM TIMING PARAMETER 3; SEE TABLE 14
Auto refresh, active command period (tRC) in clocks
55
W
Write recovery time (tWR) in clocks
D3 to D0
D7 to D4
FIELD 1 START ADDRESS (ROW)
Start address of field 1 in external SDRAM memory (row)
56 and 57
W
D10 to D0
58
W
D7 to D0
59 and 60
W
D10 to D0
61
W
D7 to D0
62 and 63
W
D10 to D0
64
W
D7 to D0
65 and 66
W
D10 to D0
67
W
D7 to D0
68 and 69
W
D10 to D0
70 and 71
W
D11 to D0
72
W
D7 to D0
73
W
D7 to D0
74
W
D7 to D0
FIELD 1 START ADDRESS (COLUMN)
Start address of field 1 in external SDRAM memory (column)
FIELD 2 START ADDRESS (ROW)
Start address of field 2 in external SDRAM memory (row)
FIELD 2 START ADDRESS (COLUMN)
Start address of field 2 in external SDRAM memory (column)
FIELD 3 START ADDRESS (ROW)
Start address of field 3 in external SDRAM memory (row)
FIELD 3 START ADDRESS (COLUMN)
Start address of field 3 in external SDRAM memory (column)
FIELD 4 START ADDRESS (ROW)
Start address of field 4 in external SDRAM memory (row)
FIELD 4 START ADDRESS (COLUMN)
Start address of field 4 in external SDRAM memory (column)
OUTPUT FRAME LENGTH
Vertical length of output frame after de-interlacing unit
OUTPUT LINE LENGTH
Horizontal length of output frame after de-interlacing unit
BLANK COLOUR RED COMPONENT DEFINITION
Red colour component for blank screen generation
BLANK COLOUR GREEN COMPONENT DEFINITION
Green colour component for blank screen generation
BLANK COLOUR BLUE COMPONENT DEFINITION
Blue colour component for blank screen generation
1999 May 11
35
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
75
W
DATA
Scaler
SCALER CONFIGURATION
Horizontal downscaler activation
Horizontal downscaler disabled
D0
logic 0
Horizontal downscaler enabled
logic 1
Vertical downscaler activation
D1
Vertical downscaler disabled
logic 0
Vertical downscaler enabled
logic 1
Horizontal upscaler activation
D2
Horizontal upscaler disabled
logic 0
Horizontal upscaler enabled
logic 1
Vertical upscaler activation
D3
Vertical upscaler disabled
logic 0
Vertical upscaler enabled
logic 1
Horizontal upscaling transition function programming
D4
Horizontal upscaling transition function writing disabled
logic 0
Horizontal upscaling transition function writing enabled
logic 1
Vertical upscaling transition function programming
D5
Vertical upscaling transition function writing disabled
logic 0
Vertical upscaling transition function writing enabled
logic 1
Line memory usage
D6
Line memory used by upscaling unit
logic 0
Line memory used by downscaling unit
logic 1
VERTICAL UPSCALE INCREMENT
Increment for vertical upscaling
76 and 77
W
D11 to D0
78
W
D6 to D0
79 and 80
W
D11 to D0
81
W
D6 to D0
82
W
D5 to D0
83
W
D6 to D0
84
W
D5 to D0
VERTICAL UPSCALE CORRECTION
Fraction of vertical upscaling increment (1⁄100)
HORIZONTAL UPSCALE INCREMENT
Increment for horizontal upscaling
HORIZONTAL UPSCALE CORRECTION
Fraction of horizontal upscaling increment (1⁄100)
VERTICAL DOWNSCALE INCREMENT
Increment for vertical downscaling
VERTICAL DOWNSCALE CORRECTION
Fraction of vertical downscaling increment (1⁄100)
HORIZONTAL DOWNSCALE INCREMENT
Increment for horizontal downscaling
1999 May 11
36
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
85
W
D6 to D0
86
W
D5 to D0
87
W
D6 to D0
88 and 89
W
D10 to D0
90 and 91
W
D11 to D0
92 and 93
W
D10 to D0
94 and 95
W
D11 to D0
96
W
D7 to D0
97
W
D7 to D0
98
W
D7 to D0
HORIZONTAL DOWNSCALE CORRECTION
Fraction of horizontal downscaling increment (1⁄100)
INDEX FOR COEFFICIENT TABLE WRITING
Transition function look-up table index
COEFFICIENT VALUE FOR LOOK-UP TABLE WRITING
Values of transition function
Panning unit
VERTICAL PICTURE OFFSET
Vertical input picture offset inside the output frame
HORIZONTAL PICTURE OFFSET
Horizontal input picture offset inside the output frame
VERTICAL OUTPUT FRAME LENGTH
Vertical output frame length
HORIZONTAL OUTPUT FRAME LENGTH
Horizontal output frame length
BORDER COLOUR RED COMPONENT DEFINITION
Red colour component for border generation
BORDER COLOUR GREEN COMPONENT DEFINITION
Green colour component for border generation
BORDER COLOUR BLUE COMPONENT DEFINITION
Blue colour component for border generation
1999 May 11
37
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
99
W
DATA
OSD overlay port
GENERAL CONFIGURATION
OSD overlay port activation
Overlay information will not be inserted into data stream
D0
logic 0
Overlay information will be inserted into data stream
logic 1
Sync pulse generation
D1
No sync pulses will be generated
logic 0
Sync pulses will be generated
logic 1
Clock edge for sampling
D2
Data sampling at falling edge of clock at pin OVCLK
logic 0
Data sampling at rising edge of clock at pin OVCLK
logic 1
Clock gating
D3
OVCLK always enabled
logic 0
OVCLK enabled only during internal active video processing
logic 1
Horizontal sync polarity
D4
Active LOW horizontal sync pulse at pin OVHS
logic 0
Active HIGH horizontal sync pulse at pin OVHS
logic 1
Vertical sync polarity
D5
Active LOW vertical sync pulse at pin OVVS
logic 0
Active HIGH vertical sync pulse at pin OVVS
logic 1
Overlay port active pixel qualifier polarity
D6
Active LOW qualifier signal at pin OVACT
logic 0
Active HIGH qualifier signal at pin OVACT
logic 1
Overlay port clock polarity
D7
Sync pulse change with respect to falling edge at pin OVCLK
logic 0
Sync pulse change with respect to rising edge at pin OVCLK
logic 1
OVERLAY HORIZONTAL SYNC START
Start of horizontal sync pulse with respect to left frame border
100 and 101
W
D10 to D0
102 and 103
W
D10 to D0
104
W
D7 to D0
105 and 106
W
D10 to D0
107 and 108
W
D10 to D0
109 and 110
W
D10 to D0
OVERLAY HORIZONTAL SYNC LENGTH
Length of horizontal sync pulse
OVERLAY HORIZONTAL SYNC LATENCY
Delay between start of horizontal sync and valid overlay data
OVERLAY WINDOW HORIZONTAL LENGTH
Horizontal length of overlay region
OVERLAY WINDOW VERTICAL OFFSET
Vertical offset of overlay region
OVERLAY WINDOW VERTICAL LENGTH
Vertical length of overlay region
1999 May 11
38
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
111 and 112
W
D10 to D0
113, 116, 119,
122, 125, 128,
131 and 134
W
D7 to D0
114, 117, 120,
123, 126, 129,
132 and 135
W
D7 to D0
115, 118, 121,
124, 127, 130,
133 and 136
W
D7 to D0
137
W
D0
OVERLAY VERTICAL SYNC START
Start of vertical sync pulse with respect to top frame border
COLOUR 0 TO 7 RED COMPONENT DEFINITION
Red colour component for overlay colour 0 to 7
COLOUR 0 TO 7 GREEN COMPONENT DEFINITION
Green colour component for overlay colour 0 to 7
COLOUR 0 TO 7 BLUE COMPONENT DEFINITION
Blue colour component for overlay colour 0 to 7
On screen display
GENERAL CONFIGURATION
OSD activation
OSD is not visible
logic 0
OSD is visible
logic 1
OSD character size
D1
12 × 16 character matrix
logic 0
24 × 24 character matrix
logic 1
OSD zoom
D2
No zooming of OSD window
logic 0
Zoom by 2 of OSD window
logic 1
OSD WINDOW VERTICAL OFFSET
Vertical offset of OSD window from left frame border in pixel
138 and 139
W
D10 to D0
140 and 141
W
D11 to D0
142
W
D5 to D0
143
W
D5 to D0
144, 147, 150,
153, 156, 159,
162 and 165
W
D7 to D0
OSD WINDOW HORIZONTAL OFFSET
Horizontal offset of OSD window from top frame border in pixel
OSD WINDOW VERTICAL SIZE
Vertical size of OSD window in characters
OSD WINDOW HORIZONTAL SIZE
Horizontal size of OSD window in characters
FOREGROUND COLOUR 0 TO 7 RED COMPONENT DEFINITION
Red colour component for foreground colour 0 to 7
1999 May 11
39
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
145, 148, 151,
154, 157, 160,
163 and 166
W
D7 to D0
146, 149, 152,
155, 158, 161,
164 and 167
W
D7 to D0
168, 171, 174,
177, 180, 183,
186 and 189
W
D7 to D0
169, 172, 175,
178, 181, 184,
187 and 190
W
D7 to D0
170, 173, 176,
179, 182, 185,
188 and 191
W
D7 to D0
192
W
D7 to D0
FOREGROUND COLOUR 0 TO 7 GREEN COMPONENT DEFINITION
Green colour component for foreground colour 0 to 7
FOREGROUND COLOUR 0 TO 7 BLUE COMPONENT DEFINITION
Blue colour component for foreground colour 0 to 7
BACKGROUND COLOUR 0 TO 7 RED COMPONENT DEFINITION
Red colour component for background colour 0 to 7
BACKGROUND COLOUR 0 TO 7 GREEN COMPONENT DEFINITION
Green colour component for background colour 0 to 7
BACKGROUND COLOUR 0 TO 7 BLUE COMPONENT DEFINITION
Blue colour component for background colour 0 to 7
FOREGROUND TRANSPARENT COLOUR DEFINITION
Foreground colour transparency
Foreground colour is not transparent
logic 0
Foreground colour is transparent
logic 1
FOREGROUND ALPHA BLENDING COLOUR DEFINITION
Foreground colour alpha blending
193
W
D7 to D0
Foreground colour is not alpha blendable
logic 0
Foreground colour is alpha blendable
logic 1
BACKGROUND TRANSPARENT COLOUR DEFINITION
Background colour transparency
194
W
D7 to D0
Background colour is not transparent
logic 0
Background colour is transparent
logic 1
BACKGROUND ALPHA BLENDING COLOUR DEFINITION
Background colour alpha blending
195
W
D7 to D0
Background colour is not alpha blendable
logic 0
Background colour is alpha blendable
logic 1
1999 May 11
40
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
196
W
D5 to D0
197
W
D5 to D0
198
W
On screen display window
CURSOR POSITION 1
Cursor row
CURSOR POSITION 2
Cursor column
CHARACTER APPEARANCE
Foreground colour code
D2 to D0
Background colour code
D5 to D3
Character appearance
D7 and D6
Picture information will be overwritten by OSD data
D7 = 0 and D6 = 0
Transparency of OSD transparent colours
D7 = 0 and D6 = 1
1 : 1 alpha blending of OSD alpha colours
D7 = 1 and D6 = 0
1 : 2 alpha blending of OSD alpha colours
D7 = 1 and D6 = 1
CHARACTER CODE
Code of character to be placed at cursor position
199
W
D6 to D0
200
W
D6 to D0
201
W
D7 to D0
202
W
D0
On screen display character matrix
CHARACTER CODE
Code of character to be defined
CHARACTER PATTERN
Character definition pattern
TFT display interface
GENERAL CONFIGURATION 1
Output width
Double pixel output (48 bits)
logic 0
Single pixel output (24 bits)
logic 1
Output clock polarity
D1
Data output with respect to falling edge of pin PCLK
logic 0
Data output with respect to rising edge of pin PCLK
logic 1
Data qualifier polarity
D2
Active LOW pin PDE
logic 0
Active HIGH pin PDE
logic 1
Horizontal sync polarity
D3
Active LOW horizontal sync at pin PHS
logic 0
Active HIGH horizontal sync at pin PHS
logic 1
Vertical sync polarity
D4
Active LOW vertical sync at pin PVS
logic 0
Active HIGH vertical sync at pin PVS
logic 1
1999 May 11
41
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
203
W
DATA
GENERAL CONFIGURATION 2
Line length controlling in active video region
D0
Line length controlling disabled
logic 0
Line length controlling enabled
logic 1
Line length controlling in border region
D1
Line length controlling disabled
logic 0
Line length controlling enabled
logic 1
Line length controlling in top blanking region
D2
Line length controlling disabled
logic 0
Line length controlling enabled
logic 1
Output interface mode
D3
Free running output interface timing (external SDRAM required)
logic 0
Synchronous output interface timing (without external SDRAM)
logic 1
Blanking mode
D4
Normal operating mode
logic 0
All data outputs are at LOW level (black colour)
logic 1
Output interface enabling
D5
Output interface disabled, no data processing
logic 0
Output interface enabled, normal data processing
logic 1
Data qualifier generation mode
D6
Disable pulse generation at pin PDE during vertical syncs
logic 0
Enable pulse generation at pin PDE during vertical syncs
logic 1
Line synchronization
D7
Normal mode
logic 0
Do not use
logic 1
HORIZONTAL LINE LENGTH IN BLANKING REGION
Horizontal line length in blanking region
204 and 205
W
D10 to D0
206 and 207
W
D10 to D0
208 and 209
W
D10 to D0
210 and 211
W
D10 to D0
212 and 213
W
D10 to D0
214 and 215
W
D10 to D0
216 and 217
W
D10 to D0
HORIZONTAL LINE LENGTH IN BORDER REGION
Horizontal line length in border region
HORIZONTAL LINE LENGTH IN ACTIVE VIDEO REGION
Horizontal line length in active video region
VERTICAL FRAME END
Vertical frame length
VERTICAL BORDER REGION START
Vertical start of border region
VERTICAL ACTIVE VIDEO REGION START
Vertical start of active video region
HORIZONTAL DELAY OF START OF VERTICAL SYNC
Horizontal start delay of vertical sync pulse at pin PVS
1999 May 11
42
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME
SUBADDRESS
R/W
DATA
218 and 219
W
D10 to D0
220 and 221
W
D10 to D0
222 and 223
W
D10 to D0
224 and 225
W
D10 to D0
226 and 227
W
D10 to D0
228 and 229
W
D10 to D0
230 and 231
W
D10 to D0
232 and 233
W
D10 to D0
HORIZONTAL DELAY OF END OF VERTICAL SYNC
Horizontal end delay of vertical sync pulse at pin PVS
HORIZONTAL SYNC PULSE START
Start of horizontal sync pulse at pin PHS
HORIZONTAL SYNC PULSE END
End of horizontal sync pulse at pin PHS
DATA QUALIFIER START
Start of border region and horizontal data qualifier at pin PDE
DATA QUALIFIER END
End of border region and horizontal data qualifier at pin PDE
HORIZONTAL ACTIVE REGION START
Start of horizontal active video region
VERTICAL SYNC PULSE END
Vertical sync pulse end at pin PVS
MAXIMUM HORIZONTAL LINE LENGTH
Maximum reachable line length for length controlling
8.2
8.2.1
It is possible to drive the memory clock output directly
without the internal PLL via pin MCLKI. To achieve this the
programming flag pll_mclk must be set to logic 0.
The same is possible for the panel output clock. Therefore
the system clock CLK is used directly. The system clock is
controlled by pll_pclk which must be set to logic 0.
Clock management
CLOCK GENERATION AND MULTIPLEXING
For normal operation the SAA6721E uses two clock
inputs; pin VCLK and pin CLK. VCLK is used as the
sample clock provided by the external ADCs or decoder.
The frequency and the sample edges of this clock depend
on the number of ADCs connected, or on the video dot
clock:
• 1 ADC mode: maximum VCLK frequency is 150 MHz
• 2 ADC mode: maximum VCLK frequency is 75 MHz.
The clock from pin CLK is used as an internal reference,
and it is the source clock for the internal PLL. The memory
clock MCLKO and panel clock PCLK are derived from the
PLL (see Fig.11):
CLK
MCLKO = ----------- × 16
N
CLK 32
PCLK = ----------- × -----N
M
Where N = pre-divider ratio, M = post-divider ratio and
CLK
5 MHz ≤ ----------- ≤ 8 MHz
N
1999 May 11
43
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
MCLKI
MCLKO
CLK
÷2
PRE-DIVIDER
PLL
× 32
POST-DIVIDER
PCLK
MHB251
Fig.11 Clock generator.
8.2.2
CLOCK DIVIDER
The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval
from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.12 and Table 9.
Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must
be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and
post_div_enable.
handbook, full CLK
pagewidth
CLK/4
CLK/4.5
CLK/5
CLK/5.5
MHB252
Fig.12 Clock waveforms.
Table 9
Clock divider programming
RATIO
P-COUNTER
(HEX)
N-COUNTER
(HEX)
N-OFFSET
COUNTER (HEX)
HALF CLK
1.5
10
10
1
1
2.0
00
00
0
0
2.5
30
30
2
1
3.0
10
10
0
1
3.5
41
41
3
1
1999 May 11
44
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
RATIO
P-COUNTER
(HEX)
N-COUNTER
(HEX)
N-OFFSET
COUNTER (HEX)
HALF CLK
4.0
11
00
0
0
4.5
61
61
4
1
5.0
21
21
0
1
5.5
72
72
5
1
6.0
22
00
0
0
6.5
92
92
6
1
7.0
32
32
0
1
7.5
A3
A3
7
1
8.0
33
00
0
0
8.5
C3
C3
8
1
9.0
43
43
0
1
9.5
D4
D4
9
1
10.0
44
00
0
0
10.5
F4
F4
A
1
11.0
54
54
0
1
12.0
55
00
0
0
13.0
65
65
0
1
14.0
66
00
0
0
15.0
76
76
0
1
16.0
77
00
0
0
17.0
87
87
0
1
18.0
88
00
0
0
19.0
98
98
0
1
20.0
99
00
0
0
21.0
A9
A9
0
1
22.0
AA
00
0
0
23.0
BA
BA
0
1
24.0
BB
00
0
0
25.0
CB
CB
0
1
26.0
CC
00
0
0
27.0
DC
DC
0
1
28.0
DD
00
0
0
29.0
ED
ED
0
1
30.0
EE
00
0
0
31.0
FE
FE
0
1
32.0
FF
00
0
0
1999 May 11
45
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.3
8.3.1
SAA6721E
RGB/YUV input interface
Table 10 Clock relationships
SAMPLING MODE
NUMBER OF
ADCs
The input interface allows sampling of RGB or YUV data.
Because of that two different modes must be supported:
RGB data sampling and YUV data sampling. The flag
rgb_proc_on selects RGB mode sampling if asserted.
If the flag is not asserted YUV data is selected.
VCLK
SAMPLE EDGE
1
dot clock
positive
2
1⁄
both
2
dot clock
In single ADC mode, with each VCLK clock, a pixel must
be sampled from port A. In dual ADC mode, at each VCLK
clock edge, a pixel must be sampled alternating from
port A or B. The flag adc_sample_seq selects from which
port data sampling starts after the active edge of the
horizontal synchronization pulse.
Sampling of interlaced RGB data is enabled by
rgb_interl_on.
8.3.2
VCLK
RGB DATA SAMPLING
Sampling is done on the rising edge or on both edges of
VCLK depending on the number of ADCs.
8.3.3
The sample window is defined by v_offset, h_offset,
v_length, and h_length.
CLAMP PULSE GENERATION
The clamp pulse is generated with respect to half the dot
clock. The counters values responsible for switching the
clamp pulse on or off are clamp_on and clamp_off. Both
start counting from the second edge of VHS. The polarity
of CLAMP is given with clamp_pol.
The offset counters start counting from the second edge of
their reference signals, i.e. VVS for vertical offset and VHS
for horizontal offset. Figure 13 shows the horizontal offset.
The polarities of the sync signals are given with vs_pol and
hs_pol. The vertical sample offset is given in lines and the
horizontal offset is measured in pixels. The width of the
sample window is defined by the length counters.
The vertical width is measured in lines and the horizontal
width in pixels, but only even pixel numbers are allowed.
The sample clock for the ADCs is always VCLK, but in dual
ADC mode this clock is half the pixel clock. Because of
that, in dual ADC mode, both clock edges are used to
sample data by the ADCs.
handbook, full pagewidth
VHS
h_length
h_offset
RGB data
1
n
2 3
4
5
0
MHB253
Fig.13 RGB data sampling.
1999 May 11
46
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.3.4
SAA6721E
GAIN CORRECTION PULSE GENERATION
The GAINC signal is the delayed horizontal sync pulse (VHS). It is delayed with respect to half the dot clock. The first
edge of VHS is delayed by gainc_on_delay and the second edge by gainc_off_delay (see Fig.14). The polarity is
programmed by gainc_pol.
handbook, full pagewidth
VHS
clamp_off
clamp_on
RGB data
GAINC
gainc_on_delay gainc_off_delay
CLAMP
MHB254
Fig.14 Gain adjustment and clamp pulse generation.
8.3.5
YUV DATA SAMPLING
Table 11 YUV input modes
In YUV mode the input interface receives digital YUV
encoded video data from an external video decoder.
The video data can be in 4 : 4 : 4, 4 : 2 : 2, 4 : 1 : 1, or
YUV 4 : 2 : 2 with CCIR 656 codes. For the 4 : 4 : 4,
4 : 2 : 2, and 4 : 1 : 1 formats the reference signals VVS
and VHS must be considered to identify the frames.
The polarity of these signals is programmable with vs_pol
and hs_pol. The region of valid video data and the start
point for the UV sequence is defined by HREF applied at
pin VPD6.
yuv_input_mode[1 and 0]
0
YUV 4 : 2 : 2 with
CCIR 656 codes
1
YUV 4 : 1 : 1
2
YUV 4 : 2 : 2
3
YUV 4 : 4 : 4
Data sampling occurs in relation to horizontal and vertical
offset counters, and horizontal and vertical length
counters. They are the same as for programming the RGB
input, v_offset, h_offset, v_length, and h_length. All offset
and length values are relative to the whole frame, and not
to odd or even fields (see Fig.15).
External reference signals are needed for sampling the
YUV 4 : 4 : 4, 4 : 2 : 2 and 4 : 1 : 1 data. If CCIR 656 data
is to be sampled, all external reference signals are
ignored, because their information is coded into the data
stream. All information about active video, blanking and
field ID is taken from the CCIR 656 codes. The selection of
the input format is done by yuv_input_mode as shown in
Table 11.
1999 May 11
DESCRIPTION
47
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
handbook, full pagewidth
SAA6721E
line number
odd line
1
314
2
315
3
316
4
317
5
318
6
319
7
320
8
321
9
322
10
323
11
324
12
325
even line
Vsync end
offset
0
1
2
3
4
5
6
7
8
9
10
MHB255
Fig.15 Line sampling.
8.3.5.1
Field capturing
8.3.5.2
Another problem that must be considered is frame
dropping. It is possible that the connected video source
only provides either odd or even frames, or that the video
source drops frames. Therefore the input interface must
process the incoming video stream in several ways, as
shown in Table 12.
VCLK, or alternatively the clock from MCLKI, is used for
clocking the input interface in YUV mode and the data path
behind the external clock. This second port will be used if
yuv_clk_mux is set to logic 1. The external clock is the
line-locked video clock from the video decoder. This clock
is gated by CREF and applied at pin VPD7. Data is only to
be sampled if this signal is asserted. Alternatively the
line-locked video clock divided by two can be used
(if provided by the decoder). In this event CREF must be
tied to logic 1 or logic 0 depending on its programmed
polarity.
Table 12 Field capture modes
yuv_field_mode[1 and 0]
1999 May 11
DESCRIPTION
0
all incoming frames are
captured
1
after an odd frame the next
even frame will be
captured, and vice versa
2
capture only odd frames
3
capture only even frames
YUV clocking
48
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.4
SAA6721E
8.5
Video mode and synchronization signal
detection
The SAA6721E features a 64 bits wide synchronous
DRAM interface. Both SDRAM and SGRAM devices can
be used. There is no difference in programming when
using SDRAM or SGRAM devices. The only thing that
must be considered is the amount of frame buffer memory,
which must be enough for the specific application.
The SAA6721E can be used to build up multi-sync
systems using an external microcontroller. Therefore
information about the input resolution and timing are
provided (see Tables 7 and 8). The flags pos_vsync and
pos_hsync show the polarity of the synchronization signals
at VVS and VHS. If they are set to logic 1 they are active
HIGH, and their active edge is the falling edge. If these
flags are set to logic 0, they are active LOW.
Depending on the kind of input data stream the memory
interface must be switched to YUV 4 : 2 : 2 or YUV 4 : 1 : 1
mode by setting yuv422_mode to logic 1 to enable 16 bits
per pixel processing. If this flag is set to logic 0, 24 bits per
pixel are used which is needed for RGB and YUV 4 : 4 : 4
processing. If not the whole bandwidth of the 64 bits wide
data bus is needed, the data bus can be downsized to
48 or 32 bits. This is done with the parameter data_width,
see Table 13.
For detecting Video Electronic Standard Association
(VESA) Power-down modes or a not connected input, the
presence of the synchronization signals will be detected:
it can be read via no_vsync, and no_hsync. These flags
are active HIGH. The timing of the applied RGB video input
can be taken from v_lines reporting the number of lines of
a full frame. The horizontal timing can be calculated from
h_clocks. This register shows the length of a line in
numbers of reference clock periods. The reference clock is
equal to the panel clock PCLK in double pixel output mode
(48 bits in parallel), or it is half the panel clock PCLK in
single pixel output mode (24 bits in parallel).
Table 13 Data bus width
If one of the above mentioned flags or counters changes
its value, it can be assumed that a new graphics mode has
been applied. In this case an interrupt at pin INT will be
generated. This port is active LOW. The reset can be
cleared by writing a logic 1 to intr_clear at address 24.
data_width[1 and 0]
PROGRAMMED BUS WIDTH
(BITS)
0
32
1
48
2
64
Since the different timing parameters of various RAM
device types are different, all important timing values are
programmable and must be set-up according to the used
RAM types.
For adjusting the RGB input interface to a new graphics
mode, the registers of the section RGB auto adjustment
are to be used. With this auto adjustment support it is
possible to measure the number of blanking pixels and
lines between the end of the synchronization pulses and
the active video. The horizontal and vertical back porch
blanking can be read out at black_pixels and black_lines.
The number of active pixels or lines will be reported from
non_black_pixels and non_black_lines. The first value
should be used for tuning the sample clocks PLL so that
this value corresponds to the number of pixels to be
sampled horizontally in this specific graphics mode.
To distinguish between blanking and active video
ref_colour is used. If the sample values of all three colour
components are below this value the pixel is treated as a
blanking pixel, otherwise it is treated as active video.
To reach a high effective bandwidth all access to the
external memory is organized in bursts. The larger the
number of subsequent read or write accesses the higher
the effective bandwidth. An effective bandwidth of 91%
can be reached by doing 64 words burst accesses.
The RAM devices support a maximum internal burst
length of 8 words only, so 8 of these bursts must be run
subsequently. This can be programmed by setting up the
RAM with SDRAM_burst_length_code taken from the
specification data of the SDRAM or SGRAM. The memory
interface must be programmed to 64 words bursts by
programming the RAM burst length SDRAM_burst_length
to 8, and the number of these bursts in burst_seq_length
to 8. The internal structure of the SAA6721E is optimized
for 64 words bursts.
Additionally a reference pixel can be defined with ref_line
and ref_pixel. The R, G, and B components of this pixel are
sampled and available at ref_pixel_red, ref_pixel_green,
and ref_pixel_blue. They can be used for fine tuning the
external PLL in frequency and phase and for colour gain
adjustment.
1999 May 11
Memory interface and de-interlacer unit
49
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.5.1
SAA6721E
MEMORY INTERFACE LIMITATIONS
The timing parameters of the memory access can be programmed to fulfil the timing restrictions of several SDRAM or
SGRAM devices. But there are some limitations, as shown in Table 14.
Table 14 Memory interface limitations
TIMING SYMBOL
PARAMETER
CONDITIONS
MINIMUM VALUE
(CLOCK PERIODS)
CAS latency
Column Address Strobe (CAS)
latency
≥2
tRCD
activate to command delay; Row
Address Strobe (RAS) to CAS delay
≥2
tRRD
RAS to RAS bank activity delay
tRP
RAS precharge time
≥3
tWR
write recovery time
≥1
tRC
RAS cycle time
≥3
tRRD ≠ tRCD; proposal is
tRRD = tRCD + 1
≥3
SDRAM_burst_length
must be supported by
SDRAM
≥2
burst_seq_length
must be an even number
≥2
tRSC
8.5.2
Register Set Cycle (RSC) mode time internally defined; cannot be
changed
=8
INITIALIZATION OF EXTERNAL MEMORY
All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6721E memory interface is
implemented to fulfil the INTEL PC100 SDRAM specification.
Table 15 shows the required programming steps to initialize the memory correctly.
Table 15 Memory initialization programming
STEP
8.5.3
ACTION
REGISTERS
−
1
SAA6721E Power-on reset
2
set-up timing parameters
3
start memory initialization with setting memory_init
4
set-up all other parameters
5
release internal memory reset together with other internal resets
51 to 55
24
50 to 74
24
FRAME AND FIELD MEMORY
The memory interface acts as a decoupling unit to adapt the different frame rates at the video input to the panel output.
The external memory is also used for the de-interlacing unit which reconstructs the frames from odd and even fields in
interlaced mode. The algorithm of de-interlacing can be selected by deint_mode (see Table 16).
1999 May 11
50
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
Table 16 De-interlacing modes
deint_mode[1 and 0]
ALGORITHM
MEMORY NEEDS
0
no de-interlacing and no filtering
1 frame buffer
1
de-interlacing without filtering
2 field buffers
2
de-interlacing with spatial filtering
2 field buffers
3
de-interlacing with temporal filtering
4 field buffers
De-interlacing mode 0 must be selected for non-interlaced input of RGB or YUV. Only one memory area is needed,
whose start address must be programmed into field1_row and field1_column. Normally this should be logic 0 for both
values. All other modes need more than one memory area. So the other field start addresses must be programmed
(see Fig.16).
handbook, full pagewidth
field1_row/column
field1_row/column
field1_row/column
ODD FIELD
ODD FIELD
field2_row/column
field2_row/column
EVEN FIELD
EVEN FIELD
field3_row/column
ODD FIELD
deint_mode 0
deint_mode 1/2
field4_row/column
EVEN FIELD
MHB256
deint_mode 3
Fig.16 Memory usage for de-interlacing.
The memory interface addresses alternately the two banks of the SDRAM or SGRAM devices. So the memory needs for
the field stores must be calculated from the following formula:
bytes_per_pixel
field_memory_size[18 to 0] = number_of_pixels × ----------------------------------------------------------------------- , where
2 × data_bus_width (bytes)
• number_of_pixels depends on the input resolution and whether it is an odd or even field
• bytes_per_pixel is 2 for YUV 4 : 2 : 2 and YUV 4 : 1 : 1; 3 for YUV 4 : 4 : 4 and RGB.
All memory addresses must be transformed into row and column addresses used by DRAMs. The column address is
formed by the 8 LSBs (field_memory_size[7 to 0]), and the row address by all the other address bits
(field_memory_size[18 to 8]). The column address must be aligned to the number of internal DRAM bursts, normally in
steps of 8 (0, 8, 16, etc.).
1999 May 11
51
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
The values given in Table 17 can be used for frame
resolutions up to 720 × 576 pixels which complies to the
625 line/50 Hz mode.
Setting up the desired downscaling ratios is achieved by
programming the scaling increments down_v_incr,
down_v_corr, and down_h_incr, down_h_corr. This must
be done for both vertical and horizontal scaling.
Table 17 Field start address values
FIELD
Field1 row/column
000/0
Field2 row/column
08D/0
Field3 row/column
100/0
Field4 row/column
180/0
8.5.4
number_of_output_pixels
incr = ------------------------------------------------------------------- × 64 = xx.yy
number_of_input_pixels
Where xx is equivalent to down_v_incr or down_h_incr
and yy is the fraction of the result in 1⁄100.
VALUE (HEX)
This is the value for programming the increment correction
values down_v_corr and down_h_corr.
Example: SXGA → XGA
FRAME RECOVERY
1024
Horizontal: ------------- × 64 = 51.20
1280
This means down_h_incr = 51 and down_h_corr = 20.
During de-interlacing and also in mode 0, output frames
with the right vertical and horizontal dimensions must be
generated. Since size information is not stored in the
external memory, the output frame resolution must be
programmed into the registers frame_length and
line_length. The first value gives the vertical resolution,
and the second the horizontal resolution in pixels. If no
downscaler is used, these values can be taken directly
from the input interface. If downscaling is activated, the
size of the de-interlacer output frame must be calculated
from the RGB input frame size divided by the downscaling
factors.
768
Vertical: ------------- × 64 = 48.00
1024
This means down_v_incr = 48 and down_v_corr = 0.
8.6.2
The upscaler must be activated by up_v_scaler_on and
up_h_scaler_on. To use the line memory for upscaling,
down_v_scaler_mem must be set to logic 0. To set-up the
zoom factor, the scaling increments up_v_incr, up_v_corr,
up_h_incr, and up_h_corr must be programmed.
If no valid data stream is applied at the RGB/YUV input
interface, the de-interlacer is able to generate a picture by
itself. This will be enabled with blank_screen at
address 25. The colour of this frame is defined by
blank_colour_red, blank_colour_green, and
blank_colour_blue.
8.6
number_of_output_pixels
incr = ------------------------------------------------------------------- × 64 = xx.yy
number_of_input_pixels
Where xx is equivalent to up_v_incr or up_h_incr and yy is
the fraction of the result in 1⁄100.
This is the value for programming the increment correction
values up_v_corr and up_h_corr.
Scaling
Two different scaling units are implemented to perform
both up and downscaling. The downscaling engine, which
is located before the memory interface, and the upscaling
engine after the memory interface.
8.6.1
Example: XGA → SXGA
1280
Horizontal: ------------- × 64 = 80.00
1024
This means up_h_incr = 80 and up_h_corr = 0.
DOWNSCALING
1024
Vertical: ------------- × 64 = 85.33
768
This means up_v_incr = 85 and up_v_corr = 33.
If the downscaler is to be used, it must be enabled by
setting flags down_v_scaler_on and down_h_scaler_on.
For vertical scaling a line memory buffer is needed.
This memory must be switched to downscaling mode by
setting down_v_scaler_mem to logic 1 because only one
is available.
1999 May 11
UPSCALING
52
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.6.3
SAA6721E
UPSCALER TRANSITION FUNCTION
8.7
A special feature of the zooming algorithm is a free
programmable transition function which allows smoothing
or sharpening of the transition between pixels that have
been calculated.
Panning unit
If the scaled or non-scaled input frame does not fit into the
needed output frame, whether it is to large or to small, the
panning unit enlarges the input frame to the size of the
output frame. This is achieved by generating a border
region around the input frame, or it cuts the input frame
down to the size of the output frame. The position of the
top left pixel of the input frame inside the output frame
must be defined with pic_v_offset and pic_h_offset.
The output frame size must be programmed with
out_v_size and out_h_size (see Fig.17).
This function will be stored in a look-up table, containing
64 words of 7 bits; thus a function of 64 points with a
resolution from 0 to 64 can be programmed.
Programming is performed using the registers coeff_index
and coeff_value. The first register defines the point of the
function, the second the value. Writing to register
coeff_value increments the value of coeff_index
automatically, so that the next point of the function is
addressed. Additionally no register increment will be
performed, so that subsequent I2C-bus write addresses
always have the same register coeff_value.
If the input frame is to large only the right and bottom part
will be cropped. The colour of the generated border region
must be set via border_colour_red, border_colour_green,
and border_colour_blue.
handbook, full pagewidth
pic_v_offset
pic_h_offset
pic_v_offset
out_v_size
pic_h_offset
OUTPUT FRAME
INPUT FRAME
out_h_size
Fig.17 Picture positioning.
1999 May 11
53
MHB257
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.8
8.8.1
SAA6721E
The incoming data from ports ovl0 and ovl1 is replaced by
the defined colour information and treated as a double
pixel, which will be inserted into the data stream if OVACT
is set. The pixel at port 0 is then the left pixel, and the pixel
at port 1 is the right pixel. The sampling of the ports ovl0
and ovl1 is done on the positive edge of OVCLK in the
event that sample_edge is asserted, otherwise on the
falling edge of OVCLK.
Overlay port
OVERLAY INSERTION
If ovl_syncs_active is HIGH, the vertical and horizontal
sync signals for the external OSD controller are generated.
The flag ovl_insert_active switches on the insertion of the
information at the overlay port provided by an external
OSD controller into the data stream at the position defined
by ovl_v_offset, ovl_hs_start, and ovl_hs_latency
(see Fig.18).
ovl_hs_latency
handbook, full pagewidth
ovl_hs_start
ovl_v_offset
ovl_v_length
ovl_h_length
OVERLAY
WINDOW
ovl_vs_start
one line Vsync
OUTPUT FRAME
MHB258
Fig.18 Overlay window positioning.
1999 May 11
54
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.8.2
SAA6721E
SYNC GENERATION
8.8.3
The start of the horizontal sync pulse is defined in
ovl_hs_start and the polarity in ovl_hs_pol. The sync
pulse length is defined in ovl_hs_length (see Fig.19). It is
possible to generate a Hsync pulse from one clock cycle
length up to longer than the horizontal overlay data.
The vertical sync pulse starts at ovl_vs_start and is
always one output frame line long.
ovl_hs_start
handbook, full pagewidth
DATA SAMPLING
Data sampling from the two ports OVA and OVB starts
from the beginning of the horizontal sync pulse, but the
number of clocks defined in ovl_hs_latency will decide
when reading data from the overlay port will start
(see Fig.19). The end of the sync pulse is not important.
ovl_hs_length
ovl_hs_latency
ovl_h_length
OVCLK
OVHS
OVA
O0
O2
O4
O6
O8
OVB
O1
O3
O5
O7
O9
OVACT
MHB259
Fig.19 Hsync generation and data sampling (Hsync latency = 2).
8.8.4
8.10
OVCLK GATING
The colour correction unit can be used to perform gamma
correction, change of brightness, and so on. This can be
achieved by means of a look-up table. Each colour
component value in an RGB pixel is used as a pointer into
this table. The value from the table will replace the
incoming colour.
All of the above mentioned functions will only work during
internal processing of valid video data, and not during
internal blanking regions. This can give problems if the
overlay window is displayed at the left border of the picture
because the first pixels of a line will be processed due to
the internal pipeline structure. To overcome this, the
OVCLK can be gated to disable data processing by the
external OSD controller during internal blanking. Clock
gating is enabled by clk_gating_on.
8.9
Various tables exist for R, G, and B components.
Programming of a table must be performed using the
programming registers 47 to 49 (see the colour correction
section of the programming register Table 7). It must be
decided which component table should be written to
(red_prog, green_prog, blue_prog). In colour_index the
start address or the first incoming colour value for
programming must be written. Then subsequent writing to
colour_value fill the table. At this address the I2C-bus
address auto-increment stops, but the value programmed
into colour_index will be incremented. It is possible to write
to more than one table by enabling of programming
multiple colour components.
Colour space matrix
The back-end processing of the SAA6721E and the TFT
panels require RGB video data. So the built-in colour
space matrix is used to convert video data from YUV
space into RGB space. It can be enabled by setting
csm_bypass to logic 0 (see general configuration section
of the programming register Table 7), otherwise the colour
space converter will be bypassed.
1999 May 11
Colour correction
55
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
If the colour correction unit is switched to bypass mode
(when colour_correction_on is not asserted), the incoming
colours are used for further processing.
The programming registers osd_v_size and osd_h_size
define the OSD window size in characters. The window
position inside the output frame must be defined with
osd_v_offset and osd_h_offset (see Fig.20).
Writing to the colour correction table is possible during
data processing.
8.11
On screen display
handbook, halfpage
8.11.1
OSD GENERALS
osd_v_offset
The implemented OSD is a character based window
system. It consists of a character matrix memory where all
character definitions are stored, and an OSD window
memory defining the OSD window’s contents. The OSD
window will be inserted into the video data stream if
osd_active is set to logic 1. Writing to these memories can
be done during data processing.
osd_h_offset
osd_v_size
OSD
OUTPUT FRAME
8.11.2
MHB260
OSD WINDOW
osd_h_size
The OSD window contains the character, colour and
appearance information to be displayed. Such a definition
exists for each character position. A character can use one
of 8 different foreground and background colours. Some of
these colours can be defined as transparent colours where
the original picture information will be displayed instead,
as alpha blended colours where a 1 : 1 or 1 : 2 alpha
blending will be done between picture and OSD, or as
normal colours. Transparency or alpha blending effects
will be enabled or disabled for the single characters.
Fig.20 OSD window positioning.
The OSD can be programmed to use a 24 × 24 character
matrix, or a 12 × 16 matrix. The first one should be used for
Kanji and the second for standard characters.
The selection of the font size is done by char_size.
A logic 1 selects 24 × 24 font, and a logic 0 the smaller
12 × 16 font. If the small 12 × 16 font is used, up to
128 different characters can be defined. Alternatively up to
42 characters of the larger 24 × 24 font can be used.
The size and outline of the visible OSD window can be
programmed as long as the internal memory meets the
needs. This memory is able to store information of
1152 characters information.
1999 May 11
Table 18 gives some possible OSD settings.
56
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
Table 18 OSD window size
OSD SIZE
Table 20 Colour effects
APPEARANCE
VALUE
OSD WINDOW
RESOLUTION/PIXELS
24 × 24
12 × 16
32 × 16
768 × 384
384 × 256
40 × 20
960 × 480
480 × 320
48 × 24
1152 × 576
576 × 384
The whole OSD window can be zoomed in both directions
by a factor of two by setting zoom2 to logic 1. This results
in pixel doubling horizontally and vertically.
Each character can be displayed using 1 of 8 different
foreground and background colours. These sixteen
colours can be chosen from the full true colour palette with
8 bits per colour component. The definition of these
colours is in registers 144 to 191 (see OSD section of the
programming register Table 7). The first 8 colour entries
are used for foreground colours, and the second half is
used for defining the background colours. Registers
192 to 195 (see Table 7) decide the transparency and
alpha blending effects. If one of these effects is enabled for
a specific character, only the colours defined as
transparency or alpha blending colours will be used to
generate these effects.
8.11.3
NUMBER OF BITS
7
Appearance
2
Background colour
3
Foreground colour
3
1
OSD character colours defined as
transparency colours will be replaced
by the picture colours
2
OSD character colours defined as
alpha blending colours will be alpha
blended 1 : 1 with the picture colours
3
OSD character colours defined as
alpha blending colours will be alpha
blended 2 : 1 with the picture colours
OSD CHARACTER MATRIX
The definition of the characters is achieved by writing to
registers 200 and 201 (see Table 7). The first register
must be written to with the character code of the character
to be defined. Then the bytes with the pixel pattern must
be written to address 201 (see Table 7). The definition of a
character is done with 3 bytes per line at 24 × 24 font
(72 bytes per character), and with 3 bytes per 2 lines at
12 × 16 font (24 bytes per character), see Fig.21.
The character code is used to address the defined
characters inside the matrix memory.
The appearance bits decide about transparency and alpha
blending, and background and foreground colour are
indices to the colour definition registers.
1999 May 11
OSD character colours are displayed
instead of the picture colours
Two different font sizes are supported; 24 × 24 and
12 × 16 pixels. With the internal matrix memory
42 characters (24 × 24 pixels) can be defined, or
128 characters (16 × 12 pixels).
Table 19 Character appearance definition
Character code
0
To access a certain character position its coordinates must
be programmed into registers 196 (cursor_row) and 197
(cursor_column), see Table 7. After that, the colours and
appearance of the character must be defined in
address 198 (see Table 7). This definition is valid for all
further writes to register 199 (char_code), see Table 7.
After writing to this register the cursor position changes to
the next right position. At line end it wraps around to the
first left character in the line below. I2C-bus auto-increment
is not active at register 199 (see Table 7), so that
subsequent I2C-bus byte write accesses will define several
characters.
Each character information in the OSD window memory
consists of 15 bits of information. This is given in
Tables 19 and 20.
CHARACTER INFORMATION
EFFECT
57
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
The second mode is synchronized to the input data, mainly
implemented to support the SAA6721E’s no memory
mode. In this mode the input data is sent directly to the
output interface, which must synchronize its output timing
to get the same frame rate as the input. Additionally it
starts generating vertical blanking and synchronization
signals at pins PVS and PHS directly after releasing the
internal reset.
handbook, halfpage
1 byte
After the programmed top blanking the output interface
enlarges the last blanking line until data from the input
interface reaches the output interface. Because too long
lines cause counter overflows in the panels, a controlling
mechanism exists which changes the length of the
blanking, border and active lines according to the timing
requirements of the panel and the applied graphics mode.
This mode can be enabled by setting the programming
register sync_mode to logic 1, otherwise the first free
running mode will be selected.
(a)
(b)
MHB261
The length controlling the blanking, border and active
video region can be enabled by asserting blank_ctrl,
border_ctrl, and active_ctrl.
a: 24 × 24 font definition.
b: 12 × 16 font definition.
The output interface also supports a Power-down mode
which sets all output signals to logic 0. This will be
activated by the programming flag power_down
(see section general configuration Table 7).
Fig.21 Character matrix organization.
8.12
For flicker free switching between different input modes,
the output interface is able to set all data outputs to the
panel to logic 0, resulting in a black picture. Even if during
programming and internal reset no synchronization pulses
for the panel are generated and the panel loses the last
picture information, the panel still displays black colour,
because this is its Idle state. To switch the output interface
into this mode blank_tft must be set.
Temporal dithering (frame rate controller)
The SAA6721E is able to display true colour (8 bits per
colour) on high colour displays (6 bits per colour).
The algorithm used is temporal dithering. This feature can
be enabled by setting frc_on to logic 1 in the general
configuration register block (see Table 7).
8.13
8.13.1
Output interface
To enable the panel interface it must be enabled with
out_if_enable. The interface supports single pixel (24 bits)
and double pixel (48 bits) output in parallel. The selection
between these two modes must be done with
single_pixel_output. The active clock edge at PCLK can
also be selected by clk_pol.
GENERAL
The output interface is the interface between the
SAA6721E and the TFT panel. Its timing parameters can
be programmed in a wide range to support panels of many
different manufacturers.
The output interface can operate in two different modes.
The first mode is the free running mode which is adapted
to the memory mode of the SAA6721E. In this mode the
output is independent from the input at the RGB/YUV input
interface. So the output frame generation can start directly
after releasing the internal reset. For getting a high frame
rate the output timing can be programmed to satisfy the
minimum timing requirements of the panel.
1999 May 11
58
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.13.2
SAA6721E
A maximum value must be programmed in h_max_len
which is the upper limit for line lengthening during
activated control mechanism. In free running mode all
3 counters should be programmed with the same
minimum values.
FRAME GENERATION
The output frame contains three main regions:
• Blanking region
• Border region
• Active video region.
If no border is needed, because the active video region
covers the visible area of the panel, the active video length
counters should point to the same positions as the border
length counters. Then the active video length counters
have a higher priority.
The blanking region contains all front and back porch as
well as the synchronization intervals. The border region is
visible on the panel and is used for positioning the active
video region inside this visible area. To ensure a great
flexibility in the ‘sync to input’ mode there are 3 different
horizontal length counters (h_len_blank, h_len_border,
h_len_active) with independent length control
(see Fig.22).
h_hs_start
handbook, full pagewidth
The border colour inserted by the output interface is the
same as the blank colour in the memory interface;
blank_colour_red, blank_colour_green,
blank_colour_blue.
h_len_border
h_hs_end
starting point
PHS
v_vs_end
v_start
v_active
h_len_blank
active video
border
PVS
blanking
v_end
h_de_start
h_active_start
h_de_end
h_len_active
h_max_len
MHB262
Fig.22 Output frame and timing.
1999 May 11
59
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.13.3
SAA6721E
The position and length of the horizontal synchronization
pulses in an output line must be programmed with
h_hs_start and h_hs_end. The vertical synchronization
pulse starts at line 0 and ends at v_vs_end. The horizontal
start offset in line 0 can be set-up with h_vs_start and the
horizontal end offset with h_vs_end.
TIMING REFERENCE SIGNALS
The SAA6721E supports three timing reference signals to
drive the panels: PVS (vertical synchronization pulse),
PHS (horizontal synchronization pulse) and PDE (data
qualifier). The polarity of these signals is programmable.
To program high polarity the three programming registers
(vsync_pol, hsync_pol, de_pol) must be set to logic 1.
Sometimes panels require that no data qualifier signals
must be active during vertical synchronization.
The generation of PDE pulses during active PVS can be
switched off by de-asserting sync_de_inact.
The data qualifier PDE frames the display region that
should be visible on the panel horizontally. It will be
asserted at h_de_start and it will be de-asserted at
h_de_end. It frames both horizontal border and active
video region.
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins are connected together and all
supply pins are connected together.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.5
+4.6
V
VDD(PLL)
PLL supply voltage
−0.5
+4.6
V
Vn
voltage at digital inputs and outputs
outputs in 3-state −0.5
+5.5
V
voltage at digital output
outputs active
−0.5
VDDD + 0.5 V
∆VSS
voltage difference between VSS(PLL) and VSS(D)
−
100
mV
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
0
70
°C
Tamb(bias)
operating bias ambient temperature
−10
+70
°C
Ves
electrostatic handling voltage for all pins
−2
+2
kV
note 1
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
1999 May 11
60
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
10 CHARACTERISTICS
VDDD = 3.0 to 3.6 V; VDD(PLL) = 3.1 to 3.5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
digital supply voltage
3.0
3.3
3.6
V
IDDD
digital supply current
−
600
tbf
mA
PD
digital power dissipation
−
2
−
W
VDD(PLL)
PLL supply voltage
3.1
3.3
3.5
V
IDD(PLL)
PLL supply current
−
tbf
tbf
mA
PPLL
PLL power dissipation
−
tbf
−
W
PPLL + D
digital plus PLL power
dissipation
−
2
−
W
VIL(SCL, SDA) LOW-level input voltage
at pins SDA and SCL
−0.5
−
+0.3VDDD
V
VIH(SCL, SDA) HIGH-level input voltage
at pins SDA and SCL
0.7VDDD
−
VDDD + 0.5 V
VIL(LVTTL)
LOW-level input voltage
at LVTTL pins
−0.5
−
+0.8
VIH(LVTTL)
HIGH-level input voltage
at LVTTL pins
2.0
−
VDDD + 0.5 V
ILI
input leakage current
−
−
10
Digital inputs
Ci
V
µA
−
−
8
pF
−
−
5
pF
LOW-level output voltage SDA at 3 mA sink current −
at pin SDA
SDA at 6 mA sink current −
−
0.4
V
−
0.6
V
input capacitance
outputs at 3-state
input capacitance at all
other inputs
Digital outputs
VOL(SDA)
VOL(CMOS)
LOW-level output voltage
at CMOS pins
−
−
0.4
V
VOH(CMOS)
HIGH-level output
voltage at CMOS pins
2.4
−
−
V
VOL(LVTTL)
LOW-level output voltage
at LVTTL pins
−
−
0.4
V
VOH(LVTTL)
HIGH-level output
voltage at LVTTL pins
0.85VDDD
−
−
V
1999 May 11
61
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
11 TIMING CHARACTERISTICS
VDDD = 3.0 to 3.6 V; VDD(PLL) = 3.1 to 3.5 V; Tamb = 25 °C; see Fig.23; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock input at pin CLK
fCLK
clock frequency
24
−
70
MHz
δ
duty factor
40
50
60
%
single ADC mode
25
−
150
MHz
double ADC mode
12.5
−
75
MHz
40
50
60
%
RGB/YUV sample clock input at pin VCLK
fVCLK
δ
clock frequency
duty factor
Input signals at pins VVS, VHS, VPA7 to VPA0, VPB7 to VPB0, VPC7 to VPC0, VPD7 to VPD0, VPE7 to VPE0,
and VPF7 to VPF0 with respect to signal at pin VCLK
tsu
set-up time
−4.0
−
−
ns
th
hold time
7.0
−
−
ns
Output signals at pins CLAMP and GAINC with respect to signal at pin VCLK; note 1
th
hold time
8
−
−
ns
tPD
propagation delay
−
−
13
ns
Output clock to panel at pin PCLK
fPCLK
clock frequency
−
−
80
MHz
δ
duty factor
40
50
60
%
Output signals at pins PVS, PHS, PDE, PAR7 to PAR0, PAG7 to PAG0, PAB7 to PAB0, PBR7 to PBR0,
PBG7 to PBG0, and PBB7 to PBB0 with respect to signal at pin PCLK; note 2
th
tPD
hold time
pins PVS, PHS and PDE
−0.5
−
−
ns
all other pins
0
−
−
ns
pins PVS, PHS and PDE
−
−
1
ns
all other pins
−
−
3.5
ns
80
MHz
60
%
propagation delay
Overlay port clock output at pin OVCLK
fOVCLK
clock frequency
δ
duty factor
40
50
Input signals at pins OVACT, OVA2 to OVA0, and OVB2 to OVB0 with respect to signal at pin OVCLK
tsu(i)
set-up time
6.0
−
−
ns
th(i)
hold time
−3.0
−
−
ns
Output signals at pins OVVS and OVHS with respect to signal at pin OVCLK; note 1
th(o)
hold time
−1.0
−
−
ns
tPD(o)
propagation delay
−
−
1.0
ns
1999 May 11
62
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SYMBOL
PARAMETER
SAA6721E
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Memory port clock output; pin MCLKO
fMCLKO
frequency
−
−
125
MHz
CL
load capacitance
−
−
20
pF
δ
duty factor
40
50
60
%
Input signal at pin MCLKI with respect to signal at pin MCLKO; see Fig.24
fMCLKI
frequency
−
−
125
MHz
δ
duty factor
40
50
60
%
tPD
propagation delay
6.5
10
ns
Input signals at pins DQ63 to DQ0 with respect to the negative edge of signal at pin MCLKO
tsu
set-up time
6.0
−
−
ns
th
hold time
−3.0
−
−
ns
Output signals at pins DQ63 to DQ0, RAS, CAS, WE, A10 to A0, and BA with respect to the negative edge of
signal at pin MCLKO; note 3
th
tPD
hold time
pins DQ63 to DQ0
−1
−
−
ns
pins RAS, CAS, WE,
A10 to A0, and BA
0
−
−
ns
pins DQ63 to DQ0
−
−
1.0
ns
pins RAS, CAS, WE,
A10 to A0, and BA
−
−
1.0
ns
propagation delay
Notes
1. CL = 15pF, Io = 2 mA and RL = 2 kΩ.
2. CL = 15pF, Io = 4 mA and RL = 2 kΩ.
3. CL = 10pF, Io = 4 mA and RL = 2 kΩ.
1999 May 11
63
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
1.5 V
clock input
data input
tsu(i)
th(i)
data output
data
transition
period
data
valid
MHB490
th(o)
tPD(o)
tsu(i): input set-up time; data input must be stable before active clock edge.
th(i): input hold time; data input must be stable after active clock edge.
tPD(o): output propagation delay; output data becomes stable with respect to active clock edge.
th(o): output hold time; output data stays stable with respect to active clock edge.
Fig.23 Data timing diagram.
handbook, full pagewidth
1.5 V
MCLKI
MCLKO
tPD
MHB491
Fig.24 Memory clock timing.
1999 May 11
64
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
12 APPLICATION INFORMATION
handbook, full pagewidth
VIDEO
PORT
SAA7113A
YUV
SDRAM
16 MBits
SDRAM
16 MBits
SDRAM
16 MBits
SDRAM
16 MBits
EEPROM
TDA8752
RGB
VGA
PORT
SAA6721E
MICROCONTROLLER
P87C695
TDA8752
RGB
I2C-bus
PANEL PORT
USB
MHB263
Fig.25 Test board.
1999 May 11
65
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
13 PACKAGE OUTLINE
BGA292: plastic ball grid array package; 292 balls; body 27 x 27 x 1.75 mm
SOT489-1
D
D1
ball A1
corner
A2
A
A1
E1 E
detail X
k
k
A
ZD
b
e
∅w M
y
v A
ZE
Y
W
V
U
T
R
P
e
N
M
L
K
J
H
G
F
E
D
C
B
A
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
X
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
D1
E
E1
e
k
v
w
y
ZD
ZE
mm
2.46
0.70
0.50
1.85
1.62
0.90
0.60
27.2
26.8
24.7
24.0
27.2
26.8
24.7
24.0
1.27
4.0
3.9
0.35
0.3
0.15
1.84
1.04
1.84
1.04
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
SOT489-1
1999 May 11
EUROPEAN
PROJECTION
ISSUE DATE
98-05-06
66
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
If wave soldering is used the following conditions must be
observed for optimal results:
14 SOLDERING
14.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
14.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
14.3
14.4
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
1999 May 11
Manual soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
67
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
14.5
SAA6721E
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, SMS
not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 May 11
68
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
15 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 May 11
69
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NOTES
1999 May 11
70
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NOTES
1999 May 11
71
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/750/01/pp72
Date of release: 1999 May 11
Document order number:
9397 750 04392