PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) FEATURES • • • • • • • • VCXO output for the 48MHz to 100MHz range Low phase noise (-130 dBc @ 10kHz offset at 48MHz). CMOS output. 12 to 25MHz crystal input. Integrated variable capacitors. Selectable High Drive (30mA) or Standard Drive (10mA) output. Wide pull range (+/- 250 ppm). Low jitter (RMS): 3.5ps period. 3.3V operation. Available in 8-Pin SOIC. XOUT 1 N/C 2 VCON 3 GND 4 8 XIN 7 OE^ 6 VDD 5 CLK Note: ^ denotes internal pull up OUTPUT RANGE FREQUENCY RANGE 48 - 100MHz MULTIPLIER DESCRIPTION PLL502-03 • • PIN CONFIGURATION X4 The PLL502-03 is a low cost, high performance and low phase noise VCXO for the 48 to 100MHz range, providing less than -130dBc at 10kHz offset at 48MHz. The very low jitter (3.5ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 12 to 25MHz (fundamental resonant mode). OUTPUT BUFFER CMOS BLOCK DIAGRAM VCO Divider Reference Divider XIN XOUT XTAL OSC Phase Comparator Charge Pump Loop Filter VCO CLK OE VARICAP VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1 PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) PIN DESCRIPTIONS Name Number Type Description XOUT 1 I Crystal output. See Crystal Specifications on page 3. N/C 2 - Not connected. VCON 3 I Voltage Control input. GND 4 P Ground. CLK 5 O Output clock. VDD 6 P +3.3V power supply. OE 7 I Output enable input. Disables (tri-state) output when low. Internal pull-up enables output by default if pin is not connected to low. XIN 8 I Crystal input. See Crystal Specifications on page 3. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. DC Electrical Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output drive current (High Drive) Output drive current (Standard Drive) Short Circuit Current VCXO Control Voltage SYMBOL I DD V DD I OH I OL I OH I OL CONDITIONS MIN. F XIN = 12 - 25MHz Output load of 10pF V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V TYP. MAX. UNITS 16 20 mA 3.63 V mA mA mA mA mA V 2.97 30 30 10 10 ±50 VCON 0 3.3 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 2 PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) 3. AC Electrical Specifications PARAMETERS SYMBOL Input Crystal Frequency Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) Output Clock Duty Cycle CONDITIONS MIN. TYP. 12 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 Measured @ 50% V DD 45 50 CONDITIONS MIN. TYP. MAX. UNITS 25 MHz ns 55 % MAX. UNITS 10 ms 4. Voltage Control Crystal Oscillator PARAMETERS SYMBOL VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW T VCXOSTB From power valid F XIN = 12 – 25MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V 500 ppm 150 ppm ppm/V % ±200 10 0V ≤ VCON ≤ 3.3V, -3dB 2000 25 kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 5. Jitter and Phase Noise specification PARAMETERS RMS Period Jitter (1 sigma – 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier CONDITIONS MIN. with capacitive decoupling between VDD and GND. 48MHz @100Hz offset 48MHz @1kHz offset 48MHz @10kHz offset 48MHz @100kHz offset 48MHz @1MHz offset TYP. MAX. UNITS 3.5 ps -100 -123 -130 -125 -125 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Capacitance Rating C0/C1 ESR SYMBOL MIN. F XIN C L (xtal) 12 RS TYP. MAX. UNITS 25 MHz pF - 9.5 250 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 3 PLL502-03 Low Phase Noise VCXO (48MHz to 100MHz) PACKAGE INFORMATION 8 PIN SOIC (in mm) Symbol A A1 B C D E H L e Min. Max. 1.47 1.73 0.10 0.25 0.33 0.51 0.19 0.25 4.80 4.95 3.80 4.00 5.80 6.20 0.38 1.27 1.27 BSC E H D A A1 C e L B ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL502-03 (H) X C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL Optional High Drive PACKAGE TYPE S=SOIC Order Number Marking Package Option PLL502-03SC PLL502-03SC -R PLL502-03HSC PLL502-03HSC -R P502-03SC P502-03SC P502-03HSC P502-03HSC 8-Pin 8-Pin 8-Pin 8-Pin SOIC SOIC SOIC SOIC (Tube) (Tape and Reel) (Tube) (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 4