INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4511 BCD to 7-segment latch/decoder/driver Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 ripple blanking input (BI), an active LOW lamp test input (LT), and seven active HIGH segment outputs (Qa to Qg). FEATURES • Latch storage of BCD inputs When LE is LOW, the state of the segment outputs (Qa to Qg) is determined by the data on D1 to D4. When LE goes HIGH, the last data present on D1 to D4 are stored in the latches and the segment outputs remain stable. When LT is LOW, all the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BI forces all segment outputs LOW. The inputs LT and BI do not affect the latch circuit. • Blanking input • Lamp test input • Driving common cathode LED displays • Guaranteed 10 mA drive capability per output • Output capability: non-standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with “4511” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS The 74HC/HCT4511 are BCD to 7-segment latch/decoder/drivers with four address inputs (D1 to D4), an active LOW latch enable input (LE), an active LOW • Driving LCD displays • Driving LED displays • Driving incandescent displays • Driving fluorescent displays • Driving gas discharge displays QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V Dn to Qn 24 24 ns LE to Qn 23 24 ns BI to Qn 19 20 ns LT to Qn 12 13 ns 3.5 3.5 pF 64 64 pF CI input capacitance CPD power dissipation capacitance per latch notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V December 1990 HCT 2 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 3 LT lamp test input (active LOW) 4 BI ripple blanking input (active LOW) 5 LE latch enable input (active LOW) 7, 1, 2, 6 D1 to D4 BCD address inputs 8 GND ground (0 V) 13, 12, 11, 10, 9, 15, 14 Qa to Qg segments outputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS DISPLAY LE BI LT D4 D3 D2 D1 Qa Qb Qc Qd Qe Qf Qg X X L X X X X H H H H H H H 8 X L H X X X X L L L L L L L blank L L L L H H H H H H H H L L L L L L L L L L H H L H L H H L H H H H H H H H L H H L H H H L H L H L L L L L H H 0 1 2 3 L L L L H H H H H H H H L L L L H H H H L L H H L H L H L H L H H L L H H H H H L H H L L L H L H H H L H H H L 4 5 6 7 L L L L H H H H H H H H H H H H L L L L L L H H L H L H H H L L H H L L H H L L H L L L H L L L H H L L H H L L 8 9 blank blank L L L L H H H H H H H H H H H H H H H H L L H H L H L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L blank blank blank blank H H H X X X X (1) Note 1. Depends upon the BCD-code applied during the LOW-to-HIGH transition of LE. H = HIGH voltage level L = LOW voltage level X = don’t care December 1990 4 (1) Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver Fig.5 Logic diagram. Fig.6 Segment designation. Fig.7 Display. December 1990 5 74HC/HCT4511 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard, excepting VOH which is given below ICC category: MSI Non-standard DC characteristics for 74HC Voltages are referenced to GND (ground = 0 V) Tamb (°C) SYMBOL TEST CONDITIONS 74HC PARAMETER +25 min. typ. −40 to +85 UNIT VCC (V) −40 to +125 VI −IO (mA) max. min. max. min. max. VOH HIGH level output voltage 3.98 3.60 3.84 3.35 3.70 3.10 V 4.5 VIH or 7.5 VIL 10.0 VOH HIGH level output voltage 5.60 5.48 4.80 5.45 5.34 4.50 5.35 5.20 4.20 V 6.0 VIH or 7.5 VIL 10.0 15.0 December 1990 6 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay Dn to Qn 77 28 22 300 60 51 375 75 64 450 90 77 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay LE to Qn 74 27 22 270 54 46 330 68 58 405 81 69 ns 2.0 4.5 6.0 Fig.9 tPHL/ tPLH propagation delay BI to Qn 61 22 18 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 Fig.10 tPHL/ tPLH propagation delay LT to Qn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Figs 8, 9 and 10 tW latch enable pulse width 80 LOW 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.9 tsu set-up time Dn to LE 60 12 10 14 5 4 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.11 th hold time Dn to LE 0 0 0 −11 −4 −3 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.11 December 1990 7 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard, excepting VOH which is given below ICC category: MSI Non-standard DC characteristics for 74HCT Voltages are referenced to GND (ground = 0 V) Tamb (°C) SYMBOL 74HCT PARAMETER +25 min. VOH HIGH level output voltage TEST CONDITIONS typ. −40 to +85 UNIT VCC (V) −40 to +125 VI max. min. max. min. max. 3.98 3.60 3.84 3.35 3.70 3.10 V 4.5 VIH or 7.5 VIL 10.0 Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT LT, LE BI, Dn 1.50 0.30 December 1990 −IO (mA) 8 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay Dn to Qn 28 60 75 90 ns 4.5 Fig.8 tPHL/ tPLH propagation delay LE to Qn 27 54 68 81 ns 4.5 Fig.9 tPHL/ tPLH propagation delay BI to Qn 23 44 55 66 ns 4.5 Fig.10 tPHL/ tPLH propagation delay LT to Qn 16 30 38 45 ns 4.5 Fig.8 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 8, 9 and 10 tW latch enable pulse width LOW 16 5 20 24 ns 4.5 Fig.9 tsu set-up time Dn to LE 12 5 15 18 ns 4.5 Fig.11 th hold time Dn to LE 0 −4 0 0 ns 4.5 Fig.11 December 1990 9 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Fig.9 Waveforms showing the input (Dn, LT) to output (Qn) propagation delays and the output transition times. Waveforms showing the input (LE) to output (Qn) propagation delays and the latch enable pulse width. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the input (BI) to output (Qn) propagation delays. December 1990 Fig.11 Waveforms showing the data set-up and hold times for Dn input to LE input. 10 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver 74HC/HCT4511 APPLICATION DIAGRAMS Fig.13 Connection to common anode LED display readout. Fig.12 Connection to common cathode LED display readout. (1) A filament pre-warm resistor to reduce thermal shock and to increase effective cold resistance of the filament is recommended. Fig.14 Connection to incandescent display readout. Fig.15 Connection to fluorescent display readout. Fig.16 Connection to gas discharge display readout. Fig.17 Connection to LCD display readout. (Direct DC drive is not recommended as it can shorten the life of LCD displays). December 1990 11 Philips Semiconductors Product specification BCD to 7-segment latch/decoder/driver PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 12 74HC/HCT4511