INTEGRATED CIRCUITS DATA SHEET TDA8706A 6-bit analog-to-digital converter with multiplexer and clamp Product specification File under Integrated Circuits, IC02 1996 Jul 30 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A FEATURES APPLICATIONS • 6-bit resolution • General purpose video applications • Binary 3-state CMOS outputs • R, G and B signals • CMOS compatible digital inputs • Automotive (car navigation) • 3 multiplexed video inputs • LCD systems • R, G and B clamps on code 0 • Frame grabber. • Single 6-bit ADC operation allowed up to 40 MSPS • External control of clamping level GENERAL DESCRIPTION • Internal reference voltage (external reference allowed) The TDA8706A is a 6-bit analog-to-digital converter (ADC) with 3 analog multiplexed inputs. Each input has an analog clamp on code 0 for RGB video processing. Clamping level can also be adjusted externally up to code 20. It can also be used as a single 6-bit ADC. • Power dissipation only 36 mW (typical) • Operating temperature of −40 to +85 °C • Operating between 2.7 and 5.5 V. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 2.7 3.0 5.5 V VDDD digital supply voltage 2.7 3.0 5.5 V VDDO output stages supply voltage 2.7 3.0 5.5 V IDDA analog supply current − 7 10 mA IDDD digital supply current − 4 6 mA IDDO output stages supply current fclk = 40 MHz; ramp input − 1 1.5 mA INL integral non-linearity fclk = 40 MHz; ramp input; Tamb = 25 °C − ±0.25 ±0.6 LSB DNL differential non-linearity fclk = 40 MHz; ramp input; Tamb = 25 °C − ±0.20 ±0.5 LSB fclk(max) maximum clock frequency 40 − − MHz Ptot total power dissipation 3 V supplies − 36 − mW 5.5 V supplies − − 96 mW fclk = 40 MHz; ramp input ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8706AM SSOP24 1996 Jul 30 DESCRIPTION plastic shrink small outline package; 24 leads; body width 5.3 mm 2 VERSION SOT340-1 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A BLOCK DIAGRAM VCLPR VCLPB VCLPG handbook, full pagewidth 11 12 13 CLP RED CLK 24 CLAMP 4 8 6-BIT ADC MULTIPLEXER GREEN BLUE CMOS OUTPUTS 20 D5 19 D4 18 D3 17 D2 16 D1 15 D0 9 10 TDA8706A VSSD 22 VDDA REGULATOR 21 5 23 1 2 3 6 VDDO VDDA VDDD SR SG SB VRB select inputs Fig.1 Block diagram. 1996 Jul 30 3 7 VSSA 14 VSSO MGD133 digital voltage outputs Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A PINNING SYMBOL PIN DESCRIPTION SR 1 select input RED SG 2 select input GREEN SB 3 select input BLUE CLP 4 clamping pulse input (positive pulse) VDDA 5 analog supply voltage SR 1 24 CLK VRB 6 reference voltage BOTTOM input SG 2 23 VDDD VSSA 7 analog ground SB 3 22 VSSD RED 8 RED input CLP 4 GREEN 9 GREEN input 21 VDDO 20 D5 10 BLUE input VDDA 5 BLUE VCLPR 11 RED clamping voltage level input VRB 6 VCLPB 12 BLUE clamping voltage level input VSSA 7 18 D3 VCLPG 13 GREEN clamping voltage level input RED 8 17 D2 VSSO 14 digital output ground GREEN 9 16 D1 D0 15 digital voltage output; bit 0 (LSB) BLUE 10 15 D0 D1 16 digital voltage output; bit 1 D2 17 digital voltage output; bit 2 D3 18 digital voltage output; bit 3 D4 19 digital voltage output; bit 4 D5 20 digital voltage output; bit 5 VDDO 21 supply voltage for output stage VSSD 22 digital ground VDDD 23 digital supply voltage CLK 24 clock input 1996 Jul 30 handbook, halfpage 19 D4 TDA8706A VCLPR 11 14 VSSO VCLPB 12 13 VCLPG MGD132 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage −0.3 +7.0 V VDDD digital supply voltage −0.3 +7.0 V ∆VDD supply voltage difference VDDA − VDDD −1.0 +1.0 V VDDA − VDDO −1.0 +1.0 V VDDD − VDDO −1.0 +1.0 V VI input voltage −0.3 +7.0 V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Tj junction temperature − +150 °C HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 Jul 30 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 119 K/W Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A CHARACTERISTICS VDDA = V5 to V7 = 2.7 to 5.5 V; VDDD = V23 to V22 = 2.7 to 5.5 V; VDDO = V21 to V14 = 2.7 to 5.5 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = −40 to +85 °C; typical values measured at VDDA = VDDD = VDDO = 3 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA analog supply voltage 2.7 3.0 5.5 V VDDD digital supply voltage 2.7 3.0 5.5 V VDDO output stages supply voltage 2.7 3.0 5.5 V ∆VDD supply voltage difference VDDA − VDDD −0.3 − +0.3 V VDDA − VDDO −0.3 − +0.3 V VDDD − VDDO −0.3 − +0.3 V IDDA analog supply current − 7 10 mA IDDD digital supply current − 4 6 mA IDDO output stages supply current fclk = 40 MHz; ramp input − 1 1.5 mA 0 − VDDD × 0.3 V 0 − Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 VIL LOW level input voltage VIH HIGH level input voltage VDDD < 3.3 V VDDD × 0.2 V VDDD × 0.7 − VDDD V VDDD < 3.3 V VDDD × 0.8 − VDDD V IIL LOW level input current Vclk = VDDD × 0.2 −1 0 +1 µA IIH HIGH level input current Vclk = VDDD × 0.8 − 2 10 µA Zi input impedance fclk = 40 MHz − 4 − kΩ CI input capacitance fclk = 40 MHz − 3 − pF 0 − VDDD × 0.3 V 0 − INPUTS SR, SG, SB, CLP (REFERENCED TO VSSD) VIL LOW level input voltage VIH HIGH level input voltage VDDD < 3.3 V VDDD × 0.2 V VDDD × 0.7 − VDDD V VDDD < 3.3 V VDDD × 0.8 − VDDD V IIL LOW level input current VIL = VDDD × 0.2 −1 − − µA IIH HIGH level input current VIH = VDDD × 0.8 − − +1 µA INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2 VCLP input voltage for clamping Vcode −9 − Vcode 20 V ICLP input current − − 30 µA 1996 Jul 30 6 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp SYMBOL PARAMETER TDA8706A CONDITIONS MIN. TYP. MAX. UNIT ANALOG INPUTS RED, GREEN AND BLUE; see Table 1 Vi(p-p) input voltage amplitude (peak-to-peak value) VDDA = VDDD = 3 V; Tamb = 25 °C 0.665 0.70 0.735 V VDDA = VDDD = 5 V; Tamb = 25 °C 0.625 0.66 0.695 V Ii input current − − 10 µA Cclamp clamp coupling capacitance 1 10 100 nF Reference voltages for the resistor ladder; see Table 1 VRB reference voltage BOTTOM VDDA = 3 V − VDDA − 1.19 − V VDDA = 5 V − VDDA − 1.13 − V ∆TVRB temperature variation on VRB Tamb = 0 to 50 °C − 0.7 − mV/°C − 0.5 V VDDO V Outputs DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD) VOL LOW level output voltage IO = 1 mA 0 VOH HIGH level output voltage IO = −1 mA VDDO − 0.5 − Switching characteristics CLOCK INPUT CLK; see Fig.3; note 1 fclk(max) maximum clock frequency 40 − − MHz fmux(max) maximum multiplexer frequency 20 − − MHz tCPH clock pulse width HIGH 8 − − ns tCPL clock pulse width LOW 8 − − ns tr clock rise time 10% to 90%; fclk ≤ 25 MHz; − LOW = VSSD, HIGH = VDDD − 10 ns tf clock fall time 90% to 10%; fclk ≤ 25 MHz; − LOW = VSSD, HIGH = VDDD − 10 ns Analog signal processing LINEARITY INL integral non-linearity fclk = 40 MHz; ramp input; Tamb = 25 °C − ±0.25 ±0.6 LSB DNL differential non-linearity fclk = 40 MHz; ramp input; Tamb = 25 °C − ±0.20 ±0.5 LSB 5.8 − bits EFFECTIVE BITS; note 2 EB 1996 Jul 30 effective bits fclk = 40 MHz; fi = 4.43 MHz − 7 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp SYMBOL PARAMETER TDA8706A CONDITIONS MIN. TYP. MAX. UNIT Timing (fclk = 40 MHz; CL = 20 pF); Tamb = 25 °C; see Fig.3 OUTPUT DATA; note 3 tds sampling delay time − − 7 ns th output hold time 5 − − ns td output delay time VDDO = 4.75 V − 12 15 ns VDDO = 3.15 V − 17 20 ns VDDO = 2.70 V − 18 21 ns 10 − − ns SELECT INPUT SIGNALS SR, SG, SB AND CLP tsu set-up time SR, SG and SB with no overlap; see Fig.3 with overlap see Fig.4 ns tr rise time SR, SG and SB 10% to 90% 4 6 − ns tf fall time SR, SG and SB 90% to 10% 4 6 − ns tover R, G and B (active) overlap time with respect to select signals SR, SG and SB see Fig.4 0 − − ns tCLPP clamp pulse time CCLP = 10 nF − 3 − µs tMH multiplexer hold time SR, SG and SB 9 − − ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 3. Output data acquisition: the output data is available after the maximum delay time of td. 1996 Jul 30 8 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp Table 1 TDA8706A Output coding and input voltage (typical values) Vi(p-p) (V) STEP BINARY OUTPUT BITS VDDA = VDDD = 3 V VDDA = VDDD = 5 V D5 D4 D3 D2 D1 D0 Underflow <VDDA − 1.1 <VDDA − 1.06 0 0 0 0 0 0 0 VDDA − 1.1 VDDA − 1.06 0 0 0 0 0 0 1 . . 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . 62 . . 1 1 1 1 1 0 63 VDDA − 0.4 VDDA − 0.4 1 1 1 1 1 1 Overflow >VDDA − 0.4 >VDDA − 0.4 1 1 1 1 1 1 Table 2 Clamping input level (VCLPR, VCLPG and VCLPB) VCLPR, VCLPG AND VCLPB CLAMPING LEVEL Open-circuit(1) code 0 Vcode −9 to Vcode 20 code −9 to code 20 Note 1. Use capacitor ≥10 pF to VSSA. Table 3 Clamp and inputs RED, GREEN and BLUE; VDDA = VDDD = VDDO = 3 V SR or SG or SB CLAMP VCLPR, VCLPG or VCLPB Vi RED or GREEN or BLUE open VDDA − 1.1 V VCLP VCLP open VDDA − 1.1 V 0 VCLP VCLP code (VCLP) 0 1 1 DIGITAL OUTPUTS X(1) Note 1. Where X = don’t care. Table 4 Clamping characteristic related to TV signals PARAMETER MIN. TYP. MAX. UNIT Clamping time per line (signal active) 2.2 3.0 − µs Input signals clamped to correct level − 3 10 lines 1996 Jul 30 9 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth tCPH TDA8706A tCPL CLK tSU tMH SR SG SB CLAMP tCLPP OUTPUT DATA GREEN BLUE RED GREEN MBE859 td th Fig.3 AC characteristics select signals, clamp and output data. 1996 Jul 30 10 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth TDA8706A CLK SR SG SB tover RED ACTIVE tover GREEN ACTIVE tsu tover BLUE ACTIVE MBE860 Fig.4 Anti-overlap system for analog multiplexer. handbook, full pagewidth RED, GREEN, BLUE (SR, SG, SB inputs) digital outputs = 000000 1 CLAMP input 0 Fig.5 AC characteristics select signals; clamp and data. 1996 Jul 30 11 MBE861 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A INTERNAL PIN CONFIGURATIONS handbook, halfpage VDDA handbook, halfpage VDDO RLAD REGULATOR VRB D5 to D0 VSSO MGD134 VSSA MBE967 Fig.6 CMOS data outputs. Fig.7 VRB. V DDD handbook, halfpage 1/2V CLK DDD VSSD MLC860 Fig.8 CLK input. 1996 Jul 30 12 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A APPLICATION INFORMATION handbook, full pagewidth SR SG SB CLP VDDA VRB(1) 100 nF VSSA RED VSSA GREEN BLUE 1 24 2 23 3 22 4 21 5 20 19 6 TDA8706A 7 18 8 17 9 16 10 15 11 14 12 13 (2) VCLPR 100 nF VSSA VCLPB (2) 100 nF CLK VDDD VSSD VDDO D5 D4 D3 D2 D1 D0 VSSO VCLPG(2) MBE969 VSSA 100 nF VSSA The analog and digital supplies should be separated and decoupled. VRB must not be connected to VCLPR, VCLPB or VCLPG pins. For applications where the black level is clamped to code 0, VCLPR, VCLPB and VCLPG must be left open-circuit with their respective decoupling capacitors. In that event, they may also be connected together in order to use only one single decoupling capacitor. (1) VRB is decoupled to VSSA. Eventually an external regulator can be connected to VRB. (2) VCLPR, VCLPB and VCLPG are decoupled to VSSA. Eventually external voltages can be forced on VCLPR, VCLPB and VCLPG. Fig.9 Application diagram. 1996 Jul 30 13 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A PACKAGE OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT340-1 1996 Jul 30 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AG 14 o Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A SOLDERING SSOP Introduction Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Reflow soldering Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Reflow soldering techniques are suitable for all SO and SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. METHOD (SO AND SSOP) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering SO Repairing soldered joints Wave soldering techniques can be used for all SO packages if the following conditions are observed: Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1996 Jul 30 15 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Jul 30 16 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A NOTES 1996 Jul 30 17 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A NOTES 1996 Jul 30 18 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A NOTES 1996 Jul 30 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (1) TDA8706A_1 July 18, 1996 12:44 pm © Philips Electronics N.V. 1996 SCA51 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/30/01/pp20 Date of release: 1996 Jul 30 Document order number: 9397 750 00991