Philips Semiconductors Product specification Phase-locked loop NE/SE564 DESCRIPTION PIN CONFIGURATIONS The NE/SE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As shown in the Block Diagram, the NE/SE564 consists of a VCO, limiter, phase comparator, and post detection processor. D, N Packages V+ FEATURES • Operation with single 5V supply • TTL-compatible inputs and outputs • Guaranteed operation to 50MHz • External loop gain control • Reduced carrier feedthrough • No elaborate filtering needed in FSK applications • Can be used as a modulator • Variable loop gain (externally controlled) 1 16 TTL OUTPUT LOOP GAIN CONTROL 2 15 HYSTERESIS SET INPUT TO PHASE COMP FROM VCO 3 14 ANALOG OUT LOOP FILTER 4 13 FREQ. SET CAP LOOP FILTER 5 12 FREQ. SET CAP FM/RF INPUT 6 11 BIAS FILTER 7 10 V+ GND 8 9 VCO OUT 2 VCO OUT TTL TOP VIEW SR01025 APPLICATIONS Figure 1. Pin Configuration • High speed modems • FSK receivers and transmitters • Frequency Synthesizers • Signal generators • Various satcom/TV systems • pin configuration ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG # 16-Pin Plastic Small Outline (SO) Package 0 to +70°C NE564D SOT109-1 16-Pin Plastic Dual In-Line Package (DIP) 0 to +70°C NE564N SOT38-4 16-Pin Plastic Dual In-Line Package (DIP) -55 to +125°C SE564N SOT38-4 BLOCK DIAGRAM V+ 4 5 PHASE COMPARATOR LIMITER 6 14 1 2 DC RETRIEVER 3 7 AMPLIFIER 11 SCHMITT TRIGGER 16 9 POST DETECTION PROCESSOR VCO 10 12 15 8 13 SR01026 Figure 2. Block Diagram 1994 Aug 31 1 853-0908 13720 Philips Semiconductors Product specification Phase-locked loop NE/SE564 ABSOLUTE MAXIMUM RATINGS SYMBOL RATING UNITS Supply voltage Pin 1 Pin 10 14 6 V V IOUT Sink Max (Pin 9) and sourcing (Pin 11) 11 mA IBIAS Bias current adjust pin (sinking) 1 mA 600 mW V+ PARAMETER PD Power dissipation TA Operating ambient temperature NE SE TSTG °C °C °C 0 to +70 -55 to +125 Storage temperature range -65 to +150 NOTE: Operation above 5V will require heatsinking of the case. DC AND AC ELECTRICAL CHARACTERISTICS VCC = 5V; TA = 0 to 25°C; fO = 5MHz, I2 = 400µA; unless otherwise specified. LIMITS SYMBOL PARAMETER Maximum VCO frequency Lock range Capture range VCO frequency drift with temperature Demodulated output voltage Modulation frequency: 1kHz fO = 5MHz, input deviation: 2%T = 25°C 1%T = 25°C 1%T = 0°C 1%T = -55°C 1%T = 70°C 1%T = 125°C Supply current Output “1” output leakage current “0” output voltage MIN TYP 50 40 20 50 20 fO = 5MHz, TA = -55°C to +125°C TA = 0 to +70°C = 0 to +70°C fO = 5MHz, TA = -55°C to +125°C TA = 0 to +70°C VCC = 4.5V to 5.5V Demodulated output at operating voltage 1994 Aug 31 Input > 200mVRMS, R2 = 27Ω VCO frequency change with supply voltage Signal-to-noise ratio LIMITS SE564 NE564 MAX MIN TYP 65 45 60 70 30 80 40 70 UNITS MAX MHz % of fO 70 40 C1 = 91pF RC = 100Ω “Internal” AM rejection ICC C1 = 0 (stray) Input > 200mVRMS TA = 25°C TA = 125°C TA = -55°C TA = 0oC TA = 70°C VCO free-running frequency Distortion S/N TEST CONDITIONS 30 20 500 1500 300 800 30 % of fO 600 PPM/oC 500 4 5 6 3 8 16 8 28 14 6 10 12 16 3.5 16 8 5 6.5 MHz 3 8 % of fO mVRMS mVRMS mVRMS mVRMS mVRMS mVRMS 28 14 13 15 Deviation: 1% to 8% 1 1 % Std. condition, 1% to 10% dev. 40 40 dB Std. condition, 30% AM 35 35 dB Modulation frequency: 1kHz fO = 5MHz, input deviation: 1% VCC = 4.5V VCC = 5.5V 7 8 12 14 7 8 mVRMS mVRMS 12 14 VCC = 5V I1, I10 45 60 45 60 mA VOUT = 5V, Pins 16, 9 IOUT = 2mA, Pins 16, 9 IOUT = 6mA, Pins 16, 9 1 0.3 0.4 20 0.6 0.8 1 0.3 0.4 20 0.6 0.8 µA V V 2 Philips Semiconductors Product specification Phase-locked loop NE/SE564 TYPICAL PERFORMANCE CHARACTERISTICS Lock Range vs Signal Input 1000 8 6 IPIN = 400µA VCO Capacitor vs Frequency 2 106 IPIN = 0µA 2 105 2 CAPACITANCE pF INPUT SIGNAL LEVEL – mV 4 100 8 6 104 103 102 10 4 1 VCC 5V 2 .1 1 fo = 5MHz 102 10 103 104 105 FREQUENCY kHz 10 0.7 0.8 0.9 1.0 1.1 1.2 1.3 NORMALIZED LOCK RANGE 1.00 0.99 0.98 0.97 1.10 VCO FREQUENCY: 50MHz 1.05 1.00 0.95 NORMALIZED VCO FREQUENCY FREQUENCY: 50MHz 1.01 Typical Noirmalized VCO Frequency as a Function of Temperature Typical Noirmalized VCO Frequency as a Function of Pin 2 Bias Current NORMALIZED VCO FREQUENCY NORMALIZED VCO FREQUENCY Typical Noirmalized VCO Frequency as a Function of Pin 2 Bias Current 0.90 –400 –200 0 BIAS CURENT (µA), PIN 2 +200 BIAS CURRENT: — 200µA FREQUENCY: 5MHz 1.05 1.00 0.95 FREQUENCY: 500MHz BIAS CURRENT: — 200µA 0.90 0.96 –600µA 1.10 –600µA –400 –200 0 +200 +400 BIAS CURENT (µA), PIN 2 –50 –25 25 0 25 50 TEMPERATURE 75 100 125 (INoC) SR01027 Figure 3. Typical Performance Characteristics 1994 Aug 31 3 Philips Semiconductors Product specification Phase-locked loop NE/SE564 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VD – PHASE COMPARATOR’S OUTPUT VOLTAGE IN mV 800 VCO FREQUENCY IN MHz IBIAS = 200µA 600 IBIAS = 400µA IBIAS = 800µA 1.6 IBIAS = 0µA IBIAS = 800µA IBIAS = 00µA 400 1.4 fo = 1.0MHz 200 1.2 0 40 60 100 120 140 –400 160 –200 200 0 – PHASE ERROR IN DEGREES –200 400 600 800 VDIN mV .8 .6 –400 –600 –800 VCO Output Frequency as a Function of Input Voltage and Bias Current (KO) Variation of the Comparator’s Output Voltage vs Phase Error and Bias Current (KD) SR01028 Figure 4. Typical Performance Characteristics (cont.) TEST CIRCUIT +5V 1K R3 R1 INPUT C3 1 6 0.1µF 10 2 16 9 3 VCO OUYPUT DEMODULATED OUTPUT 14 0.1µF 564 R2 4 13 5 12 430pF C2 390 1K 7 C2 15 pF C1 R2 8 430pF SR01029 Figure 5. Test Circuit 1994 Aug 31 4 Philips Semiconductors Product specification Phase-locked loop NE/SE564 FUNCTIONAL DESCRIPTION Phase Comparator Section The phase detection processor consists of a doubled-balanced modulator with a limiter amplifier to improve AM rejection. Schottky-clamped vertical PNPs are used to obtain TTL level inputs. The loop gain can be varied by changing the current in Q4 and Q15 which effectively changes the gain of the differential amplifiers. This can be accomplished by introducing a current at Pin 2. (Figure 6) The NE564 is a monolithic phase-locked loop with a post detection processor. The use of Schottky clamped transistors and optimized device geometries extends the frequency of operation to greater than 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. Post Detection Processor Section The post detection processor consists of a unity gain transconductance amplifier and comparator. The amplifier can be used as a DC retriever for demodulation of FSK signals, and as a post detection filter for linear FM demodulation. The comparator has adjustable hysteresis so that phase jitter in the output signal can be eliminated. The output of the PLL can be written as shown in the following equation: VO = (fIN - fO) KVCO (1) KVCO = conversion gain of the VCO As shown in the equivalent schematic, the DC retriever is formed by the transconductance amplifier Q42 - Q43 together with an external capacitor which is connected at the amplifier output (Pin 14). This forms an integrator whose output voltage is shown in the following equation: fIN = frequency of the input signal fO = free-running frequency of the VCO The process of recovering FSK signals involves the conversion of the PLL output into logic compatible signals. For high data rates, a considerable amount of carrier will be present at the output of the PLL due to the wideband nature of the loop filter. To avoid the use of complicated filters, a comparator with hysteresis or Schmitt trigger is required. With the conversion gain of the VCO fixed, the output voltage as given by Equation 1 varies according to the frequency deviation of fIN from fO. Since this differs from system to system, it is necessary that the hysteresis of the Schmitt trigger be capable of being changed, so that it can be optimized for a particular system. This is accomplished in the 564 by varying the voltage at Pin 15 which results in a change of the hysteresis of the Schmitt trigger. VO = gM C2 (3) VINdt gM = transconductance of the amplifier C2 = capacitor at the output (Pin 14) VIN = signal voltage at amplifier input With proper selection of C2, the integrator time constant can be varied so that the output voltage is the DC or average value of the input signal for use in FSK, or as a post detection filter in linear demodulation. For FSK signals, an important factor to be considered is the drift in the free-running frequency of the VCO itself. If this changes due to temperature, according to Equation 1 it will lead to a change in the DC levels of the PLL output, and consequently to errors in the digital output signal. This is especially true for narrowband signals where the deviation in fIN itself may be less than the change in fO due to temperature. This effect can be eliminated if the DC or average value of the signal is retrieved and used as the reference to the comparator. In this manner, variations in the DC levels of the PLL output do not affect the FSK output. The comparator with hysteresis is made up of Q49 - Q50 with positive feedback being provided by Q47 - Q48. The hysteresis is varied by changing the current in Q52 with a resulting variation in the loop gain of the comparator. This method of hysteresis control, which is a DC control, provides symmetric variation around the nominal value. Design Formula The free-running frequency of the VCO is shown by the following equation: VCO Section fO ≅ 1 22 RC (C1 + CS) (4) Due to its inherent high-frequency performance, an emitter-coupled oscillator is used in the VCO. In the circuit, shown in the equivalent schematic, transistors Q21 and Q23 with current sources Q25 - Q26 form the basic oscillator. The approximate free-running frequency of the oscillator is shown in the following equation: RC = 100Ω 1 fO ≅ 22 RC (C1 + CS) The loop filter diagram shown is explained by the following equation: C1 = external cap in farads CS = stray capacitance (2) fS = RC = R19 = R20 = 100Ω (INTERNAL) C1 = external frequency setting capacitor R = R12 = R13 = 1.3kΩ (Internal)* CS = stray capacitance By adding capacitors to Pins 4 and 5, a pole is added to the loop transfer at Variation of VD (phase detector output voltage) changes the frequency of the oscillator. As indicated by Equation 2, the frequency of the oscillator has a negative temperature coefficient due to the monolithic resistor. To compensate for this, a current IR with negative temperature coefficient is introduced to achieve a low frequency drift with temperature. 1994 Aug 31 1 (First Order) 1 + sRC3 ω= 5 1 RC3 NOTE: *Refer to Figure 6. (5) Philips Semiconductors Product specification Phase-locked loop NE/SE564 EQUIVALENT SCHEMATIC SR01030 Figure 6. Equivalent Schematic LOCK RANGE ADJUSTMENT I2 0.01µF LOOP FILTER 0.01µF 16 0.47µF FM INPUT fO = 5MHz 11 4 5 1k fM = 1kHz BIAS FILTER 2 6 7 15 564 .01µF 3 ANALOG OUT 1kHz POST DETECTION FILTER 14 0.1µF 1 8 10 9 12 13 80pF fO = 5MHz FREQUENCY SET CAP 1k 5V 5V Figure 7. FM Demodulator at 5V 1994 Aug 31 6 SR01031 Philips Semiconductors Product specification Phase-locked loop NE/SE564 APPLICATIONS 5V FM Demodulator FINE FREQUENCY ADJUSTMENT I2 The NE564 can be used as an FM demodulator. The connections for operation at 5V and 12V are shown in Figures 7 and 8, respectively. The input signal is AC coupled with the output signal being extracted at Pin 14. Loop filtering is provided by the capacitors at Pins 4 and 5 with additional filtering being provided by the capacitor at Pin 14. Since the conversion gain of the VCO is not very high, to obtain sufficient demodulated output signal the frequency deviation in the input signal should be 1% or higher. 2k MODULATING INPUT 1kHz 16 0.47µF 1kHz 2 11 4 5 6 1k 7 15 564 .01µF 3 Modulation Techniques 14 1 The NE564 phase-locked loop can be modulated at either the loop filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure 9. The approximate modulation frequency can be determined from the frequency conversion gain curve shown in Figure 10. This curve will be appropriate for signals injected into Pins 4 and 5 as shown in Figure 9. 8 10 9 12 13 80pF fO = 5MHz FREQUENCY SET CAP 5V 1k 5V I2 LOCK RANGE ADJUSTMENT 0.01µF MODULATED OUTPUT (TTL) SR01033 Figure 9. Modulator LOOP FILTER 0.01µF FM INPUT fO = 5MHz fM = 1kHz 16 0.47µF 2 11 4 5 6 1k ANALOG OUT 1kHz 15 7 BIAS FILTER The lock range graph indicates that the +1.0MHz frequency deviations will be within the lock range for input signal levels greater than approximately 50mV with zero Pin 2 bias current. (While strictly this figure is appropriate only for 50MHz, it can be used as a guide for lock range estimates at other fO’ frequencies). 564 .01µF 3 14 0.1µF 1 8 10 9 12 The hysteresis was adjusted experimentally via the 10kΩ potentiometer and 2kΩ bias arrangement to give the waveshape shown in Figure 12 for 20k, 500k, 2M baud rates with square wave FSK modulation. Note the magnitude and phase relationships of the phase comparators’ output voltages with respect to each other and to the FSK output. The high-frequency sum components of the input and VCO frequency also are viable as noise on the phase comparator’s outputs. POST DETECTION FILTER 13 80pF fO = 5MHz FREQUENCY SET CAP .01µF 200 1k 12V OUTLINE OF SETUP PROCEDURE SR01032 1. Determine operating frequency of the VCO: IF÷ N in feedback loop, then fO = N x fIN. Figure 8. FM Demodulator at 12V FSK Demodulation The 564 PLL is particularly attractive for FSK demodulation since it contains an internal voltage comparator and VCO which have TTL compatible inputs and outputs, and it can operate from a single 5V power supply. Demodulated DC voltages associated with the mark and space frequencies are recovered with a single external capacitor in a DC retriever without utilizing extensive filtering networks. An internal comparator, acting as a Schmitt trigger with an adjustable hysteresis, shapes the demodulated voltages into compatible TTL output levels. The high-frequency design of the 564 enables it to demodulate FSK at high data rates in excess of 1.0M baud. 2. Calculate value of the VCO frequency set capacitor: CO ≅ 3. Set I2 (current sinking into Pin 2) for ≅ 100µA. After operation is obtained, this value may be adjusted for best dynamic behavior, V 1.3V and replace with fixed resistor value of R2 = CC . IB 2 4. Check VCO output frequency with digital counter at Pin 9 of device (loop open, VCO to φ det.). Adjust CO trim or frequency adj. Pins 4 - 5 for exact center frequency, if needed. Figure 10 shows a high-frequency FSK decoder designed for input frequency deviations of +1.0MHz centered around a free-running frequency of 10.8MHz. the value of the timing capacitance required was estimated from Figure 8 to be approximately 40pF. A trimmer capacitor was added to fine tune fO’ 10.8MHz. 1994 Aug 31 1 2200 fO 5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6 with two-channel scope. Lock should occur with ∆φ3 - 6 equal to 90o (phase error). 7 Philips Semiconductors Product specification Phase-locked loop NE/SE564 50% in duty cycle, DC offsets will occur in the loop which tend to create an artificial or biased VCO. 6. If pulsed burst or ramp frequency is used for input signal, special loop filter design may be required in place of simple single capacitor filter on Pins 4 and 5. (See PLL application section) 8. For multiplier circuits where phase jitter is a problem, loop filter capacitors may be increased to a value of 10 - 50µF on Pins 4, 5. Also, careful supply decoupling may be necessary. This includes the counter chain VCC lines. 7. The input signal to Pin 6 and the VCO feedback signal to Pin 3 must have a duty cycle of 50% for proper operation of the phase detector. Due to the nature of a balanced mixer if signals are not BIAS ADJ +5V 0.22µF 0.22µF 10k 10k 2k 1.2k HYSTERESIS ADJUST FSK OUTPUT 2k 1 FSK INPUT 10 15 6 0.1µF 1k 14 7 1k *NOTE: Use R9-11 only if rise time is critical. 16 2 0.1µF 510Ω +5V 3 10µF/8V NE564 9 12 11 13 4 8 *510Ω 0–20pF 33pF 300pF 5 300pF SR01034 Figure 10. 10.8MHz FSK Decoder Using the 564 1994 Aug 31 8 Philips Semiconductors Product specification Phase-locked loop NE/SE564 SR01035 Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs +5V BIAS ADJUST .47µF 10k I2 .47µF CER. CER. 2k .33µF 2 INPUT SIGNAL 1 10 4 LOOP FILTER 5 6 fT 11 NE564 1kΩ .47µF .33µF *510Ω DET. 7 VCO OUTPUT 9 VCO 3 8 12 13 NxfT CO *NOTE: Use R9-11 only if rise time is critical. f = NxfT ÷N Figure 12. NE564 Phase-Locked Frequency Multiplier 1994 Aug 31 510Ω 9