Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function DESCRIPTION ADC0820 PIN CONFIGURATION By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power. The half-flash technique consists of 31 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. D, F, N Packages 1 20 VDD DB0 2 19 NC DB1 3 18 OFL DB2 4 17 DB7 DB3 5 16 DB6 VIN The input to the ADC0820 is tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold for signals slewing at less than 100mV/µs. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic. WR/RDY 6 15 DB5 MODE 7 14 DB4 RD 8 13 CS INT 9 12 VREF(+) 10 11 VREF(–) GND FEATURES • Built-in track-and-hold function • No missing codes • No external clocking • Single supply—5VDC • Easy interface to all microprocessors, or operates stand-alone • Latched 3-State outputs • Logic inputs and outputs meet both MOS and TTL voltage level TOP VIEW APPLICATIONS • Microprocessor-based monitoring and control systems • Transducer/µP interface • Process control • Logic analyzers • Test and measurement specifications • Operates ratiometrically or with any reference value equal to or less than VDD • 0V to 5V analog input voltage range with single 5V supply • No zero- or full-scale adjust required • Overflow output available for cascading • 0.3″ standard width 20-pin DIP ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG # 20-Pin Plastic Dual In-Line Package (DIP) DESCRIPTION 0 to +70°C ADC0820CNEN 0408B 20-Pin Plastic Small Outline (SO) package 0 to +70°C ADC0820CNED 1021B August 31, 1994 568 853-1631 13721 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 BLOCK DIAGRAM VREF(+) VREF(–) OFL DB7 DB6 DB5 DB4 OFL 4–BIT FLASG ADC (4MSBs) VIN + VREF(+) – ∑ OUTPUT LATCH AND THREE–STATE BUFFERS 4–BIT DAC VREF(–) VREF (+) 16 DB3 4–BIT FLASG ADC (4LSBs) DB2 DB1 DB0 VREF(–) TIMING AND CONTROL CIRCUITRY MODE WR/RDY CS INT RD PIN DESCRIPTION PIN NO SYMBOL DESCRIPTION 1 VIN Analog input; range=GND≤VIN≤VDD 2 DB0 3-state data output—Bit 0 (LSB) 3 DB1 3-state data output—Bit 1 4 DB2 3-state data output—Bit 2 5 DB3 3-state data output—Bit 3 6 WR/RDY WR-RD Mode WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (see Figures 3a and 3b). RD Mode RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (see Figure 1). 7 Mode Mode: Mode selection input—it is internally tied to GND through a 30µA current source. RD Mode: When mode is Low. WR-RD Mode: When mode is High. 8 RD WR-RD Mode With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (TI ~ 800ns). If this is done, the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b). RD Mode With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see Figure 1). 9 INT WR-RD Mode INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go Low ~ 800ns (the preset internal time out, tI) after the rising edge of WR (see Figure 3a); or INT will go Low after the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of RD or CS (see Figures 3a and 3b). August 31, 1994 569 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 PIN DESCRIPTION (Continued) PIN NO SYMBOL DESCRIPTION RD Mode INT going Low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or CS (see Figure 1). 10 GND Ground 11 VREF(-) The bottom of resistor ladder, voltage range: GND≤VREF(-)≤VREF(+) 12 VREF(+) The top of resistor ladder, voltage range: VREF(-)≤VREF(+)≤VDD. 13 CS CS must be Low in order for the RD or WR to be recognized by the converter. 14 DB4 3-State data output—Bit 4 15 DB5 3-State data output—Bit 5 16 DB6 3-State data output—Bit 6 17 DB7 3-State data output—Bit 7 (MSB) 18 OFL Overflow output—if the analog input is higher than the VREF(+)- LSB, OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). It is always active and never becomes 3-state. 19 NC No connection 20 VDD Power supply voltage ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VDD PARAMETER RATING UNIT 7 V Logic control inputs -0.2 to VDD+0.2 V Voltage at other inputs and output -0.2 to VDD+0.2 V -65 to +150 °C N package 1690 mW D package 1390 mW °C Supply voltage TSTG Storage temperature range PD Maximum power dissipation3 TA=25°C(still-air) TSOLD Lead temperature (soldering, 10sec) 300 TA Operating ambient temperature range TMIN≤TA≤TMAX ADC0820CNEN/CNED 0 to +70 NOTES: 1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. 2. All voltages are measured with respect to GND, unless otherwise specified. 3. Derate above 25°C at the following rates: N package at 13.5mW/°C D package at 11.1mW/°C August 31, 1994 570 °C Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 DC ELECTRICAL CHARACTERISTICS RD mode (Pin 7=0), VDD=5V, VREF(+)=5V, and VREF(-)=GND, unless otherwise specified. Limits apply from TMIN to TMAX. SYMBOL PARAMETER TEST CONDITIONS Resolution Unadjusted error1 LIMITS Min Typ3 8 8 ADC0820C 8 bits ±1 LSB Reference resistance 4 kΩ VREF(+) Input voltage5 VREF(-) VDD V VREF(-) Input voltage GND VREF(+) V VIN Input voltage5 GND-0.1 VDD+0.1 V -3 3 µA ±1/4 LSB Power supply sensitivity CS=VDD VIN=VDD VIN=GND 1.6 UNIT RREF Maximum analog input leakage current 1 Max ±1/16 VDD=5V±5% CS, WR, RD 2.0 VDD Mode 3.5 VDD CS, WR, RD GND 0.8 Mode GND 1.5 VIN(1) Logical “1” input voltage VDD=5.25V VIN(0) Logical “0” input voltage VDD=4.75V VIN(1)=5V; CS, RD 1 IIN(1) Logical “1” input current VIN(1)=5V; WR 3 IIN(0) Logical “0” input current VIN(0)=0V; CS, RD, WR, Mode -1 VDD=4.75V, IOUT=-360µA; 2.4 4.6 4.5 4.74 VIN(1)=5V; Mode VOUT(1) Logical “1” output voltage 30 V µA 200 µA DB0-DB7, OFL, INT VDD=4.75V, IOUT=-10µA V V DB0-DB7, OFL, INT VOUT(0) Logical “0” output voltage IOZ 3-state output current VDD=4.75V, IOUT=1.6mA; DB0-DB7, OFL, INT, RDY 0.2 VOUT=5V; DB0-DB7, RDY ISOURCE 0.4 3 µA VOUT=0V; DB0-DB7, RDY -3 VOUT=0V, DB0-DB7, OFL 6 12 INT 4.5 8 VOUT=5V; DB0-DB7, OFL, INT, RDY 7 20 Output source current ISINK Output sink current IDD Supply current VDD Range August 31, 1994 V mA CS=WR=RD=0 6 4.5 571 mA 15 mA 5.5 V Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 AC ELECTRICAL CHARACTERISTICS VDD = 5V, tR = tF = 20ns, VREF(+) = 5V, VREF(-) = 0V, and TA = 25°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS4 Min Typ3 Max UNIT tCRD Conversion time for RD mode Mode=0, Figure 1 1.6 2.5 µs tACCO Access time (delay from falling edge of RD to output valid) Mode=0, Figure 1 tCRD+20 tCRD+50 ns tCWR-RD Conversion time for WR-RD mode 1.52 µs tWR Write time tRD Read time tACC1 tACC2 Min Max Min Access time (delay from falling edge of RD t o output valid) Access time (delay from falling edge of RD t o output valid) Mode=VDD, tWR=600ns, tRD=600ns; Figures 3a and 3b Mode=VDD, Figures 3a and 3b2 Mode=VDD, Figures 3a and 3b2 600 ns 50 600 µs ns Mode=VDD, tRD<tI; Figure 3b, CL=15pF 190 280 CL=100pF 210 320 Mode=VDD, tRD>tI; Figure 3a, CL=15pF 70 120 ns CL=100pF 90 150 ns Mode=VDD; Figures 2 and 3a, CL=50pF 800 1300 ns RL=1kΩ, CL=10pF 100 200 ns tRD+200 tI tRD+290 ns ns ns tI Internal comparison time t1H, t0H Three-state control (delay from rising edge of RD to Hi-Z state) tINTL Delay from rising edge of WR to falling edge of INT Mode=VDD, CL=50pF tRD>tI; Figure 3a tRD<tI; Figure 3b tINTH Delay from rising edge of RD to rising edge of INT Figures 1, 3a, and 3b, CL=50pF 125 225 ns tINTHWR Delay from rising edge of WR to rising edge of INT Figure 2, CL=50pF 175 270 ns tRDY Delay from CS to RDY Figure 1, CL=50pF, Mode=0 50 100 ns tID Delay from INT to output valid Figure 2 20 50 ns Mode=VDD, tRD<tI; Figure 3b 200 290 ns tRI Delay from RD to INT tP Delay from end of conversion to next conversion SR Slew rate, tracking 0.1 V/µs CVIN Analog input capacitance 45 pF COUT Logic output capacitance 5 pF CIN Logic input capacitance 5 pF Figures 1, 2, 3a, and 3b2 500 NOTES: 1. Unadjusted error includes offset, full-scale, and linearity errors. 2. Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. 3. Typical values are at 25°C and represent most likely parametric norm. 4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. 5. VREF and VIN must be applied after VCC has been turned on to prevent possibility of latching. August 31, 1994 572 ns Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 3-STATE TEST CIRCUITS AND WAVEFORMS t1H VDD RD VCC RD GND DATA OUTPUT CS CL 10pF tR 90% 50% 10% t1H 1K VOH DATA OUTPUTS 90% GND tR = 20ns t0H VCC VCC tR VDD RD 1k RD GND DATA OUTPUT CS 90% 50% 10% t0H DATA OUTPUTS CL 10pF VDD 10% GND MODE = LOW CS RD tP RDY (OUTPUT) WITH EXTERNAL PULL–UPtINT R, C H tRDY INT tCRD VALID DATA DB0–DB7 OFL tACCO t1H, 0H Figure 1. RD Mode August 31, 1994 573 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 MODE = LOW CS x RD = LOW tWR WR tP tINT H WR INT tI tID VALID DATA DB0–DB7 Figure 2. Stand-Alone Mode MODE = HIGH CS tWR WR (INPUT) tP RD tRD INT tINT tINT H L (TI) VALID DATA DB0–DB7 tACC2 t1H, t0H a. WR-RD Mode (tRD > tI) CS tWR WR tP RD tRD tRI INT tINT tINT H L (TI) VALID DATA DB0–DB7 tACC1 b. WR-RD Mode (tRD < tI) Figure 3. WR-RD Mode August 31, 1994 574 t1H, t0H Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 In the first cycle, one input switch and the inverter’s feedback switch (Figure 4a) are closed. In this interval, C is charged to the connected input (V1) less the inverter’s bias voltage (VS, approximately 1.6V). In the second cycle (Figure 4b), these two switches are opened and the other (V2) input’s switch is closed. The input capacitor now subtracts its stored voltage from the second input and the difference is amplified by the inverter’s open loop gain. The inverter’s input (VS’) becomes FUNCTIONAL DESCRIPTION General Operation The ADC0820 uses two 4-bit flash A/D converters to make an 8-bit measurement (Block Diagram). Each flash ADC is made up of 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. To take a full 8-bit reading, one flash conversion is done to provide the 4 most significant data bits (via the MS flash ADC). Driven by the 4 MSBs, an internal DAC recreates an analog approximation of the input voltage. This analog signal is then subtracted from the input, and the difference voltage is converted by a second 4-bit flash ADC (the LS ADC), providing the 4 least significant bits of the output data word. V S V S (V2 – V1) C C CS and the output will go High or Low depending on the sign of V’S’-VS. The actual circuitry used in the ADC0820 is a simple but important expansion of the basic comparator described above. By adding a second capacitor and another set of switches to the input (Figure 5), the scheme can be expanded to make dual differential comparisons. In this circuit, the feedback switch and one input switch on each capacitor (Z switches) are closed in the zeroing cycle. A comparison is then made by connecting the second input on each capacitor (S switches) and opening all of the other switches. The change in voltage at the inverter’s input, as a result of the change in charge on each input capacitor, will now depend on both input signal differences. The internal DAC is actually a subsection of the MS flash converter. This is accomplished by using the same resistor ladder for the A/D as well as for generating the DAC signal. The DAC output is actually the tap on the resistor ladder which most closely approximates the analog input. In addition, the “sampled data” comparators used in the ADC0820 provide the ability to compare the magnitudes of several analog signals simultaneously, without using input summing amplifiers. This is especially useful in the LS flash ADC, where the signal to be converted is an analog difference. The Sampled-Data Comparator Each comparator in the ADC0820 consists of a CMOS inverter with a capacitively-coupled input (Figure 4). Analog switches connect the two comparator inputs to the input capacitor (C) and also connect the inverter’s input and output. This device in effect now has one differential input pair. A comparison requires two cycles, one for zeroing the comparator, and another for making the comparison. Architecture In the ADC0820, 15 comparators are used in the MS and LS 4-bit flash A/D converters. The MS (most significant) flash ADC also has one additional comparator to detect input over-range. These two sets of comparators operate alternately, with one group in its zeroing cycle while the other is comparing. V1 V1 C C VO A VS CS V2 VO A VS CS V2 • VO = VS • V ON C = V1 – VB • CS = SATRAY INPUT NODE CAPACITOR • VS = INVERTER INPUT BIAS VOLTAGE • VS’ – VS = (V2 – V1) –A C C + CS • VO’ = [CV2 – CV1] C + CS • VO’ IS DEPENDENT ON V2–V1 a. Zeroing Phase b. Compare Phase Figure 4. Sampled Data Comparator Z R LADDER (V1) Z C1 S VIN (V2) A Z ANALOG GND (V3) C2 CS VO VS VO = S 1/2 LSB (V4) = –A C1 + C2 + CS –A C1 + C2 + CS [C1 (V2 – V1) + C2 (V4–V3)] [ ∆QC1 Figure 5. ADC0820 Comparator (From MS Flash ADC) August 31, 1994 575 + ∆QC2] Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function To start a conversion in the WR-RD mode, the WR line is brought Low. At this instant the MS comparators go from zeroing to comparison mode (Figure 8). When WR is returned High after at least 600ns, the output from the first set of comparators (the first flash) is decoded and latched. At this point the two 4-bit converters change modes and the LS (least significant) flash ADC enters its compare cycle. No less than 600ns later, the RD line may be pulled Low to latch the lower four data bits and finish the 8-bit conversion. When RD goes Low, the flash A/Ds change state once again in preparation for the next conversion. ADC0820 CS RD RDY INT Figure 8 also outlines how the converter’s interface timing relates to its analog input (VIN). In WR-RD mode, VIN is measured while WR is Low. In RD mode, sampling occurs during the first 800ns of RD. Because of the input connections to the ADC0820’s LS and MS comparators, the converter has the ability to sample VIN at one instant, despite the fact that two separate 4-bit conversions are being done. More specifically, when WR is Low the MS flash is in compare mode (connected to VIN, and the LS flash is in zero mode (also connected to VIN). Therefore both flash ADCs sample VIN at the same time. DB0–DB7 a. RD Mode (Pin 7 is Low) CS WR Digital Interface RB The ADC0820 has two basic interface modes which are selected by strapping the Mode pin High or Low. INT RD Mode (Figure 6a) With the Mode pin grounded, the converter is set to Read mode. In this configuration, a complete conversion is done by pulling RD Low until output data appears. An INT line is provided which goes Low at the end of the conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system Transfer Acknowledge signal. DB0–DB7 b. WR-RD Mode (Pin 7 is High and tRD < tI) When in RD mode, the comparator phases are internally triggered. At the falling edge of RD, the MS flash converter goes from zero to compare mode and the LS ADC’s comparators enter their zero cycle. After 800ns, data from the MS flash is latched and the LS flash ADC enters compare mode. Following another 800ns, the lower four bits are recovered. CS WR RB WR Then RD Mode (Figures 6b and c) With the Mode pin tied High, the A/D will be set up for the WR-RD mode. Here, a conversion is started with the WR input; however, there are two options for reading the output data which relate to interface timing. If an interrupt-driven scheme is desired, the user can wait for INT to go Low INT DB0–DB7 c. WR-RD Mode (Pin 7 is High and tRD > tI) Figure 6. August 31, 1994 576 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function before reading the conversion result. INT will typically go Low 800ns after WR’s rising edge. However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a Read after only 600ns. If this is done, INT will immediately go Low and data will appear at the outputs. ADC0820 This reference flexibility lets the input span not only be varied, but also offset from zero. The voltage at VREF(-) sets the input level which produces a digital output of all zeroes. Though VIN is not itself differential, the reference design affords nearly differential-input capability for most measurement applications. Figure 9 shows some of the configurations that are possible. Stand-Alone (Figure 7) For stand-alone operation in WR-RD mode, CS and RD can be tied Low and a conversion can be started with WR. Data will be valid approximately 800ns following WR’s rising edge. Input Current Due to the unique conversion techniques employed by the ADC0820, the analog input behaves somewhat differently than in conventional devices. The A/D’s sampled data comparators take varying amounts of input current depending on which cycle the conversion is in. Other Interface Considerations In order to maintain conversion accuracy, WR has a maximum width spec of 50µs. When the MS flash ADC’s sampled data comparators are in comparison mode (WR is Low), the input capacitors (C, Figure 5) must hold their charge. Switch leakage can cause errors if the comparator is left in this phase for too long. The equivalent input circuit of the ADC0820 is shown in Figure 10a. When a conversion starts (WR Low, WR-RD mode), all input switches close, connecting VIN to 31 1pF capacitors. Although the two 4-bit flash circuits are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because the MS flash converter is connected to the input during its compare interval and the LS flash is connected to the input during its zeroing phase. In other words, the LS ADC uses VIN as its zero-phase input. Since the MS flash ADC enters its zeroing phase at the end of a conversion, a new conversion cannot be started until this phase is complete. The minimum spec for this time is 500ns (tP in Figures 1, 2, 3a, and 3b). The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5kΩ to 10kΩ). In addition, about 12pF of input stray capacitance must also be charged. For large source resistances, the analog input can be modeled as an RC network as shown in Figure 10b. As RS increases, it will take longer for the input capacitance to charge. ANALOG CONSIDERATIONS Reference and Input The two VREF inputs of the ADC0820 are fully differential and define the zero- to full-scale input range of the A/D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN(+) and VIN(-). By reducing VREF(VREF=VREF(+) -VREF(-)) to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF=2V, then 1 LSB=7.8mV). The input/reference arrangement also facilitates ratiometric operation and, in many cases, the chip power supply can be used for transducer power as well as the VREF source. In RD mode, the input switches are closed for approximately 800ns at the start of the conversion. In WR-RD mode, the time that the switches are closed to allow this charging is the time that WR is Low. Since other factors force this time to be at least 600ns, input time constants of 100ns can be accommodated without special consideration. Typical total input capacitance values of 45pF allow RS to be 1.5kΩ without lengthening WR to give VIN more time to settle. CS LOW RD LOW Input Filtering It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/D’s performance in most cases. In effect, the ADC0820 does not “look” at the input when these transients occur. The comparators’ outputs are not latched while WR is Low, so at least 600ns will be provided to charge the ADC’s input capacitance. It is WR INT DB0–DB7 Figure 7. WR-RD Mode (Pin 7 is High) Stand-Alone Operation August 31, 1994 577 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 WR 600ns • MS COMPARATORS ZERO TO REFERENCE LADDER. • LS COMPARATORS FLOAT • MS COMPARATORS COMPARE VIN TO THEIR REFERENCE LADDER TAP. THE COMPARATOR VIN • VLADDER TAP. • LS COMPARATORS ZERO TO VIN THE COMPARATOR’S INPUT CAPACTORS TRACK VIN. • LS COMPARATORS OUTPUTS ARE LATCHED AND CAN BE READ • MS COMPARATORS OUT– PUTS ARE LATCHED. THE MS DAC IS SET. THE MS COMPARATOR FLOATS. • LS COMPARATORS COM– PARE LSB SECTION OF REF– ERENCE LADDER • MS COMPARATORS RE TURN TO ZERO MODE. Figure 8. Operating Sequence (WR-RD Mode) VIN(+) IN+ VIN(+) IN+ VIN(–) GND VIN(–) GND GND 1.2k 1.2k REF (+) 5V IN+ VIN(+) 5V REF (+) 5V REF (+) 2.5V 2.5V REF(–) REF(–) VIN(–) REF(–) • CURRENT PATH MUST STILL EXIST FROM VIN(–) TO GROUND a. External Reference 2.5V Full-Scale b. Power Supply as Reference Figure 9. Analog Input Options August 31, 1994 578 c. Input not Referred to GND Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function RON ≈12pF RS ADC0820 1pF RON VIN RS TO LSB R–LADDER 1pF 350 VIN CS 12pF 15 LSB COMPARATORS RON RON 1pF TO LSB R–LADDER 1pF b. a. Figure 10. August 31, 1994 579 31pF Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function therefore not necessary to filter out these transients by putting an external cap on the VIN terminal, if an input amplifier that can settle within 600ns is used to drive the input. The NE530 is a suitable op amp for driving the input of the ADC0820. ADC0820 Input signals with slew rates typically below 100mV/µs can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the ADC0820’s loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. An SAR type converter with a conversion time as fast as 1µs would still not be able to measure a 5V, 1kHz sine wave without the aid of an external sample-and-hold. The ADC0820, with no such help, can typically measure 5V, 7kHz waveforms. Inherent Sample-Hold Another benefit of the ADC0820’s input mechanism is its ability to measure a variety of high-speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain at least 1/2LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for many high-speed signals, this signal must be externally sampled, and held stationary during the conversion. VDD Sampled data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is 1.5µs, the time through which VIN must be 1/2LSB stable is much smaller. Since the MS flash ADC uses VIN as its “compare” input and the LS ADC uses VIN as its “zero” input, the ADC0820 only “samples” VIN when WR is Low. Even though the two flashes are not done simultaneously, the analog signal is measured at one instant. The value of VIN approximately 100ns after the rising edge of WR (100ns due to internal logic propagation delay) will be the measured value. 0.1µF 47µF VREF VIN 40k – CS VIN 27k + +5V WR 12k RD +5V +5V INT VREF(+) VDD DB7 0.1µF 47µF VREF(–) DB0 GND MODE Figure 12. Telecom A/D Converter August 31, 1994 MODE DB7 VREF(–) GND DB0 Figure 11. 8-Bit Resolution Configuration 25k VIN (+4VCC, 3kHz MAX) INT RDY VREF(+) CS VIN RD VDD +5V 580 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function +5V VDD 0.1µF 47µF MODE ADC0820 CS CS WR WR RD RD D8 VREF(+) VREF VIN VIN DB7 DB0 D0–D7 VREF(–) 1k GND OFL VDD CS 5k +5V 1k MODE WR RD VREF(+) VIN DB7 DB0 VREF(–) GND OFL Figure 13. 9-Bit Resolution Configuration August 31, 1994 581