PHILIPS S87C652-4A44

INTEGRATED CIRCUITS
87C652/87C654
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
Product specification
Replaces data sheets 87C652 of 1998 May 01 and 87C654 of 1998 May 01
IC20 Data Handbook
1999 Jul 23
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
DESCRIPTION
PIN CONFIGURATIONS
The 87C652/87C654 single-chip 8-Bit
microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
87C652/87C654 has the same instruction
set as the 80C51. Three versions of the
derivative exist:
80C652—ROMless
83C652/83C654—8 Kbyte, 16 Kbyte ROM
87C652/87C654—8 Kbyte, 16 Kbyte OTP
FEATURES
• 80C51 central processing unit
• 16k × 8 EPROM or 8k x 8 EPROM
The ROMless and ROM are in separate
datasheets.
This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 87C654 contains a non-volatile
16k × 8 EPROM and the 87C652 contains an
8k x 8 EPROM. Both have a volatile 256 × 8
read/write data memory, four 8-bit I/O ports,
two 16-bit timer/event counters (identical to
the timers of the 80C51), a multi-source,
two-priority-level, nested interrupt structure,
an I2C interface, UART and on-chip oscillator
and timing circuits. For systems that require
extra capability, the 87C652/87C654 can be
expanded using standard TTL compatible
memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 0.75 µs and 40%
in 1.5 µs. Multiply and divide instructions
require 3 µs.
expandable externally to 64k bytes
• 256 × 8 RAM, expandable externally to
P1.0
1
40 VCC
P1.1
2
39 P0.0/AD0
P1.2
3
38 P0.1/AD1
P1.3
4
37 P0.2/AD2
P1.4
5
36 P0.3/AD3
P1.5
6
35 P0.4/AD4
SCL/P1.6
7
34 P0.5/AD5
SDA/P1.7
8
33 P0.6/AD6
RST
9
RxD/P3.0 10
TxD/P3.1 11
64k bytes
• Two standard 16-bit timer/counters
• Four 8-bit I/O ports
• I2C-bus serial I/O port with byte oriented
master and slave functions
• Full-duplex UART facilities
• Power control modes
PLASTIC
DUAL
IN-LINE
PACKAGE
• Extended temperature range
• OTP package available
• Two speed ranges
31 EA/VPP
30 ALE/PROG
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2
18
23 P2.2/A10
XTAL1
19
22 P2.1/A9
VSS
20
21 P2.0/A8
– Idle mode
– Power-down mode
32 P0.7/AD7
SU00259
– 16 MHz
– 20 MHz
ORDERING INFORMATION
EPROM
TEMPERATURE RANGE °C
C AND PACKAGE
S87C654-4N40
0 to +70, Plastic Dual In-line Package
S87C654-4A44
0 to +70, Plastic Leaded Chip Carrier
S87C654–4B44
0 to +70, Plastic Quad Flat Pack
S87C654-5N40
–40 to +85, Plastic Dual In-line Package
S87C654-5A44
–40 to +85, Plastic Leaded Chip Carrier
S87C654-5B44
–40 to +85, Plastic Quad Flat Pack
S87C654–7N40
0 to +70, Plastic Dual In-line Package
S87C654–7A44
0 to +70, Plastic Leaded Chip Carrier
S87C652-4N40
0 to +70, Plastic Dual In-line Package
S87C652-4A44
0 to +70, Plastic Leaded Chip Carrier
S87C652-4B44
0 to +70, Plastic Quad Flat Pack
S87C652-5A44
–40 to +85, Plastic Leaded Chip Carrier
NOTES:
1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet
1999 Jul 23
2
FREQ
MHz
Drawing
g
Number
16
16
16
16
16
16
20
20
16
16
16
16
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT129-1
SOT187-2
SOT307-2
SOT187-2
853-1689 22042
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
BLOCK DIAGRAM
FREQUENCY
REFERENCE
XTAL2
COUNTERS
XTAL1
T0
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(16K x 8
EPROM)
DATA
MEMORY
(256 x 8 RAM)
T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
SDA
I2C SERIAL I/O
CPU
SCL
SHARED
WITH
PORT 1
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
INT0
INT1
PROGRAMMABLE I/O
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
EXTERNAL
INTERRUPTS
SERIAL IN
SERIAL OUT
SHARED WITH
PORT 3
SU00271
LOGIC SYMBOL
PSEN
PORT 0
RST
XTAL1
XTAL2
VPP/EA
ADDRESS AND
DATA BUS
VCC VSS
PORT 1
PORT 3
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS BUS
SCL
SDA
PORT 2
ALTERNATE
FUNCTIONS
PROG/ALE
SU00262
1999 Jul 23
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS
6
1
87C652/87C654
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
40
7
34
39
1
33
LCC
PQFP
17
29
18
11
28
23
12
22
Pin
23
24
25
Function
NC*
P2.0/A8
P2.1/A9
Pin
1
2
3
Function
P1.5
P1.6/SCL
P1.7/SDA
Pin
23
24
25
P1.2
P1.3
P1.4
P1.5
26
27
28
29
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
4
5
6
7
RST
P3.0/RxD
NC*
P3.1/TxD
26
27
28
29
PSEN
ALE/PROG
NC*
EA/VPP
8
9
10
11
P1.6/SCL
P1.7/SDA
RST
P3.0/RxD
30
31
32
33
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
8
9
10
11
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
30
31
32
33
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
12
13
14
15
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
34
35
36
37
NC*
EA/VPP
P0.7/AD7
P0.6/AD6
12
13
14
15
P3.6/WR
P3.7/RD
XTAL2
XTAL1
34
35
36
37
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
16
17
18
19
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
38
39
40
41
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
16
17
18
19
VSS
NC*
P2.0/A8
P2.1/A9
38
39
40
41
VCC
NC*
P1.0
P1.1
20
21
22
XTAL2
XTAL1
VSS
42
43
44
P0.1/AD1
P0.0/AD0
VCC
20
21
22
P2.2/A10
P2.3/A11
P2.4/A12
42
43
44
P1.2
P.13
P1.4
Pin
1
2
3
4
5
6
7
Function
NC*
P1.0
P1.1
* NO INTERNAL CONNECTION
1999 Jul 23
SU00260
* NO INTERNAL CONNECTION
4
Function
P2.5/A13
P2.6/A14
P2.7/A15
SU00261
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
LCC
QFP
TYPE
NAME AND FUNCTION
VSS
20
22
16
I
Ground: 0 V reference.
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
VCC
40
44
38
I
39–32
43–36
37–30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code
bytes during program verification in the 87C654. External pull-ups are required during
program verification.
1–8
2–9
40–44,
1–3
I/O
7
8
8
9
2
3
I/O
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL).
Port 1 also receives the low-order address byte during program memory verification.
Alternate functions include:
SCL: I2C-bus serial port clock line.
SDA: I2C-bus serial port data line.
P2.0–P2.7
21–28
24–31
18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51
family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VCC.
ALE/PROG
30
33
27
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program memory. When the 87C654 is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally held low to
enable the device to fetch code from external program memory locations 0000H and 1FFFH
for 87C652 and 3FFFH for 87C654. If EA is held high, the device executes from internal
program memory unless the program counter contains an address greater than 3FFFH. This
pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
P0.0–0.7
P1.0–P1.7
P1.6
P1.7
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.
1999 Jul 23
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
Table 1.
SYMBOL
87C652/87C654
8XC652/654 Special Function Registers
DESCRIPTION
DIRECT
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ADDRESS MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
DPTR:
Data pointer
(2 bytes)
Data pointer high
Data pointer low
83H
82H
IE*#
Interrupt enable
A8H
IP*#
Interrupt priority
B8H
–
87
86
85
84
83
82
81
80
P0*
Port 0
80H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
97
96
95
94
93
92
91
90
P1*#
Port 1
90H
SDA
SCL
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
A0H
A15
A14
A13
A12
A11
A10
A9
A8
B7
B6
B5
B4
B3
B2
B1
B0
DPH
DPL
00H
00H
AF
AE
EA
BF
BE
AD
AC
AB
AA
A9
A8
ES1
ES0
ET1
EX1
ET0
EX0
BD
BC
BB
BA
B9
B8
PS1
PS0
PT1
PX1
PT0
PX0
0x000000B
xx000000B
FFH
FFH
FFH
P3*
Port 3
B0H
RD
WR
T1
T0
INT1
INT0
TXD
RXD
FFH
PCON#
Power control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxx0000B
9F
9E
9D
9C
9B
9A
99
98
S0CON*#
Serial 0 port control
98H
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
S0BUF#
Serial 0 data buffer
99H
D7
D6
D5
D4
D3
D2
D1
D0
CY
AC
F0
RS1
RS0
OV
F1
P
00H
xxxxxxxxB
PSW*
Program status word
D0H
S1DAT#
Serial 1 data
DAH
SP
Stack pointer
81H
S1ADR#
Serial 1 address
DBH
 SLAVE ADDRESS 
S1STA#
Serial 1 status
D9H
SC4
DF
DE
S1CON*#
Serial 1 control
D8H
CR2
ENS1
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TH1
Timer high 1
8DH
00H
TH0
Timer high 0
8CH
00H
TL1
Timer low 1
8BH
00H
TL0
Timer low 0
8AH
00H
00H
07H
TMOD
Timer mode
89H
GATE
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1999 Jul 23
00H
SC3
C/T
SC2
00H
0
F8H
SC1
SC0
0
DD
DC
DB
DA
D9
D8
STA
STO
SI
AA
CR1
CR0
M1
6
M0
GATE
C/T
0
GC
M1
M0
00000000B
00H
00H
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
milliseconds) plus two machine cycles. At
power-on, the voltage on VCC and RST must
come up at the same time for a proper
start-up.
OSCILLATOR
CHARACTERISTICS
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol.
Idle Mode
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.
Power-Down Mode
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.
I2C SERIAL
COMMUNICATION—SIO1
The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.
Note that in both the 8XC652/4 and the
8XC552 the I2C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.
Table 2. External Pin Status During Idle and Power-Down Mode
PROGRAM
MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
MODE
Serial Control Register (S1CON) – See Table 3
S1CON (D8H)
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 3. Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC
CR2
CR1
CR0
6 MHZ
12 MHz
16 MHz
20 MHz
fOSC DIVIDED BY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
23
27
31.25
37
6.25
50
100
0.25 < 62.5
0 to 255
47
54
62.5
75
12.5
100
2001
0.5 < 62.5
0 to 254
62.5
71
83.3
100
17
1331
2671
0.65 < 55.6
0 to 253
78
891
1041
1251
21
1661
3341
0.81 < 69.4
0 to 253
256
224
192
160
960
120
60
96 × (256 – (reload value Timer 1))
(Reload value range: 0 – 254 in mode 2)
NOTE:
1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application.
1999 Jul 23
7
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING
UNIT
Storage temperature range
–65 to +150
°C
Voltage on EA/VPP to VSS
–0.5 to + 13
V
Voltage on any other pin to VSS
–0.5 to + 6.5
V
Input, output current on any single pin
±5
mA
Power dissipation (based on package heat transfer
limitations, not device power consumption)
1
W
PARAMETER
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any conditions other than those described in the AC and DC Electrical
Characteristics section of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices
from the damaging effects of excessive static charge. Nonetheless, it is suggested that
conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All
voltages are with respect to VSS unless otherwise noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE
(V)
FREQUENCY
(MHz)
TEMPERATURE
RANGE
TYPE
MIN.
MAX.
MIN.
MAX.
(°C)
S87C652-4 and
S87C654-4
4.5
5.5
3.5
16
0 to +70
S87C652-5 and
S87C654-5
4.5
5.5
3.5
16
–40 to +85
S87C654–7
4.5
5.5
3.5
20
0 to +70
1999 Jul 23
8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
DC ELECTRICAL CHARACTERISTICS
VSS = 0 V
TEST
SYMBOL
PARAMETER
MAX.
UNIT
Input low voltage,
except EA, P1.6/SCL, P1.7/SDA
0 to +70°C
–40 to +85°C
–0.5
–0.5
0.2VCC–0.1
0.2VCC–0.15
V
V
VIL1
Input low voltage to EA
0 to +70°C
–40 to +85°C
–0.5
–0.5
0.2VCC–0.3
0.2VCC–0.35
V
V
VIL2
Input low voltage to P1.6/SCL, P1.7/SDA1
–0.5
0.3VCC
V
VIH
Input high voltage,
except XTAL1, RST, P1.6/SCL, P1.7/SDA
0 to +70°C
–40 to +85°C
0.2VCC+0.9
0.2VCC+1.0
VCC+0.5
VCC+0.5
V
V
VIH1
Input high voltage, XTAL1, RST
0 to +70°C
–40 to +85°C
0.7VCC
0.7VCC+0.1
VCC+0.5
VCC+0.5
V
V
VIH2
Input high voltage, P1.6/SCL, P1.7/SDA1
6.0
V
VOL
Output low voltage, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
IOL = 1.6mA2, 3
0.45
V
VOL1
Output low voltage, port 0, ALE, PSEN
IOL = 3.2mA2, 3
0.45
V
VOL2
Output low voltage, P1.6/SCL, P1.7/SDA
IOL = 3.0mA
0.4
V
VOH
Output high voltage, ports 1, 2, 3
0 to +70°C
–40 to +85°C
IOH = –60µA
IOH = –25µA
2.4
0.75VCC
V
V
VOH1
Output high voltage; port 0 in external bus mode,
ALE, PSEN, RST4
0 to +70°C
–40 to +85°C
IOH = –400µA
IOH = –150µA
2.4
0.75VCC
V
V
IIL
Logical 0 input current, ports 1, 2, 3, 4,
except P1.6/SCL, P1.7/SDA
0 to +70°C
–40 to +85°C
VIN = 0.45V
–50
–75
µA
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3,
except P1.6/SCL, P1.7/SDA
0 to +70°C
–40 to +85°C
See note 5
–650
–750
µA
µA
IL1
Input leakage current, port 0
0.45V < VI < VCC
±10
µA
IL2
Input leakage current, P1.6/SCL, P1.7/SDA
0V < VI < 6.0V
0V < VCC < 6.0V
±10
µA
µA
ICC
Power supply current:
25
6
50
135
mA
mA
µA
µA
150
kΩ
10
pF
RRST
Internal reset pull-down resistor
CIO
Pin capacitance
CONDITIONS
LIMITS
VIL
Active mode @ 16 MHz7
Idle mode @ 16 MHz8
Power down mode9, 10
Power down mode9, 10
PART TYPE
MIN.
0.7VCC
See note 6
VCC=6.0V
0 to +70°C
–40 to +85°C
50
Freq.=1 MHz
NOTES:
1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VCC will be recognized as a
logic 0 while an input voltage above 0.7VCC will be recognized as a logic 1.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10 mA per port pin; Maximum
IOL = 26 mA total for Port 0; Maximum IOL = 15 mA total for Ports 1, 2, and 3; Maximum IOL = 71 mA total for all output pins. If IOL exceeds
the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
4. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
6. See Figures 9 through 11 for ICC test conditions.
7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns;
VIL = VSS + 0.5 V; VIH = VCC –0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VCC; fCLK = 16 MHz. See Figure 9.
8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V;
VIH = VCC –0.5 V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC; EA = RST = VSS; fCLK = 16 MHz. See Figure 10.
9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC;
EA = RST = VSS. See Figure 11.
10. 2V ≤ VPD ≤ VCCmax.
1999 Jul 23
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
VARIABLE CLOCK
MAX
MIN
MAX
UNIT
3.5
16
MHz
1/tCLCL
2
Oscillator frequency Speed Versions
87C654
–4, –5
tLHLL
2
ALE pulse width
85
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
8
tCLCL–55
ns
tLLAX
2
Address hold after ALE low
28
tLLIV
2
ALE low to valid instruction in
tLLPL
2
ALE low to PSEN low
23
tCLCL–40
ns
tPLPH
2
PSEN pulse width
143
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
tPXIX
2
Input instruction hold after PSEN
tPXIZ
2
Input instruction float after PSEN
38
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
208
5tCLCL–105
ns
tPLAZ
2
PSEN low to address float
10
10
ns
tAVLL
3, 4
Address valid to ALE low
28
tCLCL–35
ns
tRLRH
3, 4
RD pulse width
275
6tCLCL–100
ns
tWLWH
3, 4
WR pulse width
275
6tCLCL–100
ns
tRLDV
3, 4
RD low to valid data in
tRHDX
3, 4
Data hold after RD
tRHDZ
3, 4
Data float after RD
55
2tCLCL–70
ns
tLLDV
3, 4
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
3, 4
Address to valid data in
398
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
138
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
120
tQVWX
3, 4
Data valid to WR transition
tDW
3, 4
Data setup time before WR
tWHQX
3, 4
Data hold after WR
13
tRLAZ
3, 4
RD low to address float
tWHLH
3, 4
RD or WR high to ALE high
5
Serial port clock cycle time3
tCLCL–35
150
ns
4tCLCL–100
83
3tCLCL–105
0
0
ns
ns
ns
Data Memory
148
5tCLCL–165
0
0
238
3tCLCL–50
ns
ns
4tCLCL–130
ns
3
tCLCL–60
ns
288
7tCLCL–150
ns
tCLCL–50
0
23
103
tCLCL–40
ns
0
ns
tCLCL+40
ns
Shift Register
tXLXL
edge3
tQVXH
5
Output data setup to clock rising
tXHQX
5
Output data hold after clock rising edge3
edge3
0.75
12tCLCL
µs
492
10tCLCL–133
ns
80
2tCLCL–117
ns
tXHDX
5
Input data hold after clock rising
tXHDV
5
Clock rising edge to input data valid3
0
tCHCX
6
High time3
20
tCLCX
6
Low time3
20
tCLCH
6
Rise
time3
tCHCL
6
Fall time3
0
492
ns
10tCLCL–133
ns
20
tCLCL – tLOW
ns
20
tCLCL – tHIGH
ns
20
20
ns
20
20
ns
External Clock
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
1999 Jul 23
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
AC ELECTRICAL CHARACTERISTICS1, 2
20 MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
VARIABLE CLOCK
MAX
MIN
MAX
UNIT
3.5
20
MHz
1/tCLCL
2
Oscillator frequency: Speed Versions
87C654
–7, –8
tLHLL
2
ALE pulse width
60
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
25
tCLCL–25
ns
tLLAX
2
Address hold after ALE low
25
tLLIV
2
ALE low to valid instruction in
tLLPL
2
ALE low to PSEN low
25
tCLCL–25
ns
tPLPH
2
PSEN pulse width
105
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
tPXIX
2
Input instruction hold after PSEN
tPXIZ
2
Input instruction float after PSEN
25
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
170
5tCLCL–80
ns
tPLAZ
2
PSEN low to address float
10
10
ns
tAVLL
3, 4
Address valid to ALE low
25
tCLCL–25
ns
tRLRH
3, 4
RD pulse width
200
6tCLCL–100
ns
tWLWH
3, 4
WR pulse width
200
6tCLCL–100
ns
tRLDV
3, 4
RD low to valid data in
tRHDX
3, 4
Data hold after RD
tRHDZ
3, 4
Data float after RD
72
2tCLCL–28
ns
tLLDV
3, 4
ALE low to valid data in
250
8tCLCL–150
ns
tAVDV
3, 4
Address to valid data in
285
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
100
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
125
tQVWX
3, 4
Data valid to WR transition
tDW
3, 4
Data setup time before WR
tWHQX
3, 4
Data hold after WR
25
tRLAZ
3, 4
RD low to address float
tWHLH
3, 4
RD or WR high to ALE high
5
Serial port clock cycle time3
tCLCL–25
135
ns
4tCLCL–65
90
3tCLCL–60
0
0
ns
ns
ns
Data Memory
160
5tCLCL–90
0
0
200
3tCLCL–50
ns
ns
4tCLCL–75
ns
20
tCLCL–30
ns
220
7tCLCL–130
ns
tCLCL–25
0
25
75
tCLCL–25
ns
0
ns
tCLCL+25
ns
Shift Register
tXLXL
edge3
tQVXH
5
Output data setup to clock rising
tXHQX
5
Output data hold after clock rising edge3
edge3
0.6
12tCLCL
µs
367
10tCLCL–133
ns
40
2tCLCL–60
ns
tXHDX
5
Input data hold after clock rising
tXHDV
5
Clock rising edge to input data valid3
0
tCHCX
6
High time3
17
tCLCX
6
Low time3
17
tCLCH
6
Rise
time3
tCHCL
6
Fall time3
0
367
ns
10tCLCL–133
ns
17
tCLCL – tLOW
ns
17
tCLCL – tHIGH
ns
20
20
ns
20
20
ns
External Clock
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
1999 Jul 23
11
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
SCL TIMING CHARACTERISTICS
tHD; STA
START condition hold time
≥ 14 tCLCL
> 4.0 µs1
tLOW
SCL LOW time
≥ 16 tCLCL
> 4.7 µs1
tHIGH
SCL HIGH time
≥ 14 tCLCL
> 4.0 µs1
tRC
SCL rise time
≤ 1 µs
–2
tFC
SCL fall time
≤ 0.3 µs
< 0.3 µs3
SDA TIMING CHARACTERISTICS
tSU; DAT1
Data set-up time
≥ 250 ns
> 20 tCLCL – tRD
tSU; DAT2
SDA set-up time (before rep. START cond.)
≥ 250 ns
> 1 µs1
tSU; DAT3
SDA set-up time (before STOP cond.)
≥ 250 ns
> 8 tCLCL
tHD; DAT
Data hold time
≥ 0 ns
> 8 tCLCL – tFC
tSU; STA
Repeated START set-up time
≥ 14 tCLCL
> 4.7 µs1
tSU; STO
STOP condition set-up time
≥ 14 tCLCL
> 4.0 µs1
tBUF
Bus free time
≥ 14 tCLCL
> 4.7 µs1
tRD
SDA rise time
≤ 1µs
–2
tFD
SDA fall time
≤ 0.3µs
< 0.3 µs3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns < tCLCL < 285 ns (16 MHz) > fOSC > 3.5 MHz) the SI01 interface meets
the I2C-bus specification for bit-rates up to 100 kbit/s.
TIMING SIO1 (I2C) INTERFACE
repeated START condition
START or repeated START condition
START condition
tSU;STA
STOP condition
tRD
0.7 VCC
SDA
(INPUT/OUTPUT)
0.3 VCC
tBUF
tFD
tRC
tFC
tSU;STO
0.7 VCC
SCL
(INPUT/OUTPUT)
0.3 VCC
tSU;DAT3
tHD;STA
tLOW
tHIGH
tSU;DAT1
tHD;DAT
tSU;DAT2
SU00107A
1999 Jul 23
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid
to ALE low.
tLLPL = Time for ALE low
to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
INSTR IN
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU00177
Figure 2. External Data Memory Read Cycle
1999 Jul 23
13
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
tWHQX
tQVWX
tDW
A0–A7
FROM RI OR DPL
PORT 0
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
SU00213
Figure 3. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
WRITE TO SBUF
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 4. Shift Register Mode Timing
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 5. External Clock Drive
1999 Jul 23
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
VCC–0.5
0.2VCC+0.9
0.2VCC–0.1
0.45V
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00010
Figure 6. AC Testing Input/Output
VLOAD+0.1V
VOH–0.1V
TIMING
REFERENCE
POINTS
VLOAD
VLOAD–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00011
Figure 7. Float Waveform
VCC
ICC
VCC
VCC
P0
RST
87C652/4
(NC)
EA
P1.6
XTAL2
P1.7
CLOCK SIGNAL
VCC
XTAL1
*
*
VSS
SU00272
Figure 8. ICC Test Condition, Active Mode
All other pins are disconnected
NOTE:
* Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not
exceed the IOL1 specification.
1999 Jul 23
15
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
VCC
ICC
VCC
RST
EA
VCC
P0
87C652/4
(NC)
P1.6
XTAL2
*
*
P1.7
CLOCK SIGNAL
XTAL1
VSS
SU00273
Figure 9. ICC Test Condition, Idle Mode
All other pins are disconnected
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 10 ns
VCC
ICC
VCC
VCC
RST
EA
P0
87C652/4
(NC)
P1.6
XTAL2
P1.7
XTAL1
*
*
VSS
SU00274
Figure 11. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2 V to 5.5 V
NOTE:
* Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not
exceed the IOL1 specification.
1999 Jul 23
16
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
The 87C652/87C654 is programmed by using
a modified Quick-Pulse Programming
algorithm. It differs from older methods in the
value used for VPP (programming supply
voltage) and in the width and number of the
ALE/PROG pulses.
shown in Figure 12. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN and pins of ports 2 and 3
specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The
ALE/PROG is pulsed low 25 times as shown
in Figure 13.
The 87C652/87C654 contains two signature
bytes that can be read and used by an
EPROM programming system to identify the
device. The signature bytes identify the device
as an 87C652/87C654 manufactured by
Philips Components.
To program the encryption table, repeat the 25
pulse programming sequence for addresses 0
through 1FH, using the ‘Pgm Encryption Table’
levels. Do not forget that after the encryption
table is programmed, verification cycles will
produce only encrypted data.
Table 4 shows the logic levels for reading the
signature byte, and for programming the
program memory, the encryption table, and
the lock bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 12 and 13. Figure 14 shows
the circuit configuration for normal program
memory verification.
To program the lock bits, repeat the 25 pulse
programming sequence using the ‘Pgm Lock
Bit’ levels. After one lock bit is programmed,
further programming of the code memory and
encryption table is disabled. However, the
other lock bit can still be programmed.
EPROM CHARACTERISTICS
Quick-Pulse Programming
The setup for microcontroller quick-pulse
programming is shown in Figure 12. Note
that the 87C652/87C654 is running with a
4 to 6 MHz oscillator. The reason the
oscillator needs to be running is that the
device is executing internal address and
program data transfers.
Note that the EA/VPP pin must not be allowed
to go above the maximum specified VPP level
for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The VPP source
should be well regulated and free of glitches
and overshoot.
Program Verification
If lock bit 2 has not been programmed, the
on-chip program memory can be read out for
program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 14. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 4.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.
If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by
Philips
(031H) = 99H
Program/Verify Algorithms
Any algorithm in agreement with the
conditions listed in Table 4, and which
satisfies the timing specifications, is suitable.
The address of the EPROM location to be
programmed is applied to ports 1 and 2, as
Table 4. EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
1
0
Program code data
1
0
1
1
0
0
0
0
0*
VPP
1
0
1
1
Verify code data
1
0
Pgm encryption table
1
0
1
1
0
0
1
1
0*
VPP
1
0
1
0
Pgm lock bit 1
1
0
0*
VPP
1
1
1
1
Pgm lock bit 2
1
0
0*
VPP
1
1
0
0
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75 V ±0.25 V.
3. VCC = 5 V±10% during programming and verification.
* ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a
minimum of 10 µs.
Trademark phrase of Intel Corporation.
1999 Jul 23
17
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
+5V
VCC
A0–A7
P0
P1
1
RST
EA/VPP
1
P3.6
ALE/PROG
1
P3.7
87C652/4
XTAL2
4–6MHz
XTAL1
PGM DATA
+12.75V
25 100µs PULSES TO GROUND
PSEN
0
P2.7
1
P2.6
0
A8–A13
P2.0–P2.5
VSS
SU00275
Figure 12. Programming Configuration
25 PULSES
1
ALE/PROG:
0
10µs MIN
1
ALE/PROG:
100µs+10
0
SU00018
Figure 13. PROG Waveform
+5V
VCC
A0–A7
P0
P1
PGM DATA
1
RST
EA/VPP
1
1
P3.6
ALE/PROG
1
1
P3.7
PSEN
0
87C652/4
XTAL2
4–6MHz
XTAL1
P2.7
0 ENABLE
P2.6
0
P2.0–P2.5
A8–A13
VSS
SU00276
Figure 14. Program Verification
1999 Jul 23
18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 15)
SYMBOL
PARAMETER
MIN
MAX
12.5
13.0
V
50
mA
6
MHz
VPP
Programming supply voltage
IPP
Programming supply current
1/tCLCL
Oscillator frequency
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
tGHSL
VPP hold after PROG
10
tGLGH
PROG width
90
tAVQV
Address to data valid
tELQZ
ENABLE low to data valid
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
4
UNIT
µs
µs
µs
110
48tCLCL
48tCLCL
48tCLCL
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
ADDRESS
P1.0–P1.7
P2.0–P2.3
tAVQV
DATA IN
PORT 0
ALE/PROG
DATA OUT
tGHDX
tGHAX
tDVGL
tAVGL
tGHGL
tGLGH
tSHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
ENABLE
SU00270
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 12.
FOR VERIFICATION CONDITIONS SEE FIGURE 14.
Figure 15. EPROM Programming and Verification
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
1999 Jul 23
19
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
DIP40: plastic dual in-line package; 40 leads (600 mil)
1999 Jul 23
20
SOT129-1
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
PLCC44: plastic leaded chip carrier; 44 leads
1999 Jul 23
SOT187-2
21
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1999 Jul 23
22
SOT307-2
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
NOTES
1999 Jul 23
23
Philips Semiconductors
Product specification
80C51 8-bit microcontroller
8K/16K, 256 OTP, I2C
87C652/87C654
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 07-99
Document order number:
1999 Jul 23
24
9397-750-06607