INTEGRATED CIRCUITS DATA SHEET SAA4977H Besic Preliminary specification File under Integrated Circuits, IC02 1998 Jul 23 Philips Semiconductors Preliminary specification Besic SAA4977H CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 6.1 6.2 Pinning Pin description 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 Analog-to-digital conversion Digital processing at 1fH level Digital processing at 2fH level Digital-to-analog conversion Microprocessor Memory controller Line locked clock generation Clock and sync interfacing 4 : 1 : 1 I/O interfacing Test mode operation I2C-bus control registers 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 CHARACTERISTICS 11 APPLICATION 12 PACKAGE OUTLINE 13 SOLDERING 13.1 13.2 13.3 13.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I2C COMPONENTS 1998 Jul 23 2 Philips Semiconductors Preliminary specification Besic 1 SAA4977H FEATURES • Internal prefilter • Clamp circuit • Analog AGC • Line locked PLL • Synchronous No parity Eight bit Reception and Transmission (SNERT) interface. • Triple YUV 8-bit Analog-to-Digital Converter (ADC) • Horizontal compression • Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) 2 • 4 : 1 : 1 digital I/O interface The SAA4977H is a video processing IC providing analog YUV interfacing, video enhancing features, memory controlling and an embedded 80C51 microprocessor core. It is applicable especially for field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) in cooperation with a 2.9 Mbit field memory. It is designed for applications together with: • Digital CTI (DCTI) • Digital luminance peaking • Triple 10-bit Digital-to-Analog Converter (DAC) • Memory controller • Embedded microprocessor GENERAL DESCRIPTION SAA4955/56TJ, TMS4C2972/73 (serial field memories) • 16 kbyte ROM SAA4990H (PROZONIC) • 256 byte RAM SAA4991WP (MELZONIC). • I2C-bus interface 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA(1,2,3) analog supply voltage front-end 4.75 5.0 5.25 V VDDD(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 V VDDA(4,5) analog supply voltage back-end 3.15 3.3 3.45 V VDDD(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 V VDDIO I/O supply voltage back-end 4.75 5.0 5.25 V IDDA(1,2,3) analog supply current front-end − 85 100 mA IDDD(1,2,3) digital supply current front-end − 65 80 mA IDDA(4,5) analog supply current back-end − 25 35 mA IDDD(4,5,6) digital supply current back-end − 40 55 mA IDDIO I/O supply current back-end − 1 10 mA Ptot total power dissipation − − 1.3 W Tamb operating ambient temperature −20 − +60 °C 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA4977H 1998 Jul 23 QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT318-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VARIABLE Y-DELAY 26 YIN CLAMP AGC UIN 30 ANALOG PREFILTER 8 BIT 4 4 37 to 34 59 51 to 58 to 62 VARIABLE Y-DELAY 8 Y-PEAKING HORIZONTAL COMPRESSION TRIPLE ADC 28 YI7 to YI0 UV CLAMP CORRECTION VIN TRIPLE DAC REFORMATTER DCTI UP SAMPLING UP SAMPLING DOWN SAMPLING 4:4:4 TO 4:1:1 79 BLANKING FORMATTER 4:2:2 TO 4:4:4 4:1:1 TO 4:2:2 76 Besic 8 45 to 38 BLOCK DIAGRAM UVI7 to UVI4 Philips Semiconductors 5 ull pagewidth 1998 Jul 23 UVO7 to UVO4 YO7 to YO0 YOUT UOUT 10 BIT SIDEPANELS 74 VOUT SAA4977H 4 ROM TEST CONTROL BLOCK 15 49 TMS ACQUISITION PLL 47 33 SWC TRST 22 17 HA LLA CONTROL INTERFACE CONTROL INTERFACE MEMORY CONTROL (ACQUISITION) MEMORY CONTROL (DISPLAY) 20 VA 32 WE 24 RSTW SELCLK 70 63, 64 66 71, 72 68 2 2 LLD BLND RE IE2 I/O SNERTPORT BUS 9 RST I2CBUS 3 to 7 12, 13, 10 1, 2 5 3 2 P1.5 to P1.1 SNDA, SNCL, SNRST MGM592 SDA, SCL Preliminary specification SAA4977H Fig.1 Block diagram. MICROPROCESSOR HRD HDFL VDFL RAM Philips Semiconductors Preliminary specification Besic 65 VSSIO 66 BLND 67 VDDIO 68 HRD 69 VDDD4 70 LLD 71 HDFL 72 VDFL 73 VSSA4 74 VOUT 75 VDDA4 76 UOUT 77 VSSA5 handbook, full pagewidth 78 VSSA6 Pinning 79 YOUT 6.1 PINNING INFORMATION 80 VDDA5 6 SAA4977H SDA 1 64 IE2 SCL 2 63 RE P1.5 3 62 UVI4 P1.4 4 61 UVI5 P1.3 5 60 UVI6 P1.2 6 59 UVI7 P1.1 7 58 YI0 VDDD5 8 57 YI1 RST 9 56 YI2 SNRST 10 55 YI3 VDDD6 11 54 YI4 SNDA 12 53 YI5 SAA4977H SNCL 13 52 YI6 VSSD4 14 51 YI7 50 VSSD3 TMS 15 VSSD1 16 49 TRST 48 VSSD2 SELCLK 17 VDDD1 18 47 SWC VDDD2 19 46 VDDD3 Fig.2 Pin configuration. 1998 Jul 23 5 YO2 40 YO1 39 YO0 38 UVO7 37 UVO6 36 UVO5 35 UVO4 34 41 YO3 LLA 33 RSTW 24 WE 32 42 YO4 VSSA3 31 VDDA1 23 VIN 30 43 YO5 VDDA3 29 HA 22 UIN 28 44 YO6 VSSA2 27 VSSA1 21 YIN 26 45 YO7 VDDA2 25 VA 20 MGM593 Philips Semiconductors Preliminary specification Besic 6.2 SAA4977H Pin description Table 1 QFP80 package SYMBOL PIN DESCRIPTION 1 I2C-bus serial data (P1.7) SCL 2 I2C-bus serial clock (P1.6) P1.5 3 Port 1 data input/output signal 5 P1.4 4 Port 1 data input/output signal 4 P1.3 5 Port 1 data input/output signal 3 P1.2 6 Port 1 data input/output signal 2 P1.1 7 Port 1 data input/output signal 1 VDDD5 8 digital supply voltage 5 (3.3 V) RST 9 microprocessor reset input SNRST 10 SNERT restart (port 1.0) VDDD6 11 digital supply voltage 6 (3.3 V) SNDA 12 SNERT data SNCL 13 SNERT clock VSSD4 14 digital ground 4 TMS 15 test mode select VSSD1 16 digital ground 1 SELCLK 17 select acquisition clock input; internal PLL if HIGH, external clock if LOW VDDD1 18 digital supply voltage 1 (5 V) VDDD2 19 digital supply voltage 2 (5 V) VA 20 vertical synchronization input, acquisition part VSSA1 21 analog ground 1 HA 22 analog/digital horizontal reference input VDDA1 23 analog supply voltage 1 (5 V) RSTW 24 reset write signal output, memory 1 VDDA2 25 analog supply voltage 2 (5 V) YIN 26 Y analog input VSSA2 27 analog ground 2 UIN 28 U analog input VDDA3 29 analog supply voltage 3 (5 V) VIN 30 V analog input VSSA3 31 analog ground 3 WE 32 write enable signal output, memory 1 LLA 33 acquisition clock input UVO4 34 V digital output bit 0 UVO5 35 V digital output bit 1 UVO6 36 U digital output bit 0 UVO7 37 U digital output bit 1 YO0 38 Y digital output bit 0 SDA 1998 Jul 23 6 Philips Semiconductors Preliminary specification Besic SYMBOL SAA4977H PIN DESCRIPTION YO1 39 Y digital output bit 1 YO2 40 Y digital output bit 2 YO3 41 Y digital output bit 3 YO4 42 Y digital output bit 4 YO5 43 Y digital output bit 5 YO6 44 Y digital output bit 6 YO7 45 Y digital output bit 7 (MSB) VDDD3 46 digital supply voltage 3 (5 V) SWC 47 serial write clock output VSSD2 48 digital ground 2 TRST 49 test reset, active LOW VSSD3 50 digital ground 3 YI7 51 Y digital input bit 7 (MSB) YI6 52 Y digital input bit 6 YI5 53 Y digital input bit 5 YI4 54 Y digital input bit 4 YI3 55 Y digital input bit 3 YI2 56 Y digital input bit 2 YI1 57 Y digital input bit 1 YI0 58 Y digital input bit 0 UVI7 59 U digital input bit 1 UVI6 60 U digital input bit 0 UVI5 61 V digital input bit 1 UVI4 62 V digital input bit 0 RE 63 read enable signal output, memory 1 IE2 64 input enable signal output, memory 2 VSSIO 65 I/O ground BLND 66 horizontal blanking signal output, display part VDDIO 67 I/O supply voltage (5 V) HRD 68 horizontal reference signal output, deflection part VDDD4 69 digital supply voltage 4 (3.3 V) LLD 70 display clock input HDFL 71 horizontal synchronization signal output, deflection part VDFL 72 vertical synchronization signal output, deflection part VSSA4 73 analog ground 4 VOUT 74 V analog output VDDA4 75 analog supply voltage 4 (3.3 V) UOUT 76 U analog output VSSA5 77 analog ground 5 1998 Jul 23 7 Philips Semiconductors Preliminary specification Besic SYMBOL SAA4977H PIN DESCRIPTION VSSA6 78 analog ground 6 YOUT 79 Y analog output VDDA5 80 analog supply voltage 5 (3.3 V) 7 FUNCTIONAL DESCRIPTION 7.1 7.1.1 7.1.4 Three identical ADCs are used to convert Y, U and V with 16 MHz data rate. A multi-step type ADC is applied here. Analog-to-digital conversion CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16 AND UV TO 0 (2’S COMPLEMENT) 7.2 A clamp circuit is applied for each input channel, to map the colourless black level in each video line (on the sync back porch) to level 16 for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch on the clamp action. An operational transconductance amplifier like construction, which references to voltage reference points in the ladders of the ADCs, will provide a current on the input of the YUV signals, in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to ±100 µA. When the clamping action is off, the residual clamp current should be very low in order not to drift away within a video line. 7.1.2 7.2.1 7.2.2 OVERLOAD DETECTION DIGITAL CLAMP CORRECTION FOR UV During 32 samples within the clamp position the clamp error is measured and accumulated to make a low-pass filtered value of the clamp error. Then a vertical recursive filter is used to further low-pass this error value. This value can be read by the microprocessor or directly be used to correct the clamp error. It is also possible to give a fixed correction value by the microprocessor. GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL 7.2.3 4 : 4 : 4 TO 4 : 1 : 1 DOWN-SAMPLING AND UV CORING The U and V samples from the ADC are low-pass filtered, before being subsampled with a factor of 2. Coring is applied to the subsampled signal to obtain no gain for low amplitudes which is considered to be noise. Coring levels can be programmed as 0 (off), ±1⁄2, ±1 and ±2 LSB. Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may be gain adjusted already, whereas luminance is to be adjusted by the SAA4977H AGC. On the other hand, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain. The U and V samples from the 4 : 2 : 2 data are low-pass filtered again, before being subsampled a second time with a factor of 2 and formatted to 4 : 1 : 1 format. ANALOG ANTI-ALIASING PREFILTERING 7.2.4 A third order linear phase filter is applied on each of the Y, U and V channels. It provides a notch on fCLK (16 MHz) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for −3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired. 1998 Jul 23 Digital processing at 1fH level The overload detection provides information to make efficient use of the AGC. The number of overflows per video field in the luminance channel is accumulated by a 14-bit counter. The 8 MSBs of this counter can be read out by the microprocessor respectively via the I2C-bus. Overflow levels can be programmed as 216, 224, 232 and 240. A variable amplifier is used to map the possible YUV input range to the ADC range. A rise of 6 dB up to a drop fall of 6 dB w.r.t. the nominal values can be achieved. The gain setting within this range is done digitally via control registers. For this purpose a gain setting DAC is incorporated. The smallest step in the gain setting should be hardly visible on the picture, which can be met with smallest steps of 0.4%/step. 7.1.3 TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION Y-DELAY The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. The other settings provide four samples less delay to three sample more delay in Y. 8 Philips Semiconductors Preliminary specification Besic 7.2.5 SAA4977H • The original signal band-passed with centre frequency of 2.38 MHz. HORIZONTAL COMPRESSION For displaying 4 : 3 sources on 16 : 9 screens a horizontal signal compression can be done by data interpolation. Therefore two horizontal compression factors of either 4⁄ or 7⁄ are possible. Via the I2C-bus the compression can 3 6 be switched on or off and the compression mode 16 : 9 or 14 : 9 can be selected. When the compression mode is active, a reduced number of the interpolated data is stored in the field memory. To achieve sufficiently high accuracy in interpolation Variable Phase Delay filters are used (VPD10 for luminance, a multiplexed VPD06 for UV). 7.3 7.3.1 The band-passed and high-passed signals are weighted with factors 0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16, and 8⁄16, resulting in a maximum gain difference of 2 dB at the centre frequencies. Coring is added to obtain no gain for low amplitudes in the high-pass and band-pass filtered signal, which is considered to be noise. Coring levels can be programmed as 0 (off), ±8, ±16, ±24 to ±120 LSB w.r.t. the (signed) 11-bit filtered signal. In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 1⁄4, 2⁄4, and 4⁄4. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 1⁄4, 2⁄4, and 4⁄4. Digital processing at 2fH level 4 : 1 : 1 TO 4 : 2 : 2 UP-CONVERSION An up-converter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. 7.3.2 7.3.4 The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide one to seven samples less delay in Y. DCTI The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately. 7.3.5 This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. Via the I2C-bus it is possible to control: gain width (see Fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.3), limit for pixel shift range (see Fig.5), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component. 7.3.3 SIDEPANELS AND BLANKING Sidepanels are generated by switching Y and the 4 MSBs of U and V to certain programmable values. The start and stop values for the sidepanels w.r.t. the rising edge of the HRD signal are programmable in a resolution of 4 LLD clock cycles. In addition, a fine shift of 0 to 3 LLD clock cycles of both values can be achieved. Blanking is done by switching Y to value 64 at 10-bit word and UV to value 0 (in 2’s complement). Blanking is controlled by a composite signal HVBDA, consisting of a horizontal part HBDA and a vertical part VBDA. Set and reset value of the horizontal control signal HBDA are programmable w.r.t. the rising edge of the HRD signal, set and reset value of the vertical control signal VBDA are programmable w.r.t. the rising edge of the VA signal. Y-PEAKING A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. The range of the Y output signal can be selected between 9 and 10 bits. In the case of 9 bits for the nominal signal there is room left for undershoot and overshoot (adding up to a total of 10 bits). In the case of selecting all 10 bits of the luminance DAC for the nominal signal any under or overshoot will be clipped (see Fig.11). The filtering is an addition of: • The original signal • The original signal high-passed with maximum gain at frequency = 1⁄2fs (8 MHz) • The original signal band-passed with centre frequency = 1⁄4fs (4 MHz) 1998 Jul 23 Y-DELAY 9 Philips Semiconductors Preliminary specification Besic SAA4977H MGM689 1 handbook, halfpage signal amplitude 0.8 (1) (2) 0.6 0.4 0.2 0 0 0.05 0.1 0.15 0.2 f/fs 0.25 (1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0. Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel. handbook, full pagewidth MGM690 500 digital signal 400 amplitude (1) 300 (4) 200 (2) (3) (5) 100 0 samples −100 −200 −300 (1) input signal. (2) gain = 1. −400 (3) gain = 3. (4) gain = 5. (5) gain = 7. −500 Fig.4 DCTI with variation of gain setting (limit = 1). 1998 Jul 23 10 Philips Semiconductors Preliminary specification Besic handbook, full pagewidth SAA4977H MGM691 500 digital signal 400 amplitude (4) (3) (2) 300 (1) 200 100 0 samples −100 −200 −300 −400 (1) (2) (3) (4) input signal. limit = 1. limit = 2. limit = 3. −500 Fig.5 DCTI with variation of limit setting (gain = 7). MGM692 1.2 handbook, halfpage signal amplitude 0.8 0.4 0 0 0.1 0.2 0.3 0.4 f/fs 0.5 Fig.6 DCTI post-filter transfer function. 1998 Jul 23 11 Philips Semiconductors Preliminary specification Besic SAA4977H MGM594 10 handbook, full pagewidth signal amplitude (dB) (7) 8 (6) (5) 6 (4) (3) 4 (2) 2 (1) 0 0 (1) (2) (3) (4) (5) (6) (7) 0.1 0.2 0.3 0.4 f/fs β = 1⁄16. β = 2⁄16. β = 3⁄16. β = 4⁄16. β = 5⁄16. β = 6⁄16. β = 8⁄16. Fig.7 Transfer function of the peaking high-pass filter with variation of β (α = 0; τ = 0). 1998 Jul 23 12 0.5 Philips Semiconductors Preliminary specification Besic SAA4977H MGM595 10 handbook, full pagewidth signal amplitude (dB) (7) 8 (6) (5) 6 (4) (3) 4 (2) 2 (1) 0 0 (1) (2) (3) (4) (5) (6) (7) 0.1 0.2 0.3 0.4 f/fs α = 1⁄16. α = 2⁄16. α = 3⁄16. α = 4⁄16. α = 5⁄16. α = 6⁄16. α = 8⁄16. Fig.8 Transfer function of the peaking band-pass with variation of α (β = 0; τ = 0). 1998 Jul 23 13 0.5 Philips Semiconductors Preliminary specification Besic SAA4977H MGM596 10 handbook, full pagewidth signal amplitude (dB) 8 (7) (6) 6 (5) (4) 4 (3) (2) 2 (1) 0 0 (1) (2) (3) (4) (5) (6) (7) 0.1 0.2 0.3 0.4 f/fs τ = 1⁄16. τ = 2⁄16. τ = 3⁄16. τ = 4⁄16. τ = 5⁄16. τ = 6⁄16. τ = 8⁄16. Fig.9 Transfer function of peaking low band-pass with variation of τ (α = 0; β = 0). 1998 Jul 23 14 0.5 Philips Semiconductors Preliminary specification Besic 7.4 SAA4977H When reading from the bus, one byte is loaded by the microprocessor for the address, the received byte is the data from the addressed SNERT location. Digital-to-analog conversion Three identical 10-bit DACs are used to map the 4 : 4 : 4 data to analog levels. 7.5 7.5.3 Microprocessor A parallel 8-bit I/O port (P1) is available, where P1.0 is used as the SNERT reset signal (SNRST), P1.1 to P1.5 can be used for application specific control signals, and P1.6 and P1.7 are used as I2C-bus signals (SCL and SDA). The SAA4977H contains an embedded 80C51 microprocessor core including a 256 byte RAM and 16 kbyte ROM. The microprocessor runs on a 16 MHz clock, generated by dividing the 32 MHz display clock by a factor of 2. For controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in, that can be addressed as internal AUX RAM via MOVX type of instructions. 7.5.1 7.5.4 I2C-BUS 7.6 The I2C-bus slave address of the SAA4977H is 0110100 R/W. Memory controller The memory controller provides all necessary acquisition clock related write signals (WE and RSTW) and display clock related read signals (RE and IE2) to control one or two-field memory concepts. Furthermore the drive signals (HDFL and VDFL) for the horizontal and vertical deflection power stages are generated. Also a horizontal blanking pulse BLND is generated which can be used for peripheral circuits as SAA4990H. The memory controller is connected to the microprocessor via the host interface. Start and stop values for all pulses, referring to the corresponding horizontal or vertical reference signal, are programmable under control of the internal software. To allow user access to these control signals via the I2C-bus a range of subaddresses is reserved; for a detailed description of this user interface refer to Application Note “I2C-bus register specification of the SAA4977H” (AN98054). For a detailed description of the transmission protocol refer to brochure “The I2C-bus and how to use it” (order number 9398 393 40011) and to Application note “I2C-bus register specification of the SAA4977H” (AN98054). SNERT-BUS A SNERT interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as the SAA4990H or SAA4991WP. The SNERT interface replaces the standard UART interface. In contrast to the 80C51 UART interface there are additional special function registers and there is no byte separation time between address and data. The SNERT interface transforms the parallel data from the microprocessor into 1 Mbaud SNERT data. The SNERT-bus consists of three signals: SNCL used as the serial clock signal and is generated by the SNERT interface; SNDA used as the bidirectional data line, and SNRST used as the reset signal and is generated by the microprocessor to indicate the start of a transmission. 7.6.1 WE The write enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position w.r.t the rising edge of the HA signal and the vertical position w.r.t the rising edge of the VA signal are programmable. The read or write operation must be set by the microprocessor. When writing to the bus, 2 bytes are loaded by the microprocessor: one for the address, the other for the data. 1998 Jul 23 WATCHDOG TIMER The microprocessor contains an internal Watchdog Timer, which can be activated by setting the bit 4 in SFR PCON. Only a synchronous reset will clear this bit. To prevent a system reset the Watchdog Timer must be reloaded in time. The Watchdog Timer is incremented every 0.75 ms. The time interval between the timer’s reloading and the occurrence of a reset depends on the reloaded 8-bit value. The I2C-bus interface in the SAA4977H is used in a slave receive and transmit mode for communication with a central system microprocessor. The standardized bus frequencies of both 100 kHz and 400 kHz can be dealt with. 7.5.2 I/O PORTS 15 Philips Semiconductors Preliminary specification Besic 7.6.2 SAA4977H RSTW 7.7.2 Reset write signal for field memory 1; this signal is derived from the positive edge of the VA input signal and has a pulse width of 64 µs. 7.6.3 The basic frequency of the clock generator is 32 MHz. The type of PLL is known as ‘Petra PLL’. This is a purely analog clock generator, with analog frequency control via a loop filter on the measured phase error. RE The read enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position w.r.t the rising edge of the HA signal and the vertical position w.r.t the rising edge of the VA signal are programmable. 7.6.4 7.7.3 IE2 7.7.4 HDFL 7.8 VDFL The line locked display clock LLD must be provided by the application. Also a line frequent signal must be provided by the application at pin HA. A vertical 50 or 60 Hz synchronization signal has to be applied on pin VA. It is also possible to use an external line locked acquisition clock, which must be provided at pin LLA. This operation mode can be selected by the SELCLK pin. When using the external acquisition clock the HA signal must be synchronous to the acquisition clock. BLND Horizontal blanking signal for peripheral circuits e.g. SAA4990H, start and stop values w.r.t. the rising edge of HRD are programmable. 7.7 7.7.1 A display clock synchronous line frequent signal is put out at pin HRD providing a duty factor of 50%. The rising edge of HRD is also the reference for display related control signals as BLND, RE, HDAV and HBDA. Line locked clock generation PHASE COMPARISON OF HA RISING EDGE WITH GENERATED Href SIGNAL The HA signal, which has a nominal period of 64 µs, is used as a timing reference for the line locked acquisition clock system. This HA signal may vary in position from application to application, related to the active video part. The phase comparator measures the delay between the HA and the internally generated, clock synchronous Href signal. 1998 Jul 23 Clock and sync interfacing Typically the circuit operates as a two clock system, i.e. LLA is supplied with a 16 MHz clock and LLD with a 32 MHz clock. Vertical deflection signal for driving a deflection circuit; this signal has a cycle time of 10 ms; the start and stop value w.r.t the rising edge of the VA signal is programmable in steps of 16 µs. 7.6.7 DIVIDE BY ANOTHER 1024 TO GENERATE LINE FREQUENT, CLOCK SYNCHRONOUS Href SIGNAL The video lines contain 1024 clock cycles of 16 MHz. Therefore, frequency division by 1024 creates a 50% duty cycle line frequent signal Href. Horizontal deflection signal for driving a deflection circuit; this signal has a cycle time of 32 µs and a pulse width of 76 LLD clock cycles. 7.6.6 DIVIDE-BY-2 FOR MASTER CLOCK 16 MHZ A simple clock divider is used to generate 16 MHz out of 32 MHz. The advantage of this construction is the inherent 50% duty cycle on the acquisition clock. Input enable signal for field memory 2, can be directly set or reset by the microprocessor. 7.6.5 PLL CLOCK GENERATOR RUNNING AT 32 MHZ (2048 CLOCK CYCLES PER LINE) The acquisition clock is buffered internally and put out as serial write clock (SWC) for supplying the field memory. 16 Philips Semiconductors Preliminary specification Besic 7.9 SAA4977H 4 : 1 : 1 I/O interfacing Table 2 Digital input and output bus format OUTPUT PIN INPUT PIN 4 : 1 : 1 FORMAT YO7 Y07 Y17 Y27 Y37 YI7 YO6 Y06 Y16 Y26 Y36 YI6 YO5 Y05 Y15 Y25 Y35 YI5 YO4 Y04 Y14 Y24 Y34 YI4 YO3 Y03 Y13 Y23 Y33 YI3 YO2 Y02 Y12 Y22 Y32 YI2 Y01 Y01 Y11 Y21 Y31 YI1 YO0 Y00 Y10 Y20 Y30 YI0 UVO7 U07 U05 U03 U01 UVI7 UVO6 U06 U04 U02 U00 UVI6 UVO5 V07 V05 V03 V01 UVI5 UVO4 V06 V04 V02 V00 UVI4 The first phase of the 4 : 1 : 1 YUV dataword is available on the output bus one SWC clock cycle after the rising edge of the WE signal. The start position, when the first phase of the 4 : 1 : 1 YUV data word is expected on the input bus, can be defined by the internal control signal HDAV. The luminance output signal is in 8-bit straight binary format, whereas U and V input signals are in 2’s complement format. Also the luminance input signal is expected in 8-bit straight binary format, whereas U and V input signals are expected in 2’s complement format. The U and V input signals are inverted if the corresponding control bit uv_inv is set via the I2C-bus. 7.10 Test mode operation The SAA4977H provides a test mode function which should not be entered by the customer. If the TRST input is driven HIGH, different test modes can be selected by applying a HIGH to the TMS input for a defined number of LLD clock cycles. To exit the test mode TMS and TRST must be driven LOW. 1998 Jul 23 17 Philips Semiconductors Preliminary specification Besic 7.11 SAA4977H I2C-bus control registers ADDRESS BIT NAME DESCRIPTION Subaddress 00H to 2FH: reserved; note 1 Subaddress 30H to 32H (AGC) 30H 0 to 7 AGC_Y AGC gain for Y channel (2’s complement relative to 0 dB): upper 8 bits 31H 0 to 7 AGC_UV AGC gain for U and V channel (2’s complement relative to 0 dB): upper 8 bits 32H 0 AGC_Y AGC gain for Y channel LSB 1 AGC_UV AGC gain for UV channel LSB 2 standby_f front-end in standby mode if HIGH 3 aaf_bypass bypass for prefilter if HIGH 4 to 7 − reserved Subaddress 33H (UV clamp correction) 33H 0 and 1 UVclcor_mode clamp correction mode = auto, fixed, keep, reserved 2 to 4 Uclcor_fval fixed value for clamp correction U channel 5 to 7 Vclcor_fval fixed value for clamp correction V channel Subaddress 34H (UV coring) 34H 0 and 1 UVcoring coring level = 0, ±0.5, ±1 and ±2 LSB 2 and 3 − reserved 4 and 5 UVcl_tau vertical filtering of measured clamp 6 and 7 − reserved Subaddress 35H (Y delay) 35H 0 to 2 ydelay_f variable Y-delay in LLA clock cycles: −4, −3, −2, −1, 0, 1, 2 and 3 3 and 4 overl_thr overload threshold: (216, 224, 232, 240) 5 fill memory with constant value if HIGH fill_mem 6 and 7 − reserved Subaddress 36H and 37H (DCTI) 36H 37H 0 to 2 dcti_gain DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7 3 to 6 dcti_threshold DCTI threshold: 0, 1 to 15 7 dcti_ddx_sel DCTI selection of first differentiating filter; see Fig.3 0 and 1 dcti_limit DCTI limit for pixel shift range: 0, 1, 2 and 3 2 dcti_separate DCTI separate processing of U and V signals; 0 = off, 1 = on 3 dcti_protection DCTI over the hill protection; 0 = off, 1 = on 4 dcti_filteron DCTI post-filter; 0 = off, 1 = on 5 dcti_superhill DCTI super hill mode; 0 = off, 1 = on 6 and 7 − reserved Subaddress 38H and 3AH (peaking) 38H 0 to 2 pk_alpha peaking alpha: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8) 3 to 5 pk_beta peaking beta: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8) 6 and 7 − 1998 Jul 23 reserved 18 Philips Semiconductors Preliminary specification Besic SAA4977H ADDRESS 39H 3AH BIT 0 to 2 NAME pk_tau DESCRIPTION peaking tau: 1⁄ 16 (0, 1, 2, 3, 4, 5, 6, 8) 3 and 4 pk_delta peaking amplitude dependent attenuation: 1⁄4 (0, 1, 2, 4) 5 and 6 pk_neggain peaking attenuation of undershoots: 1⁄4 (0, 1, 2, 4) 7 − reserved 0 to 3 pk_corthr peaking coring threshold 0, ±8, ±16 to ±120 LSB 4 to 7 − reserved Subaddress 3BH and 3CH (sidepanels overlay) 3BH 3CH 0 to 3 overlay_u sidepanels overlay U (4 MSB) 4 to 7 overlay_v sidepanels overlay V (4 MSB) 0 to 7 overlay_y sidepanels overlay Y (8 MSB) Subaddress 3DH to 3FH (sidepanel position) 3DH 0 to 7 sidepanel_start sidepanel start position (8 MSB) w.r.t. the rising edge of HRD signal 3EH 0 to 7 sidepanel_stop sidepanel stop position (8 MSB) w.r.t. the rising edge of HRD signal 3FH 0 and 1 sidepanel_fdel fine delay of sidepanel signal in LLD clock cycles: 0, 1, 2 and 3 2 output_range output range (output range = 0: 9 bit for the nominal output signal, black level: 288 and white level: 767; output range = 1: 10 bit for the nominal output signal, black level 64 and white level 1023) 3 uv_inv inverts UV input signals: 0 = no inversion, 1 = inversion 4 to 6 ydelay_out variable Y-delay in LLD clock cycles: −7, −6, −5, −4, −3, −2, −1 and 0 7 − reserved Note 1. Detailed information about the software dependent I2C-bus registers can be found in Application Note “I2C-bus register specification of the SAA4977H” (AN98054). 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA(1,2,3) analog supply voltage front-end −0.5 +5.25 V VDDD(1,2,3) digital supply voltage front-end −0.5 +5.25 V VDDA(4,5) analog supply voltage back-end −0.5 +3.45 V VDDD(4,5,6) digital supply voltage back-end −0.5 +3.45 V VDDIO digital I/O supply voltage back-end −0.5 +5.25 V Vi input voltage for all I/O pins −0.5 +5.25 V Tstg storage temperature −20 +150 °C Tamb operating ambient temperature −20 +60 °C 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1998 Jul 23 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 19 VALUE UNIT 50 K/W Philips Semiconductors Preliminary specification Besic SAA4977H 10 CHARACTERISTICS VDDD(1,2,3) = 4.75 to 5.25 V; VDDA(1,2,3) = 4.75 to 5.25 V; VDDD(4,5,6) = 3.15 to 3.45 V; VDDA(4,5) = 3.15 to 3.45 V; Tamb = 0 to 60 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA(1,2,3) analog supply voltage front-end VDDD(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 V IDDA(1,2,3) analog supply current front-end − 85 100 mA IDDD(1,2,3) digital supply current front-end − 65 80 mA 4.75 5.0 5.25 V VDDA(4,5) analog supply voltage back-end 3.15 3.3 3.45 V VDDD(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 V VDDIO I/O supply voltage back-end 4.75 5.0 5.25 V IDDA(4,5) analog supply current back-end − 25 35 mA IDDD(4,5,6) digital supply current back-end − 40 55 mA IDDIO I/O supply current back-end − 1 10 mA total power dissipation − − 1.3 W 0.95 1.00 1.05 V − 7 15 pF Dissipation Ptot Luminance input signal (Y clamp level digital 16) Vi(p-p) Y input level (peak-to-peak value) AGC fixed at 0 dB; note 1 Ci input capacitance ILI input leakage current clamp not active − − 100 nA II input current during clamping − − ±150 µA αAGC(max) maximum AGC attenuation 5.75 6 − dB GAGC(max) maximum AGC gain 5.75 6 − dB αAGC(acc) AGC attenuation accuracy digital − 8 − bits GAGC(acc) AGC gain accuracy digital − 8 − bits Colour difference input signals (U and V clamp level digital 128) Vi(p-p) U input level (peak-to-peak value) AGC fixed at 0 dB; note 1 1.29 1.34 1.39 V V input level (peak-to-peak value) AGC fixed at 0 dB; note 1 1.00 1.05 1.10 V − − 15 pF Ci input capacitance ILI input leakage current clamp not active − − 100 nA II input current during clamping − − ±150 µA αAGC(max) maximum AGC attenuation 5.75 6 − dB GAGC(max) maximum AGC gain 5.75 6 − dB αAGC(acc) AGC attenuation accuracy digital − 8 − bits GAGC(acc) AGC gain accuracy digital − 8 − bits 1998 Jul 23 20 Philips Semiconductors Preliminary specification Besic SYMBOL SAA4977H PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog input transfer function (sample rate 16 MHz/8 bits) fCLK maximum sample clock 18 − − MHz INL integral non linearity ramp input signal −1 − +1 LSB DNL differential non linearity ramp input signal −0.75 − +0.75 LSB S/N signal-to-noise ratio nominal amplitude; 0 to 8 MHz 43 − − dB HD harmonic distortion (2nd to 5th harmonic) 95% amplitude; − Y at 4.3 MHz; UV at 1 MHz −50 −37 dB Gdif differential gain fCLK = 4.4 MHz; ADC only; at nominal AGC setting − 1 2 % SVR supply voltage rejection note 2 34 − − dB 5.4 5.6 5.8 MHz 7 8 − dB Analog Y, U and V input filter (third order linear phase filter with notch at fCLK) f(−3dB) 3 dB down frequency fCLK = 16 MHz α(0.5) attenuation at αsb stop band attenuation 30 − − dB fnotch notch frequency 15.5 16 16.5 MHz td(g) group delay − 55 65 ns td(g)(dif) differential group delay within 1 to 6 MHz − 20 30 ns 1⁄ f 2 CLK (8 MHz) fCLK = 4 MHz Luminance output signal (output_range = 0: Y black level digital 288, white level digital 767, output_range = 1: Y black level digital 64, white level digital 1023); see Fig.11 Vo(p-p) Y output level (peak-to-peak value) Ro RL ZL = 2 kΩ 1.28 1.34 1.40 V output resistance − 50 100 Ω resistive load 1 2 − kΩ CL capacitive load − − 25 pF SVR supply voltage rejection note 2 34 − − dB αct crosstalk attenuation between outputs 0 to 10 MHz 40 − − dB S/N signal-to-noise ratio nominal amplitude; 0 to 10 MHz 46 − − dB Colour difference output signals (U and V digital range 0 to 1023) Vo(p-p) U output level (peak-to-peak value) ZL = 2 kΩ 1.28 1.34 1.40 V V output level (peak-to-peak value) ZL = 2 kΩ 1.28 1.34 1.40 V Gm(U-V) gain matching U to V − 1 3 % Ro output resistance − 50 100 Ω RL resistive load 1 2 − kΩ CL capacitive load SVR supply voltage rejection 1998 Jul 23 note 2 21 − − 25 pF 34 − − dB Philips Semiconductors Preliminary specification Besic SYMBOL SAA4977H PARAMETER CONDITIONS MIN. TYP. MAX. UNIT αct crosstalk attenuation between outputs 0 to 10 MHz 40 − − dB S/N signal-to-noise ratio nominal amplitude; 0 to 10 MHz 46 − − dB Output transfer function (sample rate 32 MHz/10 bits) INL integral non linearity −2 − +2 LSB DNL differential non linearity −1 − +1 LSB Digital output signals: YO, UVO, WE and RSTW (CL = 15 pF); timing referred to SWC clock VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V td(o) output delay time see Fig.10 − − 20 ns th(o) output hold time see Fig.10 4 − − ns Digital output signal: SWC (CL = 15 pF); timing referred to LLA clock VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V td(o) output delay time see Fig.10 3 − 12 ns Digital output signal: HRD VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V Digital output signals: IE2, BLND, RE, HDFL and VDFL (CL = 15 pF); timing referred to LLD clock VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V td(o) output delay time see Fig.10 − − 20 ns th(o) output hold time see Fig.10 4 − − ns Digital input/output signals: P1.1 to P1.5 and SNRST VOH HIGH-level output voltage IOH = −0.06 mA 2.4 − − V IOL = 1.6 mA VOL LOW-level output voltage 0 − 0.4 V VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage 0 − 0.8 V Digital input signals: YI and UVI; timing referred to LLD clock VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V tsu(i) input set-up time see Fig.10 4 − − ns th(i) input hold time see Fig.10 3 − − ns 1998 Jul 23 22 Philips Semiconductors Preliminary specification Besic SYMBOL SAA4977H PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital input signal: HA; timing referred to LLA clock (only when SELCLK = 0, HA used as digital horizontal reference) VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V tsu(i) input set-up time see Fig.10 7 − − ns th(i) input hold time see Fig.10 4 − − ns Digital input signals: TRST, TMS, RST and VA VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V Digital input clock signal: LLA fLLA sample clock frequency 14 16 34 MHz δclk clock duty factor 40 50 60 % VIH HIGH-level input voltage 2.4 − − V VIL LOW-level input voltage − − 0.6 V tr clock rise time see Fig.10 − − 5 ns tf clock fall time see Fig.10 − − 5 ns 30 32 34 MHz Digital input clock signal: LLD fLLD sample clock frequency δclk clock duty factor 40 50 60 % VIH HIGH-level input voltage 2.4 − − V VIL LOW-level input voltage − − 0.6 V tr clock rise time see Fig.10 − − 5 ns tf clock fall time see Fig.10 − − 5 ns 0.7VDDIO − − V I2C-bus signal: SDA and SCL; note 3 VIH HIGH-level input voltage VIL LOW-level input voltage VOL LOW-level output voltage fSCL − − 0.3VDDIO V − − 0.4 V SCL clock frequency − − 400 kHz tHD;STA hold time START condition 0.6 − − µs tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tSU;DAT data set-up time 100 − − ns tSU;DAT1 data set-up time (before repeated START condition) 0.6 − − µs tSU;DAT2 data set-up time (before STOP condition) 0.6 − − µs tSU;STA set-up time repeated START 0.6 − − µs tSU;STO set-up time STOP condition 0.6 − − µs 1998 Jul 23 IOL = 3.0 mA 23 Philips Semiconductors Preliminary specification Besic SAA4977H SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT SNERT-bus: SNDA and SNCL; note 4 VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V tsu(i) input set-up time 700 − − ns th(i) input hold time 0 − − ns tcycle SNCL cycle time − 1 − µs th(o) output hold time 50 − − ns Notes 1. With AGC at −3 dB, U full ADC range is obtained at Vi = 1.89 V; with AGC at +6 dB, U full ADC range is obtained at Vi = 0.67 V; with AGC at −3 dB, V full ADC range is obtained at Vi = 1.48 V; with AGC at +6 dB, V full ADC range is obtained at Vi = 0.52 V. 2. Supply voltage ripple rejection, measured over a frequency range from 20 Hz to 50 kHz. This includes 1⁄2fV, fV, 2fV, fH and 2fH which are major load frequencies: SVR is relative variation of the full scale analog input for a supply variation of 0.25 V. 3. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure “I2C-bus and how to use it” (order number 9398 393 40011). 4. More information about the SNERT-bus protocol can be found in Application Note “The SNERT-bus specification” (AN95127). tr handbook, full pagewidth tf 2.4 V CLOCK 1.5 V 0.6 V th(i) tsu(i) 2.0 V INPUT DATA 0.8 V td(o) th(o) 2.4 V OUTPUT DATA 0.4 V MGM597 Fig.10 Timing diagram. 1998 Jul 23 24 Philips Semiconductors Preliminary specification Besic SAA4977H INPUT 8 bit handbook, full pagewidth OUTPUT 10 bit output_range = 1 white 255 1023 output_range = 0 1023 767 1.00 V 1.34 V 288 256 black 16 0 64 0 0 MGM598 Fig.11 Luminance levels. 11 APPLICATION The SAA4977H supports two different up-converter concepts. The simple one is shown in Fig.12. In this application only one field memory SAA4955TJ is needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode). The concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the SAA4956TJ is used instead of the SAA4955TJ. The SAA4977H supports a dual-clock system. The acquisition clock is taken from the digital front-end. The display control is based on a clock generated by an external H-PLL. By this structure the stability of the display is enhanced compared to a one-clock system if an unstable source like a VCR is used as an input. The second system supported by the SAA4977H is shown in Fig.13. This concept needs two field memories (SAA4955TJ) and the signal processing IC MELZONIC (SAA4991WP). The SAA4991WP allows a vector based motion estimation and compensation for a display of 100 Hz pictures in high-end TV sets which is free of motion artefacts. It additionally provides a variable vertical zoom function, noise and cross colour reduction. Furthermore a multi-PIP feature is supported making use of the field memories. 1998 Jul 23 25 Philips Semiconductors Preliminary specification Besic SAA4977H handbook, full pagewidth +5 V +3.3 V YIN 26 UIN 28 VIN 19, 22 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 10 µF 17, 18, 19, 23, 25, 29, 46, 67 9 8.2 kΩ 30 +3.3 V D11 8, 11, 69, 75, 80 +5 V 20, 21, 23 15 16 3 SWC RSTW WE 47 45 24 44 32 43 4 17, 18 5 38 51 42 6 37 52 41 7 36 53 40 8 35 54 39 34 55 10 33 56 37 11 32 57 36 12 31 58 35 13 30 59 34 14 29 60 28 61 25 27 62 26 24 9 SAA4955TJ(1) RE SAA4977H 38 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 79 YOUT 76 UOUT 74 VOUT 63 1, 2, 39, 40 1 SDA 2 SCL 20 22 HRD HDFL 71 14 to 16, 21, 27, 31, 72 48 to 50, 3 to 7, 68 33, 65, 73, 10, 12, 70 77, 78 13, 64, 66 VDFL n.c. VA DISPLAY PLL HA SRC MGM599 (1) Alternatively SAA4956TJ. Fig.12 Application diagram 1. 1998 Jul 23 26 Philips Semiconductors Preliminary specification Besic SAA4977H handbook, YIN full pagewidth UIN VIN +5 V +3.3 V SWC +3.3 V 19, 22 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 +5 V RSTW WE 20, 21, 23 15 28 16 4 17, 18 5 38 41 6 37 40 37 SAA4955TJ 34 FM1 33 10 36 32 34 9 31 33 13 30 32 29 27 26 24 32 31 28 25 30 29 RE1 28 1, 2, 39, 40 48 51 49 52 50 53 51 54 52 55 53 56 54 57 55 58 56 59 57 60 58 61 59 62 RE 61 +3.3 V 19, 22 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 +5 V SAA4991WP 17, 18 5 38 64 6 37 66 25 7 36 67 24 8 35 68 23 SAA4955TJ 34 FM2 33 10 69 21 70 19 11 32 71 18 12 31 72 17 13 30 73 16 14 29 74 15 28 75 14 27 76 9 24 1, 2, 39, 40 42 41 40 39 SAA4977H 38 37 36 35 34 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 79 YOUT 76 UOUT 74 VOUT 1 SDA 2 SCL 20 WE2 4 26 43 13 16 25 44 12 SNCL 43 45 63 SNDA 44 20, 21, 23 15 3 8.2 kΩ 24 35 12 14 1, 4, 20, 42, 46, 65, 78 38 35 11 10 µF 17, 18, 19, 23, 25, 29, 9 46, 67 47 36 8 8, 11, 69, 75, 80 30 +5 V 3 7 26 RE2 11 77 8 to 10 2, 3, 5, 6, 7, 22, 26, 27, 47, 60, 63, 79 to 84 62 13 12 22 n.c. D11 D10 HRD HDFL 71 14 to 16, 21, 27, 31, 72 48 to 50, 68 33, 65, 73, 3 to 7, 70 77, 78 10, 64, 66 VDFL D9 n.c. D8 D7 D6 D5 DISPLAY PLL SRC D4 D3 D2 D1 D0 45 MGM600 VA HA Fig.13 Application diagram 2. 1998 Jul 23 27 Philips Semiconductors Preliminary specification Besic SAA4977H 12 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2 c y X 64 A 41 40 65 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp 80 L 25 detail X 24 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.2 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 20.1 19.9 14.1 13.9 0.8 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.2 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT318-2 1998 Jul 23 EUROPEAN PROJECTION 28 Philips Semiconductors Preliminary specification Besic SAA4977H If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: 13 SOLDERING 13.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). 13.2 Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. 13.3 Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Jul 23 Repairing soldered joints 29 Philips Semiconductors Preliminary specification Besic SAA4977H 14 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Jul 23 30 Philips Semiconductors Preliminary specification Besic SAA4977H NOTES 1998 Jul 23 31 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/00/01/pp32 Date of release: 1998 Jul 23 Document order number: 9397 750 03258