INTEGRATED CIRCUITS 74LVT74 3.3V Dual D-type flip-flop Product specification IC24 Data Handbook 1996 Aug 28 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 QUICK REFERENCE DATA SYMBOL DESCRIPTION CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay CPn to Qn CL = 50pF; VCC = 3.3V CIN Input capacitance VI = 0V or 3.0V ICC Total supply current VCC = 3.6V TYPICAL UNIT 3.1 3.6 ns 3 pF 0.5 mA The 74LVT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL 2, 12 D0, D1 D1 3, 11 CP0, CP1 Clock inputs (active rising edge) CP1 4, 10 SD0, SD1 Set inputs (active LOW) 10 SD1 1, 13 RD0, RD1 Reset inputs (active LOW) 6 9 Q1 5, 6, 8, 9 Qn, Qn 7 8 Q1 RD0 1 14 VCC D0 2 13 RD1 CP0 3 12 SD0 4 11 Q0 5 Q0 GND SF00045 NAME AND FUNCTION Data inputs Data outputs LOGIC SYMBOL (IEEE/IEC) LOGIC SYMBOL 2 12 4 & S 5 3 C1 D0 D1 3 CP0 4 SD0 2 1 1 RD0 11 CP1 10 SD1 13 RD1 10 5 6 R S 9 11 C2 12 13 Q0 Q0 Q1 Q1 VCC = Pin 14 GND = Pin 7 1D 6 9 8 2D 8 R SA00359 SF00047 ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO PACKAGES –40°C to +85°C 74LVT74 D 74LVT74 D SOT108-1 14-Pin Plastic SSOP –40°C to +85°C 74LVT74 DB 74LVT74 DB SOT337-1 14-Pin Plastic TSSOP –40°C to +85°C 74LVT74 PW 74LVT74PW DH SOT402-1 1996 Aug 28 2 853-1872 17244 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 LOGIC DIAGRAM FUNCTION TABLE INPUTS SD RD CP D 4, 10 5, 9 1, 13 Q 6, 8 3, 11 Q OUTPUTS OPERATING MODE SD RD CP D Q Q L H X X H L Asynchronous set H L X X L H Asynchronous reset L L X X H H Undetermined* H H ↑ h H L Load “1” H H ↑ l L H Load “0” H H ↑ X NC NC Hold NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition NC= No change from the previous setup X = Don’t care ↑ = Low-to-high clock transition ↑ = Not low-to-high clock transition * = This setup is unstable and will change when either set or reset return to the high level. 2, 12 VCC = Pin 14 GND = Pin 7 SF00048 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC PARAMETER IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT CONDITIONS DC supply voltage DC output out ut current Tstg Storage temperature range UNIT V –50 mA VI < 0 DC output voltage3 IOUT RATING –0.5 to +4.6 –0.5 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in High state –32 Output in Low state 64 mA °C –65 to 150 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC LIMITS PARAMETER DC supply voltage UNIT MIN MAX 2.7 3.6 V 0 5.5 V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –20 mA IOL Low-level output current 32 mA ∆t/∆v Input transition rise or fall rate; Outputs enabled 10 ns/V Tamb Operating free-air temperature range +85 °C 1996 Aug 28 2.0 –40 3 V Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions Voltages are referenced to GND (ground = 0V) LIMITS SYMBOL TEST CONDITIONS PARAMETER Temp = -40°C to +85°C MIN VIK Input clamp voltage VOL II High-level output voltage Low-level output voltage Input In ut leakage current –1.2 VCC = 2.7V; IOH = –6mA 2.4 VCC = 3.0V; IOH = –20mA 2.0 V VCC = 2.7V; IOL = 100µA 0.2 VCC = 2.7V; IOL = 24mA 0.5 VCC = 3.0V; IOL = 32mA 0.5 VCC = 0 or 3.6V; VI = 5.5V 10 VCC = 3.6V; VI = VCC or GND ±1 ±100 µA 1 mA 0.2 µA Output off current VCC = 0V; VI or VO = 0 to 4.5V ICC Quiescent supply current VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 Additional supply current per input pin2 VCC = 3V to 3.6V; One input at VCC–0.6V, Other inputs at VCC or GND Input capacitance VI = 3V or 0 CI V VCC–0.2 IOFF ∆ICC UNIT MAX VCC = 2.7V; IIK = –18mA VCC = 2.7 to 3.6V; IOH = –100µA VOH TYP1 0.5 3 V µA pF NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND. AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V MAX MAX UNIT MIN TYP1 1 150 345 Propagation delay CPn to Qn or Qn 1 1.0 1.0 3.1 3.6 4.8 5.0 5.8 5.0 ns Propagation delay SDn, RDn to Qn or Qn 2 1.0 1.0 3.1 3.0 5.0 4.4 6.2 4.8 ns fMAX Maximum clock frequency tPLH tPHL tPLH tPHL MHz NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V MIN TYP MIN 1 1.7 1.4 0.6 0.4 1.8 1.6 Holdtime Dn to CPn 1 0.3 0 –0.3 –0.6 0.3 0 tW (H) tW (L) CPn Pulse Width 1 2.0 2.0 1.0 1.2 3.0 3.0 tW (L) SDn, RDn Pulse Width 2 2.0 1.0 3.0 Recovery time SDn, RDn tp CPn 3 0.5 –0.3 0.5 tS (H) tS (L) Setup time Dn to CPn th (H) th (L) trec 1996 Aug 28 4 UNIT ns ns ns Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 AC WAVEFORMS VM = 1.5V, VIN = GND to 2.7V Dn VM tsu(L) VM VM tsu(H) th(L) VM tw(L) SDn VM VM th(H) 1/fmax CPn VM VM VM VM tw(H) tPHL tPLH tPHL tPLH Qn tw(L) RDn tw(L) VM Qn VM VM VM VM tPLH tPHL tPLH tPHL VM VM Qn VM VM Qn SF00050 Waveform 2. Propagation delay for set and reset to output, set and reset pulse width SF00049 Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency SDn or RDn VM trec CPn VM SF00051 Waveform 3. Recovery time for set or reset to clock TEST CIRCUIT AND WAVEFORMS VCC CL 10% 0V D.U.T. RT AMP (V) VM 10% VOUT PULSE GENERATOR 90% VM NEGATIVE PULSE VIN tW 90% RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for Outputs AMP (V) 90% VM VM 10% 10% tW 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74LVT RT = Termination resistance should be equal to ZOUT of pulse generators. 1996 Aug 28 Amplitude Rep. Rate 2.7V ≤10MHz tW tR tF 500ns ≤2.5ns ≤2.5ns SV00022 5 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 SO14: plastic small outline package; 14 leads; body width 3.9 mm 1996 Aug 28 6 SOT108-1 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1996 Aug 28 7 SOT337-1 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1996 Aug 28 8 SOT402-1 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 NOTES 1996 Aug 28 9 Philips Semiconductors Product specification 3.3V Dual D-type flip-flop 74LVT74 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. 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Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.