INTEGRATED CIRCUITS PCKV857A 100-250 MHz differential 1:10 clock driver Product data Supersedes data of 2002 Dec 13 Philips Semiconductors 2003 Jul 31 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver FEATURES PCKV857A PIN CONFIGURATION • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. GND 1 • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 47 Y5 Y0 3 46 Y5 VDDQ 4 Y1 5 • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications as per JEDEC specifications Y1 6 • 1-to-10 differential clock distribution • Very low skew (< 100 ps) and jitter (< 100 ps) • Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD • SSTL_2 interface clock inputs and outputs • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Full DDR solution provided when used with SSTL16877 or 45 VDDQ 44 Y6 43 Y6 GND 7 42 GND GND 8 41 GND 40 Y7 39 Y7 Y2 9 Y2 10 VDDQ 11 38 VDDQ VDDQ 12 37 PWRDWN 36 FBIN CLK 13 CLK 14 VDDQ 15 35 FBIN AVDD 16 33 FBOUT 32 FBOUT AGND 17 GND 18 SSTV16857 34 VDDQ Y3 19 31 GND 30 Y8 Y3 20 29 Y8 VDDQ 21 • Designed for DDR 266, 300, and 333 DIMM applications • Available in TSSOP-48 and TVSOP-48 packages 48 GND Y0 2 Y4 22 Y4 23 GND 24 28 VDDQ 27 Y9 26 Y9 25 GND SW00691 DESCRIPTION The PCKV857A is a high-performance, low-skew, low-jitter zero delay buffer designed for 2.5 V VDD and 2.5 V AVDD operation and differential data input and output levels. The PCKV857A is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT, FBOUT) . The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is HIGH, the outputs switch in phase and frequency with CLK. When PWRDWN is LOW, all outputs are disabled to HIGH impedance state (3-State), and the PLL is shut down (LOW power mode). The device also enters the LOW power mode when the input frequency falls below 20 MHz. An input frequency detection circuit will detect the LOW frequency condition and after applying a > 20 MHz input signal, the detection circuit turns on the PLL again and enables the outputs. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PCKV857A is also able to track spread spectrum clocking for reduced EMI. The PCKV857A is characterized for operation from 0 to +70 °C. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 48-Pin Plastic TSSOP 0 to +70 °C PCKV857ADGG SOT362-1 48-Pin Plastic TSSOP (TVSOP) 0 to +70 °C PCKV857ADGV SOT480-1 2003 Jul 31 2 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A PIN DESCRIPTION PINS SYMBOL DESCRIPTION 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND SSTL_2 ground pins 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 Yn, Yn, FBOUT, FBOUT SSTL_2 differential outputs 4, 11, 12, 15, 21, 28, 34, 38, 46 VDDQ SSTL_2 power pins 13, 14, 35, 36 CLKIN, CLKIN, FBIN, FBIN SSTL_2 differential inputs 16 AVDD Analog power 17 AGND Analog ground 37 PWRDWN Power-down control input FUNCTION TABLE INPUTS OUTPUTS PLL ON/OFF PWRDWN CLK CLK Yn Yn FBOUT FBOUT L L H Z Z Z1 Z1 OFF Z1 OFF H ON L H L Z Z Z1 H L H L H L H H L H L H L ON X2 < 20 MHz < 20 MHz Z Z Z1 Z1 OFF NOTES: H = HIGH voltage level L = LOW voltage level Z = HIGH impedance OFF-state X = don’t care 1. Subject to change. May cause conflict with FBIN pins. 2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode. BLOCK DIAGRAM 37 - PWRDWN 3 - Y0 2 - Y0 5 - Y1 6 - Y1 10 - Y2 9 - Y2 20 - Y3 19 - Y3 22 - Y4 23 - Y4 13 - CLK 14 - CLK PLL 36 - FBIN 35 - FBIN 16 - AVDD 46 - Y5 47 - Y5 44 - Y6 43 - Y6 39 - Y7 40 - Y7 29 - Y8 30 - Y8 27 - Y9 28 - Y9 32 - FBOUT 33 - FBOUT SW00692 2003 Jul 31 3 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMITS CONDITION MIN MAX UNIT VDDQ Supply voltage range 0.5 3.6 V AVDD Supply voltage range 0.5 3.6 V V VI Input voltage range see Notes 2 and 3 -0.5 VDDQ + 0.5 VO Output voltage range see Notes 2 and 3 -0.5 VDDQ + 0.5 V IIK Input clamp current VI < 0 or VI >VDDQ — ±50 mA IOK Output clamp current VO < 0 or VO >VDDQ — ±50 mA IO Continuous output current VO = 0 to VDDQ — ±50 mA — ±100 mA -65 +150 °C Continuous current to GND or VDDQ Tstg Storage temperature range NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 3.6 V maximum. RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER CONDITION LIMITS MIN TYP MAX UNIT VDDQ Supply voltage range 2.3 — 2.7 V AVDD Supply voltage range 2.2 — 2.7 V CLK, CLK, FBIN, FBIN — — VDDQ/2 − 0.18 PWRDWN −0.3 — 0.7 CLK, CLK, FBIN, FBIN VDDQ/2 + 0.18 — — PWRDWN 1.7 — VDDQ + 0.3 Note 2 −0.3 — VDDQ V VIL VIH LOW-level input voltage HIGH-level input voltage DC input signal voltage VID V V DC differential input signal voltage CLK, FBIN Note 3 0.36 — VDDQ + 0.6 V AC differential input signal voltage CLK, FBIN Note 3 0.7 — VDDQ + 0.6 V V VOX Output differential cross-voltage Note 4 VDDQ/2 − 0.2 VDDQ/2 VDDQ/2 + 0.2 Note 4 VIX Input differential cross-voltage VDDQ/2 − 0.2 — VDDQ/2 + 0.2 V IOH HIGH-level output current — — −12 mA IOL LOW-level output current — — 12 mA SR Input slew rate 1 — 4 V/ns Operating free-air temperature 0 — 70 °C Tamb NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing. 2003 Jul 31 4 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK PARAMETER TEST CONDITIONS Input voltage, all inputs VOH HIGH-level output voltage VOL LOW-level output voltage MIN TYP MAX UNIT VDDQ = 2.3 V, II = -18 mA — — −1.2 V VDDQ = min to max, IOH = -1 mA VDDQ − 0.1 — — V VDDQ = 2.3 V, IOH = -12 mA 1.7 — — V VDDQ = min to max, IOL = 1 mA — — 0.1 V VDDQ = 2.3 V, IOL = 12 mA — — 0.6 V VDDQ = 2.7 V, VI = 0 V to 2.7 V — — ±10 µA IOZ HIGH-impedance-state output current VDDQ = 2.7 V, VO = VDDQ or GND — — ±10 µA IDDPD Power-down current on VDDQ + AVDD CLK and CLK = 0 MHz, PWRDWN = LOW; Σ of IDD and AIDD — 30 100 µA Dynamic current on VDDQ fO = 67 MHz to 190 MHz — 200 300 mA Supply current on AVDD fO = 67 MHz to 190 MHz — 8 10 mA VCC = 2.5 V, VI = VCC or GND 2 2.8 3 pF II IDD AIDD CI Input current Input capacitance NOTE: 1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs. 2. All typical values are at respective nominal VDDQ. 3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature. MIN MAX UNIT Operating clock frequency PARAMETER 100 250 MHz Input clock duty cycle 40 60 % 100 — µs SYMBOL fCK Stabilization time1 NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up. 2003 Jul 31 5 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ LIMITS SYMBOL PARAMETER WAVEFORM CONDITION MIN TYP MAX UNIT t(O) Static phase offset Figure 1 -350 0 350 ps tSK(O) Output clock skew Figure 2 — — 150 ps tSLR(O) Output clock slew rate Figure 3 1 — 2 V/ns tJIT(PER) Jitter (period) Figure 4 fO = 67 MHz to 200 MHz -75 — 75 ps tJIT(CC) Jitter (cycle-to-cycle) Figure 5 fO = 67 MHz to 200 MHz -75 — 75 ps Half-period jitter Figure 6 -75 — 75 ps tJIT(HPER) tPLH1 LOW to HIGH level propagation delay Test mode/CLK to any output — 3.7 — ns tPHL1 HIGH to LOW level propagation delay Test mode/CLK to any output — 3.7 — ns SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM NOTE: 1. Refers to transition of noninverting output. FRONT SIDE SSTL16877 or SSTV16857 PCKV857A SSTL16877 or SSTV16857 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00945 2003 Jul 31 6 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A AC WAVEFORMS CLK CLK FBIN FBIN t(O)n + 1 t(O)n t(O) = Σ n =N t(O)n 1 N (N is a large number of samples) SW00882 Figure 1. Static phase offset Yx Yx Yx, FBOUT Yx, FBOUT tsk(O) SW00883 Figure 2. Output skew 80% 80% VID, VOD 20% 20% CLOCK INPUTS AND OUTPUTS tSLR(I), tSLR(O) tSLR(I), tSLR(O) SW00886 Figure 3. Input and output slew rates 2003 Jul 31 7 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A Yx, FBOUT Yx, FBOUT tcycle n Yx, FBOUT Yx, FBOUT 1 fO tJIT(PER) = tcycle n - 1 fO SW00884 Figure 4. Period jitter tcycle n + 1 tcycle n Yx, FBOUT Yx, FBOUT tJIT(CC) = tcycle n - t cycle n+1 SW00881 Figure 5. Cycle-to-cycle jitter Yx, FBOUT Yx, FBOUT thalf period n thalf period n + 1 1 fO tJIT(HPER) = thalf period n - 1 2*fO SW00885 Figure 6. Half-period jitter skew ANY TWO OUTPUTS SW00396 Figure 7. Skew between any two outputs. 2003 Jul 31 8 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver t1 45% v PCKV857A t2 t1 v 55% t1 ) t2 SW00397 Figure 8. Duty cycle limits and measurement TEST CIRCUIT VDD/2 PCKV857A C = 14 pf Z = 60 Ω SCOPE -V DD/2 R = 10 Ω Z = 50 Ω R = 50 Ω Z = 60 Ω R = 10 Ω Z = 50 Ω VTT R = 50 Ω C = 14 pf -V DD/2 VTT NOTE: VTT = GND -V DD/2 SW00946 Figure 9. Output load test circuit 2003 Jul 31 9 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2003 Jul 31 10 PCKV857A SOT362-1 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm 2003 Jul 31 11 PCKV857A SOT480-1 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver REVISION HISTORY Rev Date PCKV857A Description _2 20030731 Product data (9397 750 11759); ECN 853-2394 30057 dated 18 June 2003. Supersedes data of 2002 Decemaber 13 (9397 750 10867). Modifications: • Minor changes or corrections to existing product specifications. _1 20021213 Product data (9397 750 10867); ECN 853-2394 29181 of 13 December 2002. 2003 Jul 31 12 Philips Semiconductors Product data 100-250 MHz differential 1:10 clock driver PCKV857A Data sheet status Level Data sheet status[1] Product status[2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 07-03 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2003 Jul 31 13 9397 750 11759