74ABT623 Octal transceiver with dual enable; non-inverting; 3-state Rev. 03 — 22 October 2009 Product data sheet 1. General description The 74ABT623 high performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT623 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of pins OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high-impedance OFF-state, both sets of the bus lines will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical. 2. Features n n n n n n n Octal bidirectional bus interface 3-state buffers Power-up 3-state Output capability: +64 mA and −32 mA data inputs are disabled during 3-state mode Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT623D −40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74ABT623DB −40 °C to +85 °C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74ABT623PW −40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 4. Functional diagram 19 1 EN1 EN2 1 1 2 3 4 5 6 7 8 9 2 OEAB A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 18 2 18 17 3 17 16 4 16 5 15 6 14 12 7 13 11 8 12 9 11 15 14 13 OEBA 19 001aaa833 001aaa844 Fig 1. Logic symbol. Fig 2. IEC logic symbol. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 2 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 19 1 2 OEBA OEAB A0 B0 3 A1 B1 4 13 A6 B6 9 14 A5 B5 8 15 A4 B4 7 16 A3 B3 6 17 A2 B2 5 18 12 A7 B7 11 001aaa832 Fig 3. Logic diagram 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 3 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 5. Pinning information 5.1 Pinning 74ABT623 74ABT623 OEAB A0 A1 A2 A3 A4 A5 A6 A7 1 OEAB 1 20 VCC 19 OEBA A0 2 19 OEBA 18 B0 A1 3 18 B0 17 B1 A2 4 17 B1 16 B2 A3 5 16 B2 15 B3 A4 6 15 B3 14 B4 A5 7 14 B4 13 B5 A6 8 13 B5 12 B6 A7 9 12 B6 GND 10 11 B7 20 VCC 2 3 4 5 6 7 8 9 GND 10 11 B7 001aak829 001aak828 Fig 4. Pin configuration SO20 Fig 5. Pin configuration (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OEAB 1 output enable input (active HIGH) A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input or output B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input or output GND 10 ground (0 V) OEBA 19 output enable input (active LOW) VCC 20 supply voltage 6. Functional description Table 3. Function table[1] Input Input or output OEAB OEBA An Bn L L An = Bn input H H input Bn = An L H Z Z H L An = Bn input H L input Bn = An [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 4 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage Conditions VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input diode current VI < 0 V Min Max Unit −0.5 +7.0 V [1] −1.2 +7.0 V [1] −0.5 +5.5 V −18 - mA IOK output diode current VO < 0 V −50 - mA IO output current output in LOW-state - 128 mA Tj junction temperature - 150 °C Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot [2] Tamb = −40 °C to +85 °C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. [3] For SO20 package: Ptot derates linearly with 8 mW/K above 70 °C. For SSOP20 and TSSOP20 package: Ptot derates linearly with 5.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VIH HIGH-level input voltage VIL LOW-level input voltage IOH Conditions Min Typ Max Unit 4.5 - 5.5 V 0 - VCC V 2.0 - - V - - 0.8 V HIGH-level output current −32 - - mA IOL LOW-level output current - - 64 mA ∆t/∆V input transition rise or fall rate 0 - 10 ns/V Tamb ambient temperature −40 - +85 °C in free air 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 5 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 °C Conditions Min Typ Max Min Max - −0.9 −1.2 - −1.2 V VCC = 4.5 V; IOH = −3 mA 2.5 2.9 - 2.5 - V VCC = 5.0 V; IOH = −3 mA 3.0 3.4 - 3.0 - V VCC = 4.5 V; IOH = −32 mA 2.0 2.4 - 2.0 - V - 0.42 0.55 - 0.55 V - ±0.01 ±1.0 - ±1.0 µA VIK input clamping voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VI = VIL or VIH VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH II input leakage current VCC = 5.5 V; VI = GND or 5.5 V OEAB, OEBA An, Bn VCC = 0.0 V; VI or VO ≤ 4.5 V IOFF power-off leakage current IO(pu/pd) power-up/power-down VCC = 2.0 V; VO = 0.5 V; output current VI = GND or VCC; OEAB = GND; OEBA = VCC IOZ OFF-state output current [1] VO = 2.7 V ±5.0 ±100 - ±100 µA ±5.0 ±100 - ±100 µA - ±5.0 ±50 - ±50 µA - 5.0 50 - 50 µA - −5.0 −50 - −50 µA - 5.0 50 - 50 µA −180 −100 −50 −180 −50 mA outputs HIGH-state - 50 250 - 250 µA outputs LOW-state - 24 30 - 30 mA - 50 250 - 250 µA - 0.5 1.5 - 1.5 mA VO = 0.5 V output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [2] outputs disabled additional supply current - VCC = 5.5 V; VI = VIL or VIH ILO ∆ICC −40 °C to +85 °C Unit per input pin; VCC = 5.5 V; one input pin at 3.4 V, other inputs at VCC or GND [3] outputs enabled - 50 250 - 250 mA one enable input at 3.4 V and other inputs at VCC or GND; outputs disabled outputs disabled - 0.5 1.5 - 1.5 mA CI input capacitance VI = 0 V or VCC - 4 - - - pF CI/O input/output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF [1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 ms is permitted. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [3] This is the increase in supply current for each input at 3.4 V. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 6 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 9. Symbol Parameter 25 °C; VCC = 5.0 V Conditions −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min Typ Max Min Max tPLH LOW to HIGH propagation delay An to Bn or Bn to An; see Figure 6 1.0 2.6 4.1 1.0 4.6 ns tPHL HIGH to LOW propagation delay An to Bn or Bn to An; see Figure 6 1.0 2.7 4.2 1.0 4.6 ns tPZH OFF-state to HIGH propagation delay OEAB, OEBA to An or Bn; see Figure 7 and Figure 8 1.7 3.4 6.5 1.7 7.5 ns tPZL OFF-state to LOW propagation delay OEAB, OEBA to An or Bn; see Figure 7 and Figure 8 1.7 4.8 6.5 1.7 7.5 ns tPHZ HIGH to OFF-state propagation delay OEAB, OEBA to An or Bn; see Figure 7 and Figure 8 1.7 3.6 6.5 1.7 7.5 ns tPLZ LOW to OFF-state propagation delay OEAB, OEBA to An or Bn; see Figure 7 and Figure 8 1.7 3.1 6.5 1.7 7.5 ns 11. Waveforms VI An, Bn input VM GND t PHL t PLH VOH Bn, An output VM VOL mna366 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (An, Bn) to output (Bn, An) 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 7 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state VI OEAB input VM GND tPLZ tPZL 3.5 V output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs disabled outputs enabled outputs enabled 001aak830 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times for OEAB input. VI OEBA input VM GND tPLZ tPZL 3.5 V output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs disabled outputs enabled outputs enabled 001aak831 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Table 8. Enable and disable times for OEBA input. Measurement points Input Output VI VM VX VY 3.0 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 8 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state VI tW 90 % 90 % negative pulse VM 0V VEXT tf tr tr tf VI VCC VI VM VM 10 % DUT RT 10 % RL VO G 90 % positive pulse 0V VM 10 % RL CL tW mna616 001aac221 a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 9. CL = Load capacitance including jig and probe capacitance. Fig 9. Table 9. Test circuit for measuring switching times Test data Input Load VEXT tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 9 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT163-1. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 10 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT339-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT339-1. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 11 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT360-1 JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 12. Package outline SOT360-1. 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 12 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS BIpolar Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT623_3 20091022 Product data sheet - 74ABT623_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. DIP20 package removed from Section 3 “Ordering information” and Section 12 “Package outline”. 74ABT623_2 19980116 Product specification - 74ABT623_1 74ABT623_1 19960925 - - - 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 13 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74ABT623_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 22 October 2009 14 of 15 74ABT623 NXP Semiconductors Octal transceiver with dual enable; non-inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 22 October 2009 Document identifier: 74ABT623_3