74AUP2GU04 Low-power dual unbuffered inverter Rev. 02 — 3 July 2009 Product data sheet 1. General description The 74AUP2GU04 provides two unbuffered inverting gates. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. 2. Features n Wide supply voltage range from 0.8 V to 3.6 V n High noise immunity n ESD protection: u HBM JESD22-A114E Class 3A exceeds 5000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Low static power consumption; ICC = 0.9 µA (maximum) n Latch-up performance exceeds 100 mA per JESD 78 Class II n Inputs accept voltages up to 3.6 V n Multiple package options n Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2GU04GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP2GU04GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP2GU04GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 4. Marking Table 2. Marking Type number Marking code[1] 74AUP2GU04GW aD 74AUP2GU04GM aD 74AUP2GU04GF aD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 6 1Y 1 1 VCC 6 540 Ω 50 Ω A 3 2A 4 2Y 1 3 Y 4 001aad073 mnb107 mnb106 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AUP2GU04 74AUP2GU04 1A 1 6 1A 1 6 1Y GND 2 5 VCC 1Y GND 2 5 VCC 2A 3 4 2Y 2A 001aad699 Fig 4. Pin configuration SOT363 (SC-88) 3 4 2Y 001aad700 Transparent top view Fig 5. Pin configuration SOT886 (XSON6) 74AUP2GU04_2 Product data sheet 74AUP2GU04 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aad701 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 2 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 7. Functional description Table 4. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions Min −0.5 +4.6 V VI < 0 V −50 - mA −0.5 +4.6 V −50 - mA −0.5 VCC + 0.5 V - ±20 mA [1] VO < 0 V [2] Max Unit VO output voltage IO output current ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW VO = 0 V to VCC Tamb = −40 °C to +125 °C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 3 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCC V Tamb ambient temperature −40 +125 °C ∆t/∆V input transition rise and fall rate 0 200 ns/V Typ Max Unit V VCC = 0.8 V to 3.6 V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Tamb = 25 °C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 × VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - - 0.25 × VCC V VOH HIGH-level output voltage VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - - V IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V VOL LOW-level output voltage VI = GND or VCC IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.1 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 1.5 - pF CO output capacitance VO = GND; VCC = 0 V - 1.8 - pF 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 4 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 × VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - - 0.25 × VCC V VOH HIGH-level output voltage VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V VOL LOW-level output voltage VI = GND or VCC IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA V Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 × VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - 0.25 × VCC V VOH HIGH-level output voltage VI = GND or VCC IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V 74AUP2GU04_2 Product data sheet - © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 5 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = GND or VCC LOW-level output voltage Min Typ Max Unit IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min - 6.2 - - - - ns VCC = 1.1 V to 1.3 V 0.9 2.3 4.4 0.9 4.8 5.3 ns VCC = 1.4 V to 1.6 V 0.7 1.7 3.1 0.6 3.4 3.8 ns VCC = 1.65 V to 1.95 V 0.5 1.4 2.6 0.5 2.9 3.2 ns VCC = 2.3 V to 2.7 V 0.4 1.1 2.0 0.4 2.3 2.6 ns VCC = 3.0 V to 3.6 V 0.3 1.0 1.8 0.3 2.1 2.4 ns - 9.6 - - - - ns VCC = 1.1 V to 1.3 V 1.2 3.1 6.1 1.2 6.8 7.5 ns VCC = 1.4 V to 1.6 V 1.0 2.3 4.0 0.9 4.6 5.1 ns VCC = 1.65 V to 1.95 V 0.8 1.9 3.3 0.7 3.8 4.2 ns VCC = 2.3 V to 2.7 V 0.6 1.5 2.7 0.6 3.1 3.5 ns VCC = 3.0 V to 3.6 V 0.5 1.3 2.4 0.5 2.7 3.0 ns Max Max (85 °C) (125 °C) CL = 5 pF tpd propagation delay nA to nY; see Figure 7 [2] VCC = 0.8 V CL = 10 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V [2] 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 6 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min - 13.0 - - - - ns VCC = 1.1 V to 1.3 V 1.6 3.8 7.9 1.4 8.8 9.7 ns VCC = 1.4 V to 1.6 V 1.3 2.8 4.9 1.1 5.7 6.3 ns VCC = 1.65 V to 1.95 V 1.0 2.3 4.0 0.9 4.7 5.2 ns VCC = 2.3 V to 2.7 V 0.8 1.9 3.2 0.8 3.7 4.1 ns VCC = 3.0 V to 3.6 V 0.7 1.6 2.9 0.7 3.3 3.7 ns - 23.2 - - - - ns VCC = 1.1 V to 1.3 V 2.4 6.0 13.1 2.2 14.8 16.3 ns VCC = 1.4 V to 1.6 V 2.0 4.2 7.6 1.8 9.0 9.9 ns VCC = 1.65 V to 1.95 V 1.7 3.6 6.1 1.5 7.2 8.0 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.8 1.3 5.7 6.3 ns VCC = 3.0 V to 3.6 V 1.2 2.5 4.3 1.1 5.1 5.7 ns VCC = 0.8 V - 1.1 - - - - pF VCC = 1.1 V to 1.3 V - 1.1 - - - - pF VCC = 1.4 V to 1.6 V - 1.3 - - - - pF VCC = 1.65 V to 1.95 V - 1.5 - - - - pF VCC = 2.3 V to 2.7 V - 3.0 - - - - pF VCC = 3.0 V to 3.6 V - 4.5 - - - - pF Max Max (85 °C) (125 °C) CL = 15 pF propagation delay nA to nY; see Figure 7 tpd [2] VCC = 0.8 V CL = 30 pF propagation delay nA to nY; see Figure 7 tpd [2] VCC = 0.8 V CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD fi = 1 MHz; VI = GND to VCC [3][4] [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] All specified values are the average typical values over all stated loads. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 7 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 12. Waveforms VI VM nA input VM GND t PHL t PLH VOH VM nY output VM VOL mna344 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 10. Test data Supply voltage Load VEXT VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width RL = 1 MΩ. 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 8 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 13. Additional characteristics Rbias = 560 kΩ VCC 0.47 µF input output 100 µF VI (f = 1 kHz) A IO GND mna050 ∆I O g fs = --------∆V I VO is constant. Fig 9. Test set-up for measuring forward transconductance 001aad074 30 gfs (mA/V) 20 10 0 0 1 2 3 4 VCC (V) Tamb = 25 °C. Fig 10. Typical forward transconductance as a function of supply voltage 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 9 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 14. Application information Some applications for the 74AUP2GU04 are: • Linear amplifier (see Figure 11) • Crystal oscillator (see Figure 12) Remark: All values given are typical values unless otherwise specified. R2 VCC 1 µF R1 U04 ZL mna052 ZL > 10 kΩ. R1 ≥ 3 kΩ. R2 ≤ 1 MΩ. Open loop amplification: AOL = 20. A OL R1 1 + ------- ( 1 + A OL ) R2 Voltage amplification: A V = – ----------------------------------------- . Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC. Unity gain bandwidth product is 5 MHz. Fig 11. Linear amplifier application R1 R2 U04 C1 C2 out mna053 C1 = 47 pF. C2 = 22 pF. R1 = 1 MΩ to 10 MΩ. R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz). Fig 12. Crystal oscillator application 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 10 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 13. Package outline SOT363 (SC-88) 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 11 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 14. Package outline SOT886 (XSON6) 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 12 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 15. Package outline SOT891 (XSON6) 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 13 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2GU04_2 20090703 Product data sheet - 74AUP2GU04_1 Modifications: • Section 8 “Limiting values”: Changed: Derating factor XSON6 packages. • Section 10 “Static characteristics”: Changed: conditions for HIGH-level output voltage and LOW-level output voltage. • Section 11 “Dynamic characteristics”: Changed: typical power dissipation capacitance. 74AUP2GU04_1 20061215 Product data sheet 74AUP2GU04_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 14 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP2GU04_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 July 2009 15 of 16 74AUP2GU04 NXP Semiconductors Low-power dual unbuffered inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Additional characteristics . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 July 2009 Document identifier: 74AUP2GU04_2