INTEGRATED CIRCUITS 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) Product specification Supersedes data of 1995 Aug 03 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) When nOE is Low, the latched or transparent data appears at the outputs. When nOE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus. FEATURES • 16-bit transparent latch • Multiple VCC and GND pins minimize switching noise • Power-up 3-State • Live insertion/extraction permitted • Power-up reset • 3-State output buffers • 74ABTH16373B incorporates bus-hold data inputs which Two options are available, 74ABT16373B which does not have the bus-hold feature and 74ABTH16373B which incorporates the bus-hold feature. PIN CONFIGURATION eliminate the need for external pull-up resistors to hold unused inputs • Output capability: +64mA/–32mA • ICCL –19 mA maximum • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model DESCRIPTION The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates. The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation. 1OE 1 48 1E 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2E SA00379 QUICK REFERENCE DATA SYMBOL PARAMETER tPLH tPHL Propagation delay Dn to Qn CIN Input capacitance COUT Output capacitance ICCZ Quiescent su supply ly current ICCL CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT CL = 50pF; VCC = 5V 2.5 2.0 ns VI = 0V or VCC 4 pF VO = 0V or VCC; 3-State 7 pF Outputs disabled; VCC = 5.5V 500 µA Outputs low; VCC = 5.5V 8 mA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin SSOP type III PACKAGES –40°C to +85°C 74ABT16373B DL BT16373B DL SOT370-1 48-Pin TSSOP type II –40°C to +85°C 74ABT16373B DGG BT16373B DGG SOT362-1 48-Pin SSOP type III –40°C to +85°C 74ABTH16373B DL BH16373B DL SOT370-1 48-Pin TSSOP type II –40°C to +85°C 74ABTH16373B DGG BH16373B DGG SOT362-1 1998 Feb 27 2 853-1751 19027 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) PIN DESCRIPTION LOGIC SYMBOL (IEEE/IEC) PIN NUMBER SYMBOL FUNCTION 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 1D0 – 1D7 2D0 – 2D7 Data inputs 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1Q0 – 1Q7 2Q0 – 2Q7 Data outputs 1, 24 1OE, 2OE Output enable inputs (active-Low) 1OE 1 1EN 1E 48 C3 2OE 24 2EN 2E 25 C4 1D0 47 3D 2 1Q0 1D1 46 3 1Q1 1D2 44 5 1Q2 1D3 43 6 1Q3 1D4 41 8 1Q4 1D5 40 9 1Q5 1D6 38 11 1Q6 1D7 37 12 1Q7 2D0 36 13 2Q0 2D1 35 14 2Q1 2D2 33 16 2Q2 2D3 32 17 2Q3 2D4 30 19 2Q4 1LE 2D5 29 20 2Q5 1OE 2D6 27 22 2Q6 2D7 26 23 2Q7 48, 25 Enable inputs (active-High) 1E, 2E 4, 10, 15, 21, 28, 34, 39, 45 GND 7, 18, 31, 42 Ground (0V) Positive supply voltage VCC LOGIC SYMBOL 47 46 44 43 41 40 38 37 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1∇ 2∇ 4D SA00380 2 3 5 6 8 9 11 12 36 35 33 32 30 29 27 26 2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 2LE 24 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 13 14 16 17 19 20 22 23 SA00044 LOGIC DIAGRAM nD0 nD1 D E nD2 D Q E nD3 D Q E nD4 D Q nD5 D E Q E nD6 D Q E nD7 D Q E D Q E Q nLE nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 SA00046 1998 Feb 27 3 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) FUNCTION TABLE INPUTS OUTPUTS nOE nE nDx INTERNAL REGISTER L L H H L H L H L H Enable and read register L L ↓ ↓ i h L H L H Latch and read register L L X NC NC H H L H X Dn NC Dn Z Z H = h = L = l = NC= X = Z = ↓ = nQ0 – nQ7 OPERATING MODE Hold Disable outputs High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don’t care High impedance “off” state High-to-Low E transition ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER DC input diode current VI DC input DC output diode current DC output voltage3 IOUT O DC output current Tstg Storage temperature range RATING UNIT –0.5 to +7.0 V –18 mA VI < 0 voltage3 IOK VOUT CONDITIONS DC supply voltage –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 output in High state –64 mA °C –65 to 150 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER MIN DC supply voltage MAX UNIT 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1998 Feb 27 2.0 4 V Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER MIN VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage VRST Power-up output voltage3 II Input leakage g current 74ABT16373B II Input leakage current 74ABTH16373B VCC = 4.5V; IIK = –18mA MAX –0.9 –1.2 MIN MAX –1.2 V 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V 5V; VI = VCC or GND VCC = 5 5.5V; ±0 01 ±0.01 ±1 ±1 µA ±0.01 ±1 ±1 µA 0.01 1 1 µA –1 –3 –5 µA VCC = 5.5V; VI = VCC Control pins Data pins5 VCC = 5.5V; VI = 0 VCC = 4.5V; VI = 0.8V Bus Hold current A inputs6 74ABTH16373B TYP UNIT VCC = 4.5V; IOH = –3mA; VI = VIL or VIH VCC = 5.5V; VI = VCC or GND IHOLD Tamb = –40°C to +85°C Tamb = +25°C TEST CONDITIONS 50 50 VCC = 4.5V; VI = 2.0V –75 –75 VCC = 5.5V; VI = 0 to 5.5V ±800 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = GND ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or VIH 0.5 10 10 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or VIH Output current1 VCC = 5.5V; VO = 2.5V Output High leakage current IOFF IPU/IPD IO ICEX ICCH ICCL Quiescent supply current µA mA 50 50 µA 0.5 2 2 mA 8 19 19 mA 0.5 2 2 mA –10 –70 –180 VCC = 5.5V; VO = 5.5V; VI = GND or VCC 0.1 VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC ICCZ –10 –180 –0.5 –50 –50 ∆ICC Additional supply current per input pin2 74ABT16373B VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 5 100 100 µA ∆ICC Additional supply current per input pin2 74ABTH16373B VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1 to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 5. Unused pins at VCC or GND. 6. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 27 5 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40 to +85°C VCC = +5.0V ±0.5V MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay nDx to nQx 2 1.5 1.1 2.5 2.0 3.8 3.1 1.5 1.1 4.4 3.8 ns tPLH tPHL Propagation delay nE to nQx 1 1.6 1.3 2.5 2.1 3.8 3.1 1.6 1.3 4.4 3.6 ns tPZH tPZL Output enable time to High and Low level 4 5 1.2 1.3 2.3 2.3 3.5 3.5 1.2 1.3 4.6 4.5 ns tPHZ tPLZ Output disable time from High and Low level 4 5 1.9 1.7 3.1 2.6 4.5 3.8 1.9 1.7 5.3 4.2 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40 to +85°C VCC = +5.0V ±0.5V MIN TYP MIN UNIT ts(H) ts(L) Setup time, High or Low nDx to nE 3 1.0 1.0 0.0 0.3 1.0 1.0 ns th(H) th(L) Hold time, High or Low nDx to nE 3 0.5 0.5 –0.2 0.0 0.5 0.5 ns tw(H) Enable pulse width High 1 2.5 1.0 2.5 ns AC WAVEFORMS For all waveforms, VM = 1.5V. nE VM VM VM nDx VM VM SA00047 1998 Feb 27 tPHL tPLH nQx Waveform 1. VM tPLH tw(H) tPHL nQx VM VM VM SA00048 Propagation Delay, Enable to Output, and Enable Pulse Width Waveform 2. Propagation Delay for Data to Outputs 6 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) nDx ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM VM ts(H) VM ts(L) th(H) nE VM nOE VM VM th(L) VM tPZL tPLZ VM VM nQx VOL + 0.3V VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00051 SA00049 Waveform 3. Data Setup and Hold Times VM nOE Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level VM tPZH tPHZ VOH nQx VOH – 0.3V VM 0V SA00050 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VOUT VIN tW 90% VM NEGATIVE PULSE 10% 0V tTHL (tF) CL tTLH (tR) tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. AMP (V) VM 10% RL D.U.T. RT 90% FAMILY 74ABT/H16 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00018 1998 Feb 27 7 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 1998 Feb 27 8 SOT370-1 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1998 Feb 27 9 SOT362-1 Philips Semiconductors Product specification 74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State) Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 05-96 9397-750-03491