PHILIPS CX24109-11Z

CX24109
Digital Satellite Tuner
Rev. 01 — 13 November 2008
Document information
Info
Keywords
Abstract
Content
Product data sheet
CX24109
NXP Semiconductors
Digital Satellite Tuner
Ordering information
Type number
CX24109-11
Description
Package
Digital Satellite Tuner
48-pin eTQFP
CX24109-11Z
Revision history
Revision
01
Date
20081113
Description
First NXP version based on the Conexant 102031A data sheet.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
2
CX24109
NXP Semiconductors
Digital Satellite Tuner
General description
The CX24109 is a highly integrated, direct down-conversion satellite tuner intended for
high-volume digital video, audio, and data receivers. When combined with the CX24121
QPSK demodulator/FEC decoder, the chip set provides a complete broadband satellite
front-end solution capable of operating from 1–45 MSps in the most demanding satellite
environments. It is compatible with international standards such as DVB and DSS. The
highly integrated CX24109 reduces the tuner BOM cost and simplifies the RF layout.
Features
‹
‹
‹
‹
‹
Zero-IF architecture eliminates the need for image reject filtering
Integrated LNA
Integrated LO with onboard VCO and synthesizer
Single +5 V supply
Reference oscillator output for demodulator
Applications
‹
‹
‹
DBS set-top boxes
Commercial digital video, audio, and data receivers
Digital VCRs
Block diagram
VGA1
Variable Low
Pass Filter
VGA2
I Channel
Output
VCA
90
RF
Input
0
VGA1
Variable Low
Pass Filter
VGA2
Q Channel
Output
Reference
Oscillator
VCO
PLL
Dividers, Phase Detector,
and Charge Pump
Reference Programming Lock
to DEMOD and Control Detect
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
3
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
4
CX24109
NXP Semiconductors
Digital Satellite Tuner
Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3
Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5
AGC and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6
Local Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.7
Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.7.1
Gain Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7.2
Frequency Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7.3
Recommended Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1
AGC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2
VCO Power Pin Ripple Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4
Example Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3
Parametric Data and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1.1
Standard Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
5
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
6
CX24109
NXP Semiconductors
Digital Satellite Tuner
Figures
Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
CX24109 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QPSK Demodulation Typical Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Schematic (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Schematic (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflection Coefficient at Input of CX24109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband Filter Gain vs. Frequency and FILTUNE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter –3 dB Bandwidth vs. FILTUNE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain and IIP3 vs. AGC Voltage at 950 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain and IIP3 vs. AGC Voltage at 2150 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain and NF vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain and NF vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48-pin eTQFP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48-pin eTQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CX24109_N_1
Product data sheet
11
13
14
16
16
24
25
26
27
27
28
28
29
29
33
36
37
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
7
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
8
CX24109
NXP Semiconductors
Digital Satellite Tuner
Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Band Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VGA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended AGC Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended VCO Frequency vs. Charge Pump Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Charge Pump Polarity and Reference Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RF Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CX24109_N_1
Product data sheet
11
12
16
18
19
20
21
22
22
22
31
31
32
32
33
36
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
9
CX24109
NXP Semiconductors
Digital Satellite Tuner
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
10
CX24109
Chapter 1: Functional Description
Rev. 01 — 13 November 2008
VCC
GND
GND
VCC
GND
VCC
GND
VCC
GND
VCC
AGC
47
46
45
44
43
42
41
40
39
38
37
CX24109 Pin Diagram
GND
Pinout Information
Figure 1.
48
1.1
Product data sheet
VCC
1
36
FILTUNE
GND
2
35
IOUTN
GND
3
34
IOUTP
RFIN
4
33
GND
RFGND
5
32
QOUTN
GND
6
31
QOUTP
30
GND
CX24109
GND
7
DCIP
8
29
VCC
24
22
VCC
23
21
GND
GND
20
CLKREFOUT
19
GND
LPFILT
LD
18
25
VCC
12
17
TUNERES
XTAL2
EN
16
26
15
11
GND
DCQN
XTAL1
DATA
14
CLK
27
GND
28
10
13
9
VCC
DCIN
DCQP
102031_002
1.2
Pin Description
Table 1.
Pin Description
Pin Name
Pin No.
I/O
Description
RFIN
4
I
RF input signal pin.
AGC
37
I
AGC control input from the demodulator/FEC IC. It controls the gain of the RF attenuator
and both baseband amplifiers. Minimum gain occurs at minimum voltage. Input impedance
zin = 1 MΩ//20 pF..
FILTUNE
36
I
Baseband filter control input from the demodulator/FEC IC.
Minimum BW occurs at minimum voltage. Zin = 17 kΩ//20 pF.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
11
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 1.
Pin Description
Pin Name
Pin No.
I/O
Description
12
—
Filter reference. A resistor to ground from this pin sets the reference current for the tunable
filter. See Figure 6 and Figure 7.
IOUTP, IOUTN
34, 35
O
I channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout
= 1 kΩ//10 pF.
QOUTP, QOUTN
31, 32
O
Q channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout
= 1 kΩ//10 pF.
8, 9
—
I channel DC offset cancellation. A capacitor must be placed between these pins. See
Figure 6 and Figure 7.
10, 11
—
Q channel DC offset cancellation. A capacitor must be placed between these pins. See
Figure 6 and Figure 7.
LPFILT
20
—
Loop filter. A network with a capacitor in parallel with a series resistor and capacitor
connected from this pin to ground determines the loop filter bandwidth. See Figure 6 and
Figure 7.
CLKREFOUT
24
O
Clock reference output. This pin provides the reference clock for the demodulator/FEC IC.
The maximum load allowed at this node is ZLOAD = 10 kΩ//20 pF.
XTAL1, XTAL2
16, 17
—
Crystal inputs. A 10.111 MHz, series-resonant, fundamental crystal is placed between
these two pins to create the system clock. See Figure 6 and Figure 7.
CLK
28
I
Serial bus clock signal.
EN
26
I
Serial bus latch enable.
DATA
27
I
Serial bus data pin.
LD
25
O
The lock detect signal to the demodulator/FEC IC.
ZLOAD = 10 kΩ//20 pF. High is the locked state.
TUNERES
DCIP, DCIN
DCQP, DCQN
Table 2.
Power Supply and Ground Pins
Pin Name
Pin No.
I/O
VCC
1, 13, 18, 22,
29, 38, 40,
42, 44, 47
P
+5 V power supply
GND
2, 3, 5, 6, 7,
14, 15, 19,
21, 23, 30,
33, 39, 41,
43, 45, 46, 48
P
Ground
1.3
Description
Application Overview
Several million Satellite Set-Top Boxes (STBs) are deployed in many different entertainment
networks around the world today. The standards for each network may vary a little but the
requirements for the tuner in the STB are essentially the same. Each receiver system in the
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
12
CX24109
NXP Semiconductors
Chapter 1: Functional Description
network requires an antenna, a Low Noise Block (LNB) downconverter, a drop cable, and an
STB. The LNB converts the satellite downlink frequency to an intermediate L-band frequency
where it is passed to the STB via the drop cable. The STB front end consists of a tuner and a
demodulator/FEC IC. The satellite tuner must tune to the L-band frequency, downconvert the
carrier, and separate it to baseband I and Q signals. The demodulator/FEC IC includes
QPSK Demodulation, carrier tracking, AGC control, bit timing, and the required FEC for a
given network service. Figure 2 illustrates a typical application block diagram for the
CX24109/CX24121 chip set in an STB front end.
Figure 2.
QPSK Demodulation Typical Application Block Diagram
LNB
CX24109
RF Tuner IC
Dish
Antenna
CX24121
Demod/FEC IC
IOUTP
Drop
Cable
RFIN
IOUTN
I_N
QOUTN
Q_N
RS_DATA[7:0]
RS_CLK
QOUTP
XTAL1
AGC
XTAL2
FILTUNE
RSCntl1
AGCV
8
To
MPEG
Processor
RSCntl2
FILTERV
XTAL_IN
LD
TUNERES
Tuner_Data
Tuner_Clk
LD
Tuner_En
CONTROL
LPFILT
CLKREFOUT
Tuner Control
3
102031_003
1.4
Signal Path
The CX24109 is a highly integrated, direct-down conversion satellite tuner. It consists of an
LNA, variable RF attenuator, quadrature downconverter, variable IF gain amplifiers, variable
low-pass filters, VCO, and synthesizer. A detailed block diagram of the IC is illustrated in
Figure 3.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
13
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Figure 3.
Detailed Functional Block Diagram
VGA1
Variable Low
Pass Filter
VGA2
IOUTP
IOUTN
VCA
TUNERES
90 Degree
Splitter and
Divide by
2 or 4
RFIN
QOUTP
QOUTN
FILTUNE
AGC
Control
AGC
LPFILT
Crystal
Cell
XTAL1
XTAL2
Divide by
10, 20, 40
Phase
Detector
Charge
Pump
Voltage
Controlled
Oscillator
CLKREFOUT
CLK
DATA
EN
9 Bit
Counter
32/33
Prescaler
Divide
by 2
Control
Interface
5 Bit
Counter
Lock
Detect
LD
102031_004
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
14
CX24109
NXP Semiconductors
Chapter 1: Functional Description
The L-band output from the LNB enters the IC through the RFIN pin and is immediately
amplified by the Voltage Controlled Attenuator block (VCA). The VCA functions as a variable
gain LNA. The noise figure and gain of the VCA are the dominant factors for the tuner’s noise
figure. The signal is then quadrature downconverted to I and Q baseband channels.
Additional amplifiers at baseband provide more variable gain for the AGC loop. Also at
baseband, variable low-pass filters provide anti-alias filtering and eliminate noise power from
adjacent carriers and spurious signals before they can impact the A/Ds in the demodulator
IC.
1.5
AGC and Control
The AGC functionality for the CX24109 is split between the RF and baseband sections, and
provides 80 dB of variable gain. The primary control for the AGC is an analog voltage from
the demodulator IC. Programmable adjustments to the slope and offset of each variable gain
component in the tuner are available through the AGC control registers. Programming
information for the VGA and VCA is provided in Tables 4 and 5, respectively. The
recommended default values for the programmable control bits versus symbol rate are listed
in Table 8.
1.6
Local Oscillator
The local oscillator consists of a synthesizer and a VCO block, and is contained entirely
within the CX24109. The VCO block uses an innovative architecture that requires only a 5 V
source, eliminating the need for a 28 V power supply. It includes the required tank circuit.
The VCO block consists of a bank of eight oscillators operating at twice and four times the
input frequency with a continuous range from 2200 MHz to 4400 MHz. The VCOs overlap to
cover the frequency range from 950 MHz to 2150 MHz under all voltage, temperature, and
process variations. The VCO tuning range, combined with programmable ÷2 or ÷4 frequency
dividers, creates the continuous frequencies from 950 MHz to 2150 MHz for the local
oscillator. A simple tuning algorithm must be run by the host processor one time at power-up
to calibrate the VCO block. Conexant provides this program.
The synthesizer is also contained within the CX24109. It uses a 10.111 MHz reference
frequency and a reference divider, ÷R, to set the phase comparison frequency. Two
programming bits are used to configure the reference divider to divide by 10, 20, or 40, which
in turn sets the comparison frequency to 1.0111 MHz, 505 kHz, or 253 kHz, respectively. A
reference divider of 10 is recommended. The comparison frequency also determines the
frequency step size of the local oscillator. Another programmable divider is provided for the
VCO output. It consists of a 32/33 prescaler, a 9-bit N-counter (N-divider), a 5-bit A-counter
(A-divider), and a fixed ÷ 2 block. The programmable divider divides the VCO output from its
highest frequency to the minimum phase comparison frequency. The programmable charge
pump includes output currents of 1 mA, 2 mA, 3 mA, and 4 mA. Programming information for
the synthesizer can be found in Table 7. The recommended values for charge pump current,
polarity, and referenced dividers are listed in Tables 9 and 10.
The typical loop filter bandwidth is set with external passive components and should be set
between 8 kHz and 15 kHz.
1.7
Programming Interface
A three-wire serial interface with Clock, Data, and Enable lines is used to program the
CX24109. All digital signals are CMOS-compatible. The serial data carries the binary settings
for the programmable dividers, the VCO band select, the voltage-controlled attenuator, and
the voltage-controlled amplifiers. When the Enable line is low, data is shifted into an internal
shift register on the rising edge of the clock, and when the Enable line goes high, the stored
data is latched. The clock signal should be kept low when inactive. The maximum clock rate
is 1 MHz. Figure 4 illustrates the relationship between the Clock, Data, and Enable signals.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
15
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Figure 4.
Serial Interface Programming Example
Clock
...
Data
...
Enable
102031_005
The internal shift register in the CX24109 is 21 bits long. When the data is latched into the IC,
the two MSBs act as control bits, and the lower 19 bits are the data bits as illustrated in
Figure 5. Data must be entered MSB first.
Figure 5.
Programming Word Configuration
LSB
MSB
d20 d19
d18 d17 d16 d15 d14 d13
d12 d11 d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
Data Bits
Control
Bits
102031_006
The control bits determine the functional block that is being programmed, while the data bits
contain the specific control information. Table 3 provides a detail mapping of the control and
data bits.
Table 3.
Programming Bit Mapping (Sheet 1 of 2)
Programming Bit Mapping
20
MSB
19
18
17
16
15
14
13
12
11
10
9
8
V
R(1)
7
6
5
4
3
2
1
0
LSB
Band Select
0
0
R
R
R
R
R
R
R
R(1)
R
Band Select
VGA Programming
0
1
R
VGA2 Offset
VGA1 Offset
VCA Programming
1
0
R
VCA Offset
VCA Slope
PLL Programming
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
16
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 3.
Programming Bit Mapping (Sheet 2 of 2)
Programming Bit Mapping
1
1
÷R Divider
P
Charge
Pump
Current
÷ N Divider(2)
MSB
LSB
MSB
÷A Divider(2)
LSB
GENERAL NOTES:
1. R means Reserved except for ÷R which means reference divider.
P means Charge Pump Polarity
V means VCO Divide Select
FOOTNOTES:
(1) These Reserved locations must be set to zero. All other Reserved location values do not matter.
(2) These Divide ratios are binary coded.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
17
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 4.
Band Select Programming
Band Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Typical Receive
Frequency Range
(MHz)
VCO
Number
VCO
Divider
0
1
0
0
0
0
0
0
950–1019
7
4
1
0
0
0
0
0
0
0
1019–1075
8
4
0
0
0
0
0
0
0
1
1075–1178
1
2
0
0
0
0
0
0
1
0
1178–1296
2
2
0
0
0
0
0
1
0
0
1296–1432
3
2
0
0
0
0
1
0
0
0
1432–1576
4
2
0
0
0
1
0
0
0
0
1576–1718
5
2
0
0
1
0
0
0
0
0
1718–1856
6
2
0
1
0
0
0
0
0
0
1856–2036
7
2
1
0
0
0
0
0
0
0
2036–2150
8
2
VCO Divide Select
Bit 9
Function
0
÷4
1
÷2
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
18
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 5.
VGA Programming
VGA1 Offset
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset in dB
1
1
1
1
1
1
1
1
0
–27.0
1
1
1
1
1
1
1
0
0
–28.5
1
1
1
1
1
1
0
0
0
–30.0
1
1
1
1
1
0
0
0
0
–31.5
1
1
1
1
0
0
0
0
0
–33.0
1
1
1
0
0
0
0
0
0
–34.5
1
1
0
0
0
0
0
0
0
–36.0
1
0
0
0
0
0
0
0
0
–37.5
0
0
0
0
0
0
0
0
0
–39.0
VGA2 Offset
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Offset in dB
1
1
1
1
1
1
1
1
0
35
1
1
1
1
1
1
1
0
0
32
1
1
1
1
1
1
0
0
0
29
1
1
1
1
1
0
0
0
0
26
1
1
1
1
0
0
0
0
0
23
1
1
1
0
0
0
0
0
0
20
1
1
0
0
0
0
0
0
0
17
1
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
11
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
19
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 6.
VCA Programming
VCA Slope
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slope in dB/V
0
0
0
0
0
0
0
0
1
47.0
0
0
0
0
0
0
0
1
1
49.5
0
0
0
0
0
0
1
1
1
52.0
0
0
0
0
0
1
1
1
1
54.5
0
0
0
0
1
1
1
1
1
57.0
0
0
0
1
1
1
1
1
1
59.5
0
0
1
1
1
1
1
1
1
62.0
0
1
1
1
1
1
1
1
1
64.5
1
1
1
1
1
1
1
1
1
67.0
VCA Offset
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Offset in dB
0
0
0
0
0
0
0
0
1
90.00
0
0
0
0
0
0
0
1
1
94.25
0
0
0
0
0
0
1
1
1
98.50
0
0
0
0
0
1
1
1
1
102.75
0
0
0
0
1
1
1
1
1
107.00
0
0
0
1
1
1
1
1
1
111.25
0
0
1
1
1
1
1
1
1
115.50
0
1
1
1
1
1
1
1
1
119.75
1
1
1
1
1
1
1
1
1
124.00
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
20
CX24109
NXP Semiconductors
Chapter 1: Functional Description
Table 7.
PLL Programming
Charge Pump Current
Bit 15
Bit 14
Current (mA)
0
0
1
0
1
2
1
0
3
1
1
4
Charge Pump Polarity
Bit 16
Function
0
Positive
1
Negative
Reference Dividers
1.7.1
Bit 18
Bit 17
Function
0
0
—
0
1
Reserved
1
0
Reserved
1
1
÷10
Gain Equations
The RF block voltage gain (GRF) is equal to the VCA gain + the mixer gain.
G RF = V AGC × VCA Slope – VCA Offset ( in dB ) + 23
where the maximum value of G RF is 23 dB, regardless of voltage
VGA1 voltage gain ( G VGA1 ) is equal to
G VGA1 = V AGC × 26 + VGA1 Offset ( in dB )
VGA2 voltage gain ( G VGA2 ) is equal to
G VGA2 = VGA2 Offset ( in dB )
The total baseband voltage gain ( GBaseband ) is equal to
G Baseband = G VGA1 + G Filter + G VGA2
= G VGA1 + 3 + G VGA2
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
21
CX24109
NXP Semiconductors
Chapter 1: Functional Description
1.7.2
Frequency Equations
The VCO frequency is determined by
F VCO = ( F Crystal ÷ R ) × ( N + ( A ÷ 32 ) ) × 32 × 2
= ( 10.111 ÷ R ) × ( N + ( A ÷ 32 ) ) × 32 × 2
NOTE:
If A = 0, then N = N + 1
Remember, the incoming receive frequency is always lower than the VCO frequency, such
that:
F Receive = F VCO ÷ 2 or F VCO ÷ 4
1.7.3
Table 8.
Recommended Default Values
Recommended AGC Programming Values
VCA and VGA Slope and Offset vs. Symbol Rate
Condition
Symbol Rate
VCA Slope
(dB/V)
VCA Offset
(dB)(1)
VGA1 Slope
(dB/V)(2)
VGA1 Offset
(dB)
VGA2
Slope (dB/
V)(2)
VGA2 Offset
(dB)
FILTUNE
Voltage
(V)
1 to 5 MSps
52
98.5
(102.75)
26
–30
0
29
0.41
5 to 15 MSps
57
98.5
(107)
26
–33
0
17
0.90
15 to 45 MSps
59.5
98.5
(111.25)
26
–36
0
14
2.70
FOOTNOTES:
(1) There is an interaction between the offset and slope settings in the RF block, so the actual settings will be different from the theoretical
setting. Theoretical settings are given in parentheses.
(2)
These values are for reference only. They are not programmable.
Table 9.
Recommended VCO Frequency vs. Charge Pump Current
VCO Frequency
Charge Pump Current
Lower 50% VCO Frequency Range
2 mA
Upper 50% of VCO Frequency Range
3 mA
Table 10.
Recommended Charge Pump Polarity and Reference Divider Values
Feature
Specification
Charge Pump Polarity
Negative
÷10
Reference Divider
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
22
CX24109
Chapter 2: Applications
Rev. 01 — 13 November 2008
2.1
Product data sheet
AGC Input
To prevent excessive current draw, a 10 kΩ resistor on the AGC pin is recommended. See
Figure 6.
2.2
VCO Power Pin Ripple Requirement
Care must be taken to reduce the power supply ripple on pin 13 (VCO power supply) in order
to reduce phase noise. The power supply conditioning circuitry given in Figure 6 is suitable
for most circumstances.
2.3
Transmission Lines
Though the CX24109’s RF layout is simple, there are two transmission lines that must be
designed. The first transmission line is the LNB power line, which is located at the connector.
The second transmission line is between the connector and the RF IN pin. The input
transmission line must have a characteristic impedance of 75 Ω. The schematic gives
recommended dimensions assuming a two-layer FR-4 board.
2.4
Example Schematic
Figure 6 provides a simplified version of the CX24109/CX24121 reference design. For
complete and current reference design information, contact your local Conexant sales office.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
23
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 6.
Simplified Application Schematic (Page 1 of 2)
5 V_RF
LNB_POWER
C106
33 p
C104
47 p
C107
0.01 µF
C105
33 p
C108
33 p
L103
BEAD
C109
1n
C110
1n
1
4
5
3.3 pF
37
38
AGC
40
FILT_VCC
44
42
MIX_VCC
FILTUNE
FILTUNE
I_OUTN
I_OUTP
RF_GND
8
9
10
CLK
DC_QP
DATA
TUNERES
CKREF_OUT
LD
36
C111
0.047 µF
35
I_OUT
34
C112
0.047 µF
32
31
29
Q_OUT
C113
0.047 µF
28
CLK
27
DATA
26
LE
25
LD
24
SYNTH_VCC
22
LP_ILT
OSC_VCC
EN
20
C119
10 n
AGC2_VCC
DC_QP
13
R101
1.2 k
11
Q_OUTP
CX24109
DC_IN
GND (1)
C120
0.047 µF
DC_IP
18
C121
0.047 µF
XTA2
22 pF
Q_OUTN
17
2
AGC
RF_IN
XTA1
J1
ATTEN_VCC2
AGC1_VCC
1
VCO_VCC
3
ATTEN_VCC3
W = 1.4 mm
L = 1.6 mm
H < 10 mm FR-4
75 Ω
C101
16
RF_IN F Connector
C103
33 p
ATTEN_VCC1
47
W = 0.5 mm, L = 27 mm, H = 1.6 mm FR-4
CLKREF
_OUT
C114
1n
10.111
Series
C117
10 n
C116
6.8 n
C118
100 u
Y1
R105
8.2
R102
1.0 k
L102
BEAD
5 V_RF
C115
33 n
FOOTNOTE:
(1) Ground pins include: 2, 3, 5, 6, 7, 14, 15, 19, 21, 23, 30, 33, 39, 41, 43, 45, 46, and 48
102031_007
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
24
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 7.
Simplified Application Schematic (Page 2 of 2)
+3.3 V
R515
30.9 KΩ
1%
C536
0.01 uF
AGC
C534
0.01 uF
2
C533
0.01 uF
1
Vcm
FILTUNE
C532
0.01 uF
PWR (2)
C535
0.047 uF
Iref
C602
0.047 uF
AD_VAA
AD_VAA
AD_VDD
I_OUT
Q_OUT
72
3
5
CX24121
CLK
R203 300
DATA
68
LE
R204 300
R205 300
LD
R206
R208
300
CLKREF
_OUT
LD
C204
0.1 u
C205
100 p
C206
100 p
300
R207 10 K
C207
100 p
C209
0.1 u
67
66
65
63
64
55
56
GPIO_1 (LNB_DC)
LNB_22K
AGCV
FILTERV
LNB
Control
C208
0.1 u
41
11
79
77
80
78
(3)
RS_DATA
RS_CLK
RSCntl1
Interrupt (RSSYNC)
RSCntl2
TEST_MODE
XTAL_IN
32
37
47
38
To MPEG
Processor
I_N
Q_N
I_P
Q_P
C863
0.01 µF
GND (1)
C861
0.01 µF
TUNER_EN
TUNER_DATA
TUNER_CLK
SER_CLK
SER_DATA
45
46
R306
33
SER_CLK
SER_DATA
R307
33
FOOTNOTE:
(1) Ground Pins include: 4, 6, 8, 10, 15, 26, 30, 34, 50, 52, 62, 70, and 71.
(2) Core (1.8 V) power pins include: 7, 9, 14, 29, 49, and 69.
3.3 V power pins include: 25, 33, 51, and 61.
(3) RS_DATA includes RS_DATA0–RS_DATA7 pins 35, 31, 28, 27, 24, 23, 22, and 21.
102031_008
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
25
CX24109
NXP Semiconductors
Chapter 2: Applications
2.5
Typical Performance Curves
Figure 8.
Reflection Coefficient at Input of CX24109
CX24109 S11
m1
Freq = 950 MHz
plot_vs(S(1,1), freq) = –0.19 + j0.21
Impedance = 31.629 + j14.373
S11
m2
Freq = 1.20 GHz
plot_vs(S(1,1), freq) = 0.39/65.79
Impedance = 51.055 + j42.441
m3
Freq = 2.15 GHz
plot_vs(S(1,1), freq) = 0.29/–2.11
Impedance = 89.855 – j2.055
Frequency (950.0 MHz to 2.200 GHz)
102031_020
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
26
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 9.
Baseband Filter Gain vs. Frequency and FILTUNE Voltage
10
FILTUNE = 0.5 V
FILTUNE = 1.0 V
FILTUNE = 1.5 V
0
FILTUNE = 2.0 V
FILTUNE = 2.5 V
FILTUNE = 3.0 V
–10
Gain (dB)
–20
–30
–40
–50
–60
–70
0
5
10
15
20
25
30
35
40
45
Frequency (MHz)
Figure 10.
Filter –3 dB Bandwidth vs. FILTUNE Voltage
30
–3dB Bandwodth of Filter (MHz)
25
20
15
10
5
0
0
0.5
1
1.5
2
2.5
3
FILTUNE Voltage (V)
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
27
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 11.
Gain and IIP3 vs. AGC Voltage at 950 MHz
85
80
75
70
65
60
55
IIIP3
Gain and IIIP3 (dB)
50
Gain
45
40
35
30
25
20
15
10
5
0
–5
–10
1
1.5
2
2.5
3
AGC Voltage (V)
Figure 12.
Gain and IIP3 vs. AGC Voltage at 2150 MHz
85
80
75
70
65
60
Gain and IIIP3 (dB)
55
IIIP3
50
Gain
45
40
35
30
25
20
15
10
5
0
–5
–10
1.2
1.7
2.2
2.7
3.2
AGC Voltage (V)
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
28
CX24109
NXP Semiconductors
Chapter 2: Applications
Figure 13.
Gain and NF vs. AGC Voltage at 950 MHz
85
80
75
70
65
60
Gain and NF (dB)
55
Gain
50
Noise Figure
45
40
35
30
25
20
15
10
5
0
–5
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2
AGC Voltage (V)
Figure 14.
Gain and NF vs. AGC Voltage at 2150 MHz
85
80
75
70
65
60
Gain and NF (dB)
55
Gain
50
Noise Figure
45
40
35
30
25
20
15
10
5
0
–5
–10
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
3
3.1 3.2
AGC Voltage (V)
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
29
CX24109
NXP Semiconductors
Chapter 2: Applications
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
30
CX24109
Chapter 3: Parametric Data and Specifications
Rev. 01 — 13 November 2008
3.1
Electrical Specifications
Table 11.
Absolute Maximum Ratings
Parameter
3.1.1
Product data sheet
Minimum
Maximum
Units
Supply Voltage
–0.3
6
V
Input Voltage Range
–0.3
Vcc +0.3
V
Storage Temperature
–65
+150
°C
Junction Temperature
—
+150
°C
Standard Operating Conditions
All specifications are valid under the operating conditions indicated in Tables 8, 9, 10, and
12.
Table 12.
Operating Conditions
Parameter
Conditions
Min
Typ
Max
Units
Ambient Operating Temperature
—
0
+25
+70
°C
Maximum Operating Junction Temperature
—
—
—
125
°C
Supply Voltage
—
4.75
5.0
5.25
V
Reference Oscillator Frequency
Series resonant, fundamental
—
10.111
—
MHz
Reference Oscillator Frequency Stability
Including temperature drift
—
—
+100
ppm
—
10
—
kHz
Loop Filter Bandwidth
—
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
31
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 13.
DC Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Supply Current(1)
—
—
244
262
mA
Usable AGC Voltage Range, VAGC
—
1.3
—
2.80
V
at DC
—
1
—
MΩ
AGC Current, IAGC
—
—
—
0.4
mA
Usable Filtune Voltage Range, VFiltune
—
0
—
3.0
V
Impedance of Filtune Input
at DC
—
17
—
kΩ
Thermal Resistance of Package
θja(2)
—
42
—
°C/W
θjc
—
8.7
—
°C/W
Impedance of AGC Input
FOOTNOTES:
Using 15–45 MSps programming values (see Table 8), Vcc = 5.0 V, VAGC = 1.45 V, VFiltune = 2.7 V.
(2) Using a 2-layer CX24109/CX24121 reference design, where the package’s exposed paddle is connected to the printed circuit board ground plane
using thermal vias. The ground plane on the reference design is approximately 2-7/8 inches x 1-1/4 inches. Better thermal performance can be
obtained by increasing ground plane coverage or increasing the number of attached printed circuit board layers.
(1)
Table 14.
AC Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Programming Clock Frequency
—
—
—
1
MHz
See Figure 15.
—
10
—
ns
Data Hold, tHD
—
10
—
ns
Enable Pulse
Width, tEW
1
—
—
μs
Clock to Enable,
tCE
—
1
—
μs
Bus Timing
Programming Lines:
Clock, Data, Enable
LD and CLKREFOUT
Data Setup, tSU
VIH
—
2.1
—
—
V
VIL
—
—
—
0.8
V
IIH
—
—
—
0.5
mA
IIL
—
—
—
–0.5
mA
VOH
—
2.3
2.65
—
V
VOL
—
—
0.9
1.125
V
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
32
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Figure 15.
Serial Programming Example
Clock
...
Data
...
tHD
tsu
Enable
tce
tew
102031_016
Table 15.
RF Electrical Characteristics (Sheet 1 of 3)
Parameter
Conditions
Min
Typ
Max
Units
—
950
—
2150
MHz
–81
—
–23
dBm
—
—
–7
dBm
—
75
—
Ω
—
10
—
dB
Tuning Frequency
Input Power, Single Tone(1)
Depends on bandwidth of incoming signal
and C/I
Aggregate Input Power(1)(2)
Input Impedance, Balanced(1)
—
ZSOURCE = 75 Ω
—
Input VSWR(1)
Iout and Qout Output Voltage
RLoad = 1 kΩ
—
0.5
—
VP-P
Maximum Conversion (Voltage) Gain
VAGC=2.4 V, 1 MSps gain coefficients(1)
76
86
91
dB
Minimum Conversion (Voltage) Gain
VAGC=1.45 V, 45 MSps gain coefficients(1)
8
18
23
dB
Noise Figure (NF)(1) (3)
Pin = –43 dBm,
1–5 MSps gain coefficients(4)
—
36
42
dB
Pin = –81 dBm,
1–5 MSps gain coefficients(5)
—
10.5
14
dB
Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
—
35
42
dB
Pin = –72 dBm,
5–15 MSps gain coefficients(7)
—
10.5
14
dB
Pin = –30 dBm,
15–45 MSps gain coefficients(8)
—
35
45
dB
Pin = –70 dBm,
15–45 MSps gain coefficients(9)
—
10.5
14
dB
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
33
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 15.
RF Electrical Characteristics (Sheet 2 of 3)
Parameter
IIP3 (Out-of-band)(1) (4)
IIP3I (Inband)
Conditions
Min
Typ
Max
Units
+(31 and 60) MHz, Pin = –42 dBm,
1–5 MSps gain coefficients(4)
–2
4.0
—
dBm
+(91 and 180) MHz, Pin = –42 dBm,
1–5 MSps gain coefficients(4)
5.5
9.4
—
dBm
+(31 and 60) MHz, Pin = –81 dBm,
1–5 MSps gain coefficients
–35
–25.0
—
dBm
+(91 and 180) MHz, Pin = –81 dBm,
1–5 MSps gain coefficients(5)
–39
–7.2
—
dBm
+(31 and 60) MHz, Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
0
5.0
—
dBm
+(91 and 180) MHz, Pin = –34.5 dBm,
5–15 MSps gain coefficients(6)
5.5
9.8
—
dBm
+(31 and 60) MHz, Pin = –72 dBm,
5–15 MSps gain coefficients(7)
–35
–25.5
—
dBm
+(91 and 180) MHz, Pin = –72 dBm,
5–15 MSps gain coefficients(7)
–30
–6.5
—
dBm
+(31 and 60) MHz, Pin = –30 dBm,
15–45 MSps gain coefficients(8)
–2
5.5
—
dBm
+(91 and 180) MHz, Pin = –30 dBm,
15–45 MSps gain coefficients(8)
5.7
10.5
—
dBm
+(31 and 60) MHz, Pin = –70 dBm,
15–45 MSps gain coefficients(9)
–35
–24.5
—
dBm
+(91 and 180) MHz, Pin = –70 dBm,
15–45 MSps gain coefficients(9)
–28
–6.5
—
dBm
1 MSps coefficients and VAGC = 1. 5 V(1)
—
–30
—
dBm
1 MSps coefficients and VAGC = 2.4 V(1)
—
–65
—
dBm
I/Q Phase Difference
—
—
3
13
+deg
I/Q Amplitude Ratio
—
—
1
3
+dB
LO Leakage
950 to 2150 MHz(1)
—
–80
–70
dBm
2LO-RF Rejection
C/I = 10 dB VAGC = 1.5 V(1)
–30
–45
—
dB
2RF-LO Rejection
C/I = 10 dB(1)
–30
–50
—
dB
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
34
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 15.
RF Electrical Characteristics (Sheet 3 of 3)
Parameter
Conditions
Min
Typ
Max
Units
VCO and Synthesizer
Reference Oscillator Phase Noise
Measured at 400 Hz
—
–130
—
dBc/Hz
Spurious
At 1, 10.111, and 30 MHz offsets
with 2 mA charge pump and
10 kHz loop BW
–30
–45
—
dBc
100
—
330
MHz/V
10 kHz offset
—
–75
—
dBc/Hz
100 kHz offset
—
–97
—
dBc/Hz
10 kHz offset
—
–69
—
dBc/Hz
100 kHz offset
—
–94
—
dBc/Hz
LO Phase Noise at 950 MHz–2150 MHz
10 kHz offset +100 kHz offset
—
—
–158
dBc/Hz
Local Oscillator Settling Time
All frequencies, VCOs and modes
—
1
—
ms
VCO Tuning Sensitivity
LO Phase Noise at 950 MHz–1450 MHz
LO Phase Noise at 1450 MHz–2150 MHz
—
GENERAL NOTES:
1. Values in this table are valid under the operating conditions listed in Tables 8, 9, and 10, using a reference divider of 10, unless otherwise
stated.
FOOTNOTES:
(1) This measurement is made at RFIN of CX24109.
(2) Aggregate average power of 40 QPSK modulated carriers.
(3) All NF and IIP3 measurements/specifications are made by setting a specific input level for the desired symbol rate and adjusting the AGC
level to obtain the desired output level of 0.5 Vpp.
(4) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 1 MSps.
Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 1 MHz), thus, Pin = –23 dBm – 7 dB – 10 log (20 / 1) = –43 dBm.
(5) This level is derived from Pin = P
Transponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 1 MSps and
PTransponder is at a minimum. PTransponder = 10 log ((1E6 / 45E6) 10 (82 – 4) /10) = +61 dBm. Therefore, Pin = + 61 dBm – 205 dB + 38 dB +
45 dB – 20 dB = –81 dBm.
(6) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 7 MSps.
Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 7 MHz), thus, Pin = –23 dBm – 7 dB – 10 log 20 / 7 = –34.5 dBm.
(7)
This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 7 MSps and
PTransponder = 10 log ((7E6 / 45E6) 10 (82–4)/10) = +70 dBm. Therefore, Pin = +70 dB – 205 dB + 38 dB + 45 dB – 20 dB = –72 dBm
This level is derived assuming –23 dBm is the maximum level of all other transponders, an operating symbol rate of 20 MSps and a C/I of
7 dB.
(9) Assume a symbol rate of 20 MSps.
(8)
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
35
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Table 16.
Baseband Frequency Response
Parameter
Conditions
Min
Typ
Max
Units
Minimum Cutoff Frequency, F1 dB
Measured at minimum VFiltune
1.4
—
2.6
MHz
Minimum Cutoff Frequency, F1 dB
Measured at maximum VFiltune
27
—
—
MHz
Tuning Voltage Transfer Function
0 V < VFiltune < 3.0 V
—
10.5
—
MHz/V
Passband Ripple
0 < Freq < F1 dB
—
—
1.0
dB
Stopband Attenuation
F > 2.6 × F1 dB
35
—
—
dB
Stopband Attenuation
5 × F1 dB < F < 2 GHz
45
—
—
dB
3.2
Mechanical Specifications
Figure 16.
48-pin eTQFP Land Pattern
LAND PATTERN - 48 ETQFP
0.965 REF.
5.070 REF.
PWB Exposed Pad
3x3 Array of
Thermal Vias
0.330 mm Dia.
Spacing TBD
1.215 REF.
4.570 REF.
Mask Opening
Thermal Vias Should be
Tinted Using 0.430 mm Dia.
Solder Mask
4.570 REF.
5.070 REF.
0.250
0.965 REF.
0.500
1.000
0.250
1.215 REF.
8.400 REF.
11 EQ SP @ 0.50 = 5.50
TYP
9.400 REF.
PWB METALIZATION PATTERN
PWB SOLDER MASK PATTERN
102031_017
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
36
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
Figure 17.
48-pin eTQFP Package Diagram
D
D1
Pin #1
Ref. Mark
D
D2
D1
D2
D1
e
b
TOP VIEW
BOTTOM VIEW
Millimeters
Dimension
SIDE VIEW
See Detail A
A2
A
c
Min
A
L
L1
Max
0.047 MAX
A1
0.05
0.15
0.002
A2
0.95
1.05
0.037
0.006
0.041
D
9.00 BSC
0.354 BSC
D1
7.00 BSC
0.275 BSC
D2
4.50 REF
L
0.177 REF
0.75
0.45
0.039 REF
0.50 BSC
0.020 BSC
b
0.17
0.27
0.007
c
0.09
0.20
0.004
Coplanarity
0.08 MAX
0.030
0.018
1.00 REF
e
DETAIL A
Min
1.20 MAX
L1
A1
Inches
Max
0.011
0.008
0.003 MAX
102031_018
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
37
CX24109
NXP Semiconductors
Chapter 3: Parametric Data and Specifications
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
38
CX24109
NXP Semiconductors
Digital Satellite Tuner
Legal information
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
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Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
CX24109_N_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
39
CX24109
NXP Semiconductors
Digital Satellite Tuner
40
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 November 2008
Document identifier: CX24109_N_1