INTEGRATED CIRCUITS
DATA SHEET
SAA7356HL
1394 SBP-2 link layer controller
Preliminary specification
File under Integrated Circuits, IC01
2000 Nov 17
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
CONTENTS
8.4
8.4.1
8.4.2
RAM access for parameter passing
Register Access
Register definitions for the register access
method
1
FEATURES
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
9
LIMITING VALUES
4
ORDERING INFORMATION
10
5
BLOCK DIAGRAM
RECOMMENDED OPERATING
CONDITIONS
6
PIN CONFIGURATION
11
DC CHARACTERISTICS
7
FUNCTIONAL DESCRIPTION
12
AC CHARACTERISTICS
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.5
7.6
Overview
SBP-2 automation engine
DMA interface
Microcontroller interface
Intel 8031 interface support
Hitachi H8 interface
NEC V851 interface support
Interrupt handling
Address map for the SAA7356HL
13
APPLICATION INFORMATION
14
PACKAGE OUTLINE
15
SOLDERING
15.1
8
MICROCONTROLLER COMMUNICATION
WITH THE SAA7356HL
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
8.1
Communications initiated by the
microcontroller
Communications initiated by the SAA7356HL
Interrupt registers
8.2
8.3
2000 Nov 17
15.2
15.3
15.4
15.5
2
16
DATA SHEET STATUS
17
DEFINITIONS
18
DISCLAIMERS
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
1
SAA7356HL
FEATURES
2
• Institute of Electrical and Electronics Engineers
(IEEE) 1394-1995 standard link layer controller
GENERAL DESCRIPTION
The SAA7356HL is an IEEE1394-1995 and P1394a
compliant link layer controller featuring an embedded
SBP-2 transaction layer for data storage applications. The
SAA7356HL provides full automation of the SBP-2
transaction layer to an extent that the user need not have
knowledge of SBP-2 or 1394.
• Compatible with the P1394a standard
• Fully automated Serial Bus Protocol 2 (SBP-2)
transaction layer for data storage applications
• Interface to many of the industry standard Direct
Memory Access (DMA) protocols
• Interface to any IEEE1394-1995 or P1394a PHY layer
interface
• Very low power comma mode
• Small package
• Single 3.3 V supply voltage with 5 V tolerance.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
supply voltage
IDD
supply current
SCLK
system clock
4
CONDITIONS
VDD = 3.3 V
MIN.
TYP.
MAX.
UNIT
3.0
3.3
3.6
V
−
29
−
mA
49.147
49.152
49.157
MHz
ORDERING INFORMATION
TYPE
NUMBER
SAA7356HL
2000 Nov 17
PACKAGE
NAME
LQFP80
DESCRIPTION
plastic low profile quad flat package; 80 leads;
body 12 × 12 × 1.4 mm
3
VERSION
SOT315-1
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
5
SAA7356HL
BLOCK DIAGRAM
handbook, full pagewidth
SRAM
32-bit
data bus
ARBITER
SRAM
CONTROLLER
1394 PHY interface
Req/Ack
flow control
ARBITER
MICROCONTROLLER
INTERFACE
LINK
CORE
DMA
CONTROL
SAA7356HL
SBP-2 AUTOMATION ENGINE
GSA038
microcontroller interface
Fig.1 Block diagram.
2000 Nov 17
4
DMA interface
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
6
SAA7356HL
PIN CONFIGURATION
TYPE(1)
DESCRIPTION
SYMBOL
PIN
MICRO_ADDR[0]
1
I
microcontroller address input (bit 0); note 2
MICRO_ADDR[1]
2
I
microcontroller address input (bit 1); note 2
MICRO_ADDR[2]
3
I
microcontroller address input (bit 2); note 2
MICRO_ADDR[3]
4
I
microcontroller address input (bit 3); note 2
VDD1(P)
5
S
supply voltage 1 for periphery
VSS1(P)
6
S
ground 1 for periphery
MICRO_ADDR[4]
7
I
microcontroller address input (bit 4); note 2
MICRO_ADDR[5]
8
I
microcontroller address input (bit 5); note 2
MICRO_ADDR[6]
9
I
microcontroller address input (bit 6); note 2
MICRO_ADDR[7]
10
I
microcontroller address input (bit 7); note 2
VDD2(P)
11
S
supply voltage 2 for periphery
VSS2(P)
12
S
ground 2 for periphery
DMA_DATA[15]
13
I /O
DMA data input/output (bit 15); note 3
DMA_DATA[14]
14
I /O
DMA data input/output (bit 14); note 3
DMA_DATA[13]
15
I /O
DMA data input/output (bit 13); note 3
DMA_DATA[12]
16
I /O
DMA data input/output (bit 12); note 3
DMA_DATA[11]
17
I /O
DMA data input/output (bit 11); note 3
DMA_DATA[10]
18
I /O
DMA data input/output (bit 10); note 3
VDD1(C)
19
S
supply voltage 1 for core
VSS1(C)
20
S
ground 1 for core
DMA_DATA[9]
21
I /O
DMA data input/output (bit 9); note 3
DMA_DATA[8]
22
I /O
DMA data input/output (bit 8); note 3
DMA_DATA[7]
23
I /O
DMA data input/output (bit 7); note 3
DMA_DATA[6]
24
I /O
DMA data input/output (bit 6); note 3
DMA_DATA[5]
25
I /O
DMA data input/output (bit 5); note 3
DMA_DATA[4]
26
I /O
DMA data input/output (bit 4); note 3
DMA_DATA[3]
27
I /O
DMA data input/output (bit 3); note 3
DMA_DATA[2]
28
I /O
DMA data input/output (bit 2); note 3
VSS3(P)
29
S
ground 3 for periphery
VDD3(P)
30
S
supply voltage 3 for periphery
DMA_DATA[1]
31
I /O
DMA data input/output (bit 1); note 3
DMA_DATA[0]
32
I /O
DMA data input/output (bit 0); note 3
DMA_REQ
33
O
DMA request signal output in slave mode (acknowledge in master/ATA mode)
(may be configured for active HIGH or active LOW)
DMA_ACK
34
I
DMA acknowledge signal input in slave mode (request in master/ATA mode)
(may be configured for active HIGH or active LOW)
VSS2(C)
35
S
ground 2 for core
VDD2(C)
36
S
supply voltage 2 for core
DMA_READ
37
I /O
DMA read strobe input/output (may be configured for active HIGH or active
LOW)
2000 Nov 17
5
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
SYMBOL
PIN
TYPE(1)
DMA_WRITE
38
I /O
DMA write strobe input/output (may be configured for active HIGH or active
LOW)
PHY_CTRL[1]
39
I /O
PHY control line input/output (1); note 4
PHY_CTRL[0]
40
I /O
PHY control line input/output (0); note 4
PHY_DATA[0]
41
I /O
PHY data input/output (bit 0); notes 4, 5 and 6
PHY_DATA[1]
42
I /O
PHY data input/output (bit 1); notes 4 and 5
PHY_DATA[2]
43
I /O
PHY data input/output (bit 2); notes 4 and 5
PHY_DATA[3]
44
I /O
PHY data input/output (bit 3); notes 4 and 5
VSS4(P)
45
S
ground 4 for periphery
DESCRIPTION
VDD4(P)
46
S
supply voltage 4 for periphery
PHY_DATA[4]
47
I /O
PHY data input/output (bit 4); notes 4 and 5
PHY_DATA[5]
48
I /O
PHY data input/output (bit 5); notes 4 and 5
PHY_DATA[6]
49
I /O
PHY data input/output (bit 6); notes 4 and 5
PHY_DATA[7]
50
I /O
PHY data input/output (bit 7); notes 4 and 5
VDD5(P)
51
S
supply voltage 5 for periphery
VSS5(P)
52
S
ground 5 for periphery
PHY_SCLK
53
I
PHY system clock input (49.152 MHz)
MICRO_SEL[0]
54
I
microcontroller select (0) input; selects microcontroller interface; note 10
PHY_LREQ
55
O
PHY-Link request output (used to request arbitration or read/write PHY
registers); note 4
PHY_ISO
56
I
PHY isolation barrier input (active LOW). Negated HIGH when the Link and
PHY are directly connected or when bus-holder isolation is used; note 4
MICRO_SEL[1]
57
I
microcontroller select (1) input; selects microcontroller interface; note 10
1394_MODE
58
I /O
note 7
RESET
59
I
asynchronous master reset input to the SAA7356HL (active LOW)
TC
60
−
reserved for factory testing; for normal operation should be connected to
ground
BT
61
−
reserved for factory testing; for normal operation should be connected to
ground
MICRO_CS
62
I
microcontroller chip select input (active LOW)
VDD3(C)
63
S
supply voltage 3 for core
VSS3(C)
64
S
ground 3 for core
MICRO_INT
65
O
microcontroller interrupt open-drain output (active LOW)
MICRO_WRITE
66
I
microcontroller write strobe input (active LOW)
MICRO_READ
67
I
microcontroller read strobe input (active LOW)
MICRO_ALE
68
I
microcontroller address latch enable input; note 8
VSS6(P)
69
S
ground 6 for periphery
VDD6(P)
70
S
supply voltage 6 for periphery
MICRO_DATA[0]
71
I /O
microcontroller data input/output [bit 0); note 9
MICRO_DATA[1]
72
I /O
microcontroller data input/output (bit 1); note 9
MICRO_DATA[2]
73
I /O
microcontroller data input/output (bit 2); note 9
MICRO_DATA[3]
74
I /O
microcontroller data input/output (bit 3); note 9
2000 Nov 17
6
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SYMBOL
MICRO_DATA[4]
PIN
TYPE(1)
75
I /O
SAA7356HL
DESCRIPTION
microcontroller data input/output (bit 4); note 9
MICRO_DATA[5]
76
I /O
microcontroller data input/output (bit 5); note 9
VSS4(C)
77
S
ground 4 for core
VDD4(C)
78
S
supply voltage 4 for core
MICRO_DATA[6]
79
I /O
microcontroller data input/output (bit 6); note 9
MICRO_DATA[7]
80
I /O
microcontroller data input/output (bit 7); note 9
Notes
1. Pin type abbreviations: I = Input, O = Output and S = Supply.
2. Used in NEC V851 and 16-bit Intel 8031 microcontroller interface configurations.
3. DMA data to the external buffer manager may be configured for 16 or 8 bits wide. For 16-bit operation pins
DMA_DATA[15:0] are used, and for 8-bit operation, pins DMA_DATA[7:0] are used.
4. For more information see IEEE1394-1995 standard, Annex J.
5. Data is expected on PHY_DATA[0:1] for 100 Mbits/s, PHY_DATA[0:3] for 200 Mbits/s and PHY_DATA[0:7] for
400 Mbits/s.
6. To preserve compatibility to the specified Link-PHY interface of the IEEE1394-1995 standard, Annex J, bit 0 is the
most significant bit.
7. During Power-on reset, this line is sampled to select between IEEE1394-1995 mode (HIGH) and P1394a mode
(LOW). A 22 kΩ pull-up or pull-down resistor should be connected accordingly. This line acts as the MICRO_WAIT
line when the V851 microcontroller interface mode is selected.
8. Used in NEC V851 and Intel 8031 (8-bit and 16-bit) microcontroller interface configurations.
9. This is the data bus for all microcontroller interface configurations. This forms the lower address bus for the
NEC V851 and Intel 8031 microcontroller configurations.
10. MICRO_SEL [1:0] = ‘00’ selects 8-bit 8031 mode; MICRO_SEL [1:0] = ‘01’ selects H8 mode;
MICRO_SEL [1:0] = ‘10’ selects 16-bit 8031 mode; MICRO_SEL [1:0] = ‘11’ V851 mode.
2000 Nov 17
7
Philips Semiconductors
Preliminary specification
61 BT
62 MICRO_CS
63 VDD3(C)
64 VSS3(C)
65 MICRO_INT
66 MICRO_WRITE
67 MICRO_READ
68 MICRO_ALE
69 VSS6(P)
70 VDD6(P)
71 MICRO_DATA[0]
72 MICRO_DATA[1]
SAA7356HL
73 MICRO_DATA[2]
74 MICRO_DATA[3]
75 MICRO_DATA[4]
76 MICRO_DATA[5]
77 VSS4(C)
78 VDD4(C)
80 MICRO_DATA[7]
handbook, full pagewidth
79 MICRO_DATA[6]
1394 SBP-2 link layer controller
MICRO_ADDR[0]
1
60 TC
MICRO_ADDR[1]
2
59 RESET
MICRO_ADDR[2]
3
58 1394_MODE
MICRO_ADDR[3]
4
57 MICRO_SEL[1]
VDD1(P)
5
56 PHY_ISO
VSS1(P)
6
55 PHY_LREQ
MICRO_ADDR[4]
7
54 MICRO_SEL[0]
MICRO_ADDR[5]
8
53 PHY_SCLK
MICRO_ADDR[6]
9
52 VSS5(P)
MICRO_ADDR[7] 10
51 VDD5(P)
SAA7356HL
Fig.2 Pin configuration.
2000 Nov 17
8
PHY_CTRL[0] 40
PHY_CTRL[1] 39
DMA_WRITE 38
41 PHY_DATA[0]
DMA_READ 37
VSS1(C) 20
VDD2(C) 36
42 PHY_DATA[1]
VSS2(C) 35
VDD1(C) 19
DMA_ACK 34
43 PHY_DATA[2]
DMA_REQ 33
44 PHY_DATA[3]
DMA_DATA[10] 18
DMA_DATA[0] 32
DMA_DATA[11] 17
DMA_DATA[1] 31
45 VSS4(P)
VDD3(P) 30
DMA_DATA[12] 16
VSS3(P) 29
46 VDD4(P)
DMA_DATA[2] 28
DMA_DATA[13] 15
DMA_DATA[3] 27
47 PHY_DATA[4]
DMA_DATA[4] 26
DMA_DATA[14] 14
DMA_DATA[5] 25
48 PHY_DATA[5]
DMA_DATA[6] 24
49 PHY_DATA[6]
DMA_DATA[15] 13
DMA_DATA[7] 23
VSS2(P) 12
DMA_DATA[8] 22
50 PHY_DATA[7]
DMA_DATA[9] 21
VDD2(P) 11
GSA017
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
7
7.1
SAA7356HL
FUNCTIONAL DESCRIPTION
The SBP-2 link also provides an interface to an external
microcontroller. The microcontrollers supported include
8/16-bit addressing from the Intel 8031 derivatives, the
Hitachi H8 and the NEC V851. Through this interface, the
microcontroller retrieves the 12-byte Command Descriptor
Blocks (CDBs) and provides the command status
indication; unsolicited status information is also supported.
Overview
The SAA7356HL is an IEEE1394-1995 and P1394a
compliant link layer controller. It provides a direct interface
between a 1394 bus and a DMA interface found on many
buffer managers (see Fig.3). Through this interface, the
SBP-2 automation engine performs all transaction layer
specific operations; these include the management agent,
fetch agent, and page table handling features.
handbook, full pagewidth
MICRO_ADDR [7:0]
MICRO_DATA [7:0]
microcontroller
interface
MICRO_SEL [1:0]
PHY_DATA [0:7]
MICRO_ALE
PHY_CTRL [0:1]
MICRO_READ
PHY_LREQ
MICRO_WRITE
MICRO_CS
1349-MODE (1)
MICRO_INT
1394 PHY
interface
PHY_ISO
PHY_SCLK
SAA7356HL
IEEE1394/P1394a
SBP-2 LINK LAYER CONTROLLER
VDD
DMA_DATA [15:0]
VSS
DMA_REQ
DMA
interface
RESET
DMA_ACK
DMA_READ
DMA_WRITE
GSA039
(1) Acts as the MICRO_WAIT line when the V851 microcontroller interface mode is selected.
Fig.3 Functional diagram.
7.2
SBP-2 automation engine
The microcontroller will return the requested information.
The SAA7356HL will then add the required header for the
1394 transaction to service these requests.
The complete SBP-2 transaction layer is supported by the
SAA7356HL. This includes the log-in, log-out and
reconnect functions in the management agent plus the
fetch engine for retrieving linked lists of Operation Request
Blocks (ORBs) from the logged-in node. The data
transfers plus the required flow control and target node
page-table management are also supported. The
transaction layer parses the ORBs to extract the CDBs and
presents them to the microcontroller. The microcontroller
returns status indication to the transaction layer: the
SBP-2 engine then returns this information plus the
transaction status information to the logged-in node.
7.3
The SAA7356HL supports many formats of DMA interface.
The DMA bus width may be 8 or 16 bits wide. The polarity
of the request, acknowledge, read and write strobes can
be configured for active HIGH or active LOW. The DMA
controller may also be configured as a master or a slave.
In the slave mode, the burst length can also be configured.
All configuration details are loaded into the SAA7356HL
via a shared page in the Static Random Access Memory
(SRAM).
The SAA7356HL will present all Configuration-ROM reads
to the microcontroller.
2000 Nov 17
DMA interface
9
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
In slave mode a buffer data transfer begins when the
DMA interface asserts the DMA_REQ pin. The buffer
manager responds with the DMA_ACK signal. The burst
configuration defines the number of bytes/words to keep
DMA_REQ asserted. The settings include:
In master mode the SAA7356HL appears to be an
Advanced Technology Attachment (ATA) host and can be
connected to an ATA or Advanced Technology
Attachment Packet Interface (ATAPI) peripheral. The
SAA7356HL output signal (DMA_REQ) behaves like the
acknowledge on the Integrated Drive Electronics (IDE)
bus; the input signal (DMA_ACK) behaves like the request
line on the IDE bus.
• DMA_REQ is asserted until the last byte/word is
transferred or until there is no space/data available in
the FIFO
• DMA_REQ is asserted and negated for each byte/word
transferred
The configuration information is provided via a
communication page which is shared between the
microcontroller and the SAA7356HL. The connections for
the various modes are shown in Figs 4 and 5.
• DMA_REQ is not asserted unless there is space/data
available in the FIFO
• the DMA interface waits until there are at least two
bytes/words of data/space in the FIFO before asserting
DMA_REQ (in this case, DMA_REQ remains asserted
for the two bus transfers and then de-asserts); and
7.4
Because of the high-level protocol support, only ten
addresses are required. The user should note that all of
the internal SAA7356HL registers are still accessible and
so the chip-select line should be used to ensure that the
SAA7356HL is not accessed accidentally. The behaviour
on accessing these other addresses is not specified.
• the DMA interface waits until there are at least four
bytes/words of data/space in the FIFO before asserting
DMA_REQ (in this case, DMA_REQ remains asserted
for the four bus transfers and then de-asserts).
When used in V851 and H8 modes, the MICRO_WAIT line
is asserted within 4 ns of the MICRO_READ falling edge.
This process repeats until all of the data is transferred. In
slave mode, there are three modes of operation for moving
data between the SAA7356HL and the DMA interface:
For all modes of operation, the data bus is the
MICRO_DATA bus. The microcontroller interface can be
configured for four modes of operation, namely:
• Mode 0: DMA_WRITE strobes the data from the buffer
memory data bus into the FIFO; DMA_READ gates the
data from the FIFO onto the buffer memory data bus
• Mode 0: 8-bit addressed Intel 8031 peripheral
(multiplexed address/data bus)
• Mode 1: DMA_WRITE strobes the data from the buffer
memory into the FIFO. DMA_ACK gates data from the
FIFO onto the buffer memory data bus
• Mode 1: 8-bit addressed Hitachi H8 peripheral
(non-multiplexed address and data buses)
• Mode 2: 16-bit addressed Intel 8031 peripheral (lower
address from multiplexed address/data bus)
• Mode 2: DMA_ACK strobes the data from the buffer
memory bus into the FIFO and also gates the data from
the FIFO onto the buffer memory data bus.
• Mode 3: 16-bit addressed NEC V851 peripheral (acting
as an 8-bit peripheral).
In slave mode the DMA interface drives the DMA_REQ pin
and waits for the buffer manager to acknowledge the
request via DMA_ACK as described above. In master
mode, the buffer manager drives the DMA_REQ pin and
the DMA interface acknowledges the availability of
data/space with the DMA_ACK pin.
7.4.1
INTEL 8031 INTERFACE SUPPORT
The microcontroller interface logic supports the industry
standard 8031 style interface.
On reading, the MICRO_DATA output is enabled as soon
as the MICRO_READ is asserted. Before this happens,
the address will have already been decoded and the
internal Data Out signal asserted. On writing, the data is
loaded from the rising edge of MICRO_WRITE.
The read or write strobes are driven by the buffer manager
in slave mode, and by the DMA interface in master mode.
All mode selections listed above are also valid in master
mode, however it should be noted that the burst
configuration is not applicable in master mode.
Burst size in master mode is determined by the buffer
manager request signal, and DMA interface flow control by
the time duration between successive acknowledge
assertions or read/write assertions.
2000 Nov 17
Microcontroller interface
10
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
handbook, full pagewidth
SAA7356HL
DMA_REQ
DMA_REQ
DMA_REQ
DMA_ACK
DMA_ACK
DMA_ACK
DMA_WRITE
DMA_WRITE
(data direction –>)
(data direction –>)
DMA_READ
(data direction <–)
buffer data 16 or 8-bit
BUFFER
MANAGER
SAA7356HL
slave mode 0
buffer data 16 or 8-bit
BUFFER
MANAGER
SAA7356HL
slave mode 1
buffer data 16 or 8-bit
BUFFER
MANAGER
SAA7356HL
slave mode 2
GSA040
Fig.4 Slave Mode 0, 1 and 2
handbook, full pagewidth
DMA_ACK DMA_REQ
DMA_ACK DMA_REQ
DMA_ACK DMA_REQ
DMA_REQ DMA_ACK
DMA_REQ DMA_ACK
DMA_REQ DMA_ACK
DMA_WRITE
DMA_WRITE
(data direction –>)
(data direction –>)
DMA_READ
(data direction <–)
buffer data 16 or 8-bit
BUFFER
MANAGER
master mode 0
SAA7356HL
BUFFER
MANAGER
SAA7356HL
master mode 1
Fig.5 Master Mode 0, 1 and 2.
2000 Nov 17
buffer data 16 or 8-bit
buffer data 16 or 8-bit
11
BUFFER
MANAGER
master mode 2
SAA7356HL
GSA041
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
7.4.2
SAA7356HL
The MICRO_WAIT line must be low during the falling edge
of the (V851) CLK during state T2: this is the same
requirement as the H8. Instead of a MICRO_READ and a
MICRO_WRITE signal the V851 uses a R/W and DSTB
signal. The address lines are time multiplexed and should
be latched using the ASTB signal.
HITACHI H8 INTERFACE
In this mode, the address and data buses are
non-multiplexed. The address bus is connected directly to
the MICRO_ADDR pins and the data bus is connected
directly onto the MICRO_DATA pins.
The MICRO_CS pin must be asserted before the assertion
of the MICRO_READ pin. The SAA7356HL will stop
driving the microcontroller data bus when either the
MICRO_CS pin or the MICRO_READ pin are negated.
7.5
The SAA7356HL may use interrupts to communicate with
the microcontroller. The microcontroller will read from the
CmdToMicro register to find the interrupt reason.
If parameters are required with the command then this is
implied in the command byte.These parameters may then
be read from the SAA7356HL RAM using the RAM.Offset
and the RAM.Next registers.
The H8 microcontroller supports wait states. The timing is
shown in Fig.6. Note that the MICRO_WAIT pin must be
low during the falling edge of the (H8) CLK during state T2.
Since the relationship between the SAA7356HL and the
H8 clock is unknown the MICRO_WAIT pin is asserted low
when the MICRO_READ and the MICRO_CS are
asserted. The SAA7356HL will de-assert the
MICRO_WAIT line once the data is ready for transfer.
7.4.3
Interrupt handling
7.6
Address map for the SAA7356HL
The address mapping for the 4-bit, 8-bit and 16-bit
addressing modes is given in Table 1.
NEC V851 INTERFACE SUPPORT
The most important timing information for this
microcontroller is given in Fig.7.
Table 1
Big-endian register map for the SAA7356HL
ADDRESS
MNEMONIC
4-BIT
8-BIT
COMMENT
16-BIT
0
9C
FF90
Reserved
reserved
1
9D
FF91
InterruptEnable
enables the InterruptReason to assert the
microcontroller interrupt line
2
9E
FF92
InterruptReason provides the interrupt sources
3
9F
FF93
CmdFromMicro
command byte channel from the microcontroller to the
SAA7356HL
4
BC
FFB0
CmdToMicro
command byte from the SAA7356HL to the
microcontroller
5
BD
FFB1
Sbp2Start
used to complete the SAA7356HL initialization sequence
6
BE
FFB2
InterruptSet
7 to B
BF, DC to DF
FFB3,
Reserved
FFD0 to FFD3
reserved
C
FC
FFF0
RAM.OffsetB
High-byte of the offset address
D
FD
FFF1
RAM.OffsetA
Low-byte for the offset address
E
FE
FFF2
RAM.Next
RAM access register: forces a post-increment of the
RAM.Offset address
F
FF
FFF3
RAM.Current
RAM access register: no modification to the RAM.Offset
address
2000 Nov 17
allows setting of the flags in the InterruptReason register
12
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
T1
handbook, full pagewidth
SAA7356HL
T2
Tw
T3
CLK
MICRO_ADDR
AS
MICRO_READ
MICRO_DATA(read)
MICRO_WRITE
MICRO_DATA(write)
MICRO_WAIT
GSA042
Fig.6 H8 microcontroller interface timing.
T1
handbook, full pagewidth
T2
Tw
T3
CLK
MICRO_ADDR
MICRO_ALE(ASTB)
MICRO_READ(DSTB)
MICRO_DATA(read)
ADDRESS
DATA
MICRO_READ(R/W)
MICRO_DATA(write)
ADDRESS
DATA
MICRO_WAIT
GSA043
Fig.7 V851 microcontroller interface timing.
2000 Nov 17
13
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
8
SAA7356HL
MICROCONTROLLER COMMUNICATION WITH
THE SAA7356HL
This style of communication is used to realize a simple
command-driven communication protocol in which the
microcontroller sends command bytes to the SAA7356HL.
If no parameters are required, there is no need to write to
a shared memory location and hence there is no need to
write to the RAM Access Offset, Current and Next
registers. The CmdFromMicro register definition is given
in Table 2.
The communications protocol from a hardware
perspective is described in the following sections.
The automation engine within the SAA7356HL performs
all of the functions necessary to support the SBP-2
protocol layer. The microcontroller and the SAA7356HL
communicate via command registers and access to the
shared RAM resource.
In addition to the CmdFromMicro register, the
microcontroller can also write to the Sbp2Start register.
This is used in the system initialization sequence. The
value that is written has no significance and reading from
this address will return zeros.
The microcontroller will download the configuration
information into the SAA7356HL after a Power-on reset.
Once this has been done, the power-on sequence will be
completed when the microcontroller writes any value to the
Sbp2Start register. To download the configuration
information, the microcontroller simply copies a binary
image (provided by Philips Semiconductors) and writes
repetitively into the RAM.Next address.
8.1
When using this command to initialize the SAA7356HL,
the microcontroller may first write to a pre-designated
memory area for the parameter passing and then write to
the Sbp2Start register to start the requested action. The
Sbp2Start register definition is given in Table 3.
Communications initiated by the
microcontroller
8.2
The SAA7356HL has only one form of communication to
the microcontroller: the SAA7356HL will write to the
CmdToMicro register. On writing to this register, the
maskable CmdMicro bit in the InterruptReason register
is asserted, which in turn may assert the maskable
interrupt to the microcontroller. The microcontroller will
read from the InterruptReason register to determine the
cause of the interrupt. If no data is required from the
communication then the microcontroller can determine this
from the value in the CmdToMicro register. The
CmdToMicro register definition is given in Table 4.
The microcontroller may send a message to the
SAA7356HL by writing to the CmdFromMicro register.
Once the SAA7356HL has used this register, the
SAA7356HL will assert the maskable interrupt,
InterruptReason.CmdClr, to the microcontroller. The
value in the CmdFromMicro register will remain.
On receiving the InterruptReason.CmdClr interrupt, the
microcontroller will read from the InterruptReason
register to determine the source of this interrupt. To clear
the interrupt, the microcontroller must write a logic 1 to the
InterruptReason.CmdClr bit: writing a logic 0 to this
location has no effect. An alternative control protocol may
be used. As the SAA7356HL acknowledges the
CmdFromMicro, the InterruptReason.CmdClr is
asserted as before. The user may decide to mask this
interrupt and use a polling technique.
If data or parameters are needed then the SAA7356HL will
first write to the RAM and then write to the CmdToMicro
register. To signal acknowledgment of the interrupt, the
microcontroller writes a logic 1 to the CmdMicro bit in the
InterruptReason register which also has the effect of
clearing the CmdMicro bit and negating the interrupt (if no
other interrupts are pending): writing a logic 0 to the
CmdMicro bit has no effect. On signalling the
acknowledgment, the value in the CmdToMicro register is
unchanged, but now the SAA7356HL is free to modify the
CmdToMicro register contents.
On detecting completion of the previous command via
InterruptReason.CmdClr, the microcontroller may write
another command into the CmdFromMicro register: this
will clear the InterruptReason.CmdClr flag and so there
is no need for the microcontroller to perform another
operation to explicitly clear this flag.
2000 Nov 17
Communications initiated by the SAA7356HL
14
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
Table 2
CmdFromMicro register definition (read/write)
BYTE
NUMBER
0
Table 3
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Sbp2Start register definition (read/write)
0
BIT 7
BIT 6
BIT 5
Command(7:0)
CmdToMicro register definition (read/write)
BYTE
NUMBER
0
8.3
BIT 7
Command(7:0)
BYTE
NUMBER
Table 4
SAA7356HL
BIT 7
BIT 6
BIT 5
Command(7:0)
Interrupt registers
In addition to these two registers, the microcontroller may
set the values in the InterruptReason register: this may
be used for setting initial conditions, for example. To set
the required bits, a logic 1 must be written to the flag
location in the InterruptSet register: writing a logic 0 to
any bit-field has no effect. The InterruptSet register
definition is given in Table 7.
As mentioned in the previous section, the communications
may be interrupt driven. To facilitate this there is one
InterruptReason and one InterruptEnable register. The
interrupt to the microcontroller is of the AND-OR type and
is asserted when any of the maskable interrupts are
enabled and active: to enable an interrupt, the
corresponding field in the InterruptEnable register must
be set to logic 1. Reading from the InterruptReason
register provides the un-masked value: this allows polling
if desired.
It is recommended that only the InterruptReason.CmdClr
flag is set as InterruptReason.CmdMicro will cause a
maskable interrupt to be asserted to the microcontroller.
The definition of the InterruptReason, InterruptEnable
and the InterruptSet register fields are shown in Table 8.
The InterruptEnable and InterruptReason register
definitions are shown in Tables 5 and 6 respectively.
Table 5
InterruptEnable register definition (read/write)
BYTE
NUMBER
0
Table 6
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
BIT 2
CmdMicro
BIT 1
BusReset
BIT 0
CmdClr
InterruptReason register definition (read/write)
BYTE
NUMBER
0
Table 7
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
BIT 2
CmdMicro
BIT 1
BusReset
BIT 0
CmdClr
InterruptSet register definition (write only, read via InteruptReason)
BYTE
NUMBER
0
2000 Nov 17
BIT 7
BIT 6
BIT 5
BIT 4
Reserved
BIT 3
BIT 2
CmdMicro
15
BIT 1
Reserved
BIT 0
CmdClr
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
Table 8
SAA7356HL
Definition of the InterruptReason, InterruptEnable and InterruptSet register fields
MNEMONIC
CmdClr
VALUE
COMMENT
0
default condition: no action occurred
1
the SAA7356HL device has acknowledged the write to the CmdFromMicro register
0
default condition: no action occurred
1
the SAA7356HL has detected a serial bus reset
CmdMicro
0
default condition: no action occurred
1
the SAA7356HL has written a command into the CmdToMicro register
Reserved
X
reserved and set to zero
BusReset
8.4
RAM access for parameter passing
Accesses to the RAM.Current address allow reads and
writes to the data in the RAM.Offset location without
altering the RAM.Offset address.
Within the SAA7356HL there is a 16 kbyte RAM. This is
shared between: the IEEE1394 transaction FIFOs,
the code for the automation engine and its local storage
requirements, and the shared memory area for
communications with the microcontroller.
The ability to write to anywhere within the RAM is used for
the power-on sequence.
8.4.2
The SAA7356HL user must understand how this shared
memory is accessed in order to write and read the
communications parameters. Each of the read and write
accesses to the FIFOs are byte-wide and the offset
addresses are byte offsets.
8.4.1
This section defines the register structure for the RAM
registers.
The RAM.Offset registers are used to index into the RAM
inside the SAA7356HL. The index is a byte address. The
RAM.Offset register definition is shown in Table 9.
REGISTER ACCESS
The RAM can be directly accessed to upload the code into
the SAA7356HL. The C-structure for the registers for the
RAM access is shown below.
The RAM.Next register is used to read or write to the RAM
location addressed by the RAM.Offset register. Once an
access has been made, the value of the RAM.Offset
register is incremented to simplify the process of reading
or writing contiguous memory areas. The RAM.Next
register definition is shown in Table 10.
struct RAM {
U16; offset; // absolute offset into the RAM
U8; next; // read/write data at offset and
post-increment
U8; current; // read/write data at offset
};
The RAM.Current register is used to read or write to the
RAM location addressed by the RAM.Offset register.
Once an access has been made there is no change to the
RAM.Offset register. The RAM.Current register definition
is shown in Table 11.
The RAM.Offset field allows the microcontroller to access
anywhere within the SAA7356HL RAM. The RAM.Next
accesses will access the RAM.Offset address and
post-increment the offset pointer.
2000 Nov 17
REGISTER DEFINITIONS FOR THE REGISTER ACCESS
METHOD
16
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
Table 9
SAA7356HL
Definition of the RAM.Offset registers (read/write)
BYTE
NUMBER
BIT 7
BIT6
0
RAM.Offset(7:0)
1
Reserved
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 3
BIT 2
BIT 1
BIT 0
BIT 3
BIT 2
BIT 1
BIT 0
RAM.Offset (13:8)
Table 10 Definition of the RAM.Next register (read/write)
BYTE
NUMBER
0
BIT 7
BIT 6
BIT 5
BIT 4
RAM.Next(7:0)
Table 11 Definition of the RAM.Current register (read/write)
BYTE
NUMBER
0
2000 Nov 17
BIT 7
BIT 6
BIT 5
BIT 4
RAM.Current(7:0)
17
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to ground
(ground = 0 V); notes 1 and 2.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+4.0
V
IIK
input clamping diode current
−
−50
mA
VI
input voltage
microcontroller and DMA
pins
−0.5
+5.5
V
PHY pins
−
VDD + 0.5 V
IOK
output clamping diode current
−
±50
mA
VO
output voltage
−0.5
VDD + 0.5 V
IO(source)
output source current
−
±150
mA
IO(sink)
output sink current
−
±150
mA
ISS − ICC
VCC or GND current
−
±150
mA
Tstg
storage temperature
−60
+150
°C
Tamb
ambient temperature
0
70
°C
Ptot
total power dissipation
package
−
380
mW
comma mode
−
82
µW
Notes
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated in “Recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The performance capability of a high performance integrated circuit in conjunction with its thermal environment can
create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated
circuit should not exceed 150 oC.
10 RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD
supply voltage
VI
input voltage
VIH
HIGH-level input voltage
VIL
CONDITIONS
MIN.
MAX.
UNIT
3.0
3.6
V
microcontroller and DMA
pins
0
5.5
V
PHY pins
0
3.6
V
2.0
−
V
LOW-level input voltage
−
0.8
V
IOH
HIGH-level output current
−
4
mA
IOL
LOW-level output current
−
−4
mA
∆tt(i)(r)/∆V
input transition rise time
0
20
ns/V
∆tt(i)f)/∆V
input transition fall time
0
20
ns/V
Tamb
ambient temperature
0
70
°C
SCLK
system clock
49.147
49.157
MHz
ti(r)
input rise time
−
10
ns
ti(f)
input fall time
−
10
ns
2000 Nov 17
18
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
11 DC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIH
HIGH-level input voltage
note 1
2.4
−
−
V
VIL
LOW-level input voltage
note 1
−
−
0.8
V
VI(th)(r)
input voltage threshold, rising note 2
edge
0.5VDD + 0.12 −
0.5VDD + 0.66 V
VI(th)(f)
input voltage threshold, falling note 2
edge
0.5VDD − 0.66 −
0.5VDD − 0.12 V
VOH1
HIGH-level output voltage 1
note 1
2.4
−
−
V
VOL1
LOW-level output voltage 1
note 1
-
−
0.4
V
VOH2
HIGH-level output voltage 2
note 3
2.9
−
−
V
VOL2
LOW-level output voltage 2
note 3
−
−
0.4
V
IIL
input leakage current
note 1
−
−
±1
µA
note 4
−
−
100
µA
IOZ
3-state output current
note 5
−
−
±5
µA
note 3
−
−
200
µA
VDD = 3.3 V;
note 6
−
−
−
mA
IDD
active supply current
Notes
1. Microcontroller and DMA interface pins.
2. PHY-Link data and control and PHY_SCLK pins.
3. PHY-Link data and control pins.
4. PHY_SCLK pin.
5. Microcontroller, DMA and PHY_LREQ pins.
6. Under idle conditions the average value is 108 mA.
2000 Nov 17
19
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
12 AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 0; see Fig.8
t0
cycle time
67
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
25
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
−
−
25
ns
t3
DMA_REQ de-assert from DMA_READ assert
(multi-word DMA)
−
−
25
ns
t4
DMA_REQ assert after DMA_ACK de-assert
8
−
−
ns
t5
write data set-up
15
−
−
ns
t6
write data hold
5
−
−
ns
t7
DMA_WRITE active pulse duration
25
−
−
ns
t8
read data stable after DMA_READ active
−
−
10
ns
t9
read data 3-state after DMA_READ inactive
5
−
10
ns
t10
DMA_REQ assert after DMA_READ and
DMA_WRITE negated
68
−
−
ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 1; see Fig.9
t0
cycle time
67
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
25
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
−
−
25
ns
t3
DMA_REQ assert after DMA_ACK de-assert
5
−
−
ns
t4
read data stable after DMA_ACK assert
−
−
10
ns
t5
read data 3-state after DMA_ACK inactive
5
−
10
ns
t6
write data set-up
15
−
−
ns
t7
write data hold
5
−
−
ns
t8
DMA_WRITE active pulse width
25
−
−
ns
DMA INTERFACE WRITE/READ TIMING FOR SLAVE MODE 2; see Fig.10
t0
cycle time
67
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
25
ns
t2
DMA_REQ assert after DMA_ACK de-assert
5
−
−
ns
t3
write data set-up
15
−
−
ns
t4
write data hold
5
−
−
ns
t5
DMA_ACK active pulse duration during data write
25
−
−
ns
t6
read data stable after DMA_ACK assert
−
−
10
ns
t7
read data 3-state after DMA_ACK de-assert
5
−
10
ns
2000 Nov 17
20
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SYMBOL
SAA7356HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 0; note 1; see Fig.11
t0
cycle time
40
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
30
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
−
−
30
ns
t3
DMA_REQ de-assert from DMA_READ assert
(multi-word DMA)
−
−
30
ns
t4
DMA_REQ assert after DMA_ACK de-assert
0
−
−
ns
t5
write data set-up
20
−
−
ns
t6
write data hold
0
−
−
ns
t7
DMA_WRITE active pulse duration
20
−
−
ns
t8
read data stable after DMA_READ active
−
−
15
ns
t9
read data 3-state after DMA_READ inactive
25
−
30
ns
t10
DMA_WRITE active pulse duration
20
−
−
ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 1; note 1; see Fig.12
t0
cycle time
40
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
30
ns
t2
DMA_REQ de-assert from DMA_WRITE assert
(multi-word DMA)
−
−
30
ns
t3
DMA_REQ assert after DMA_ACK de-assert
0
−
−
ns
t4
read data stable after DMA_ACK assert
−
−
15
ns
t5
read data 3-state after DMA_ACK inactive
25
−
30
ns
t6
write data set-up
20
−
−
ns
t7
write data hold
0
−
−
ns
t8
DMA_WRITE active pulse width
20
−
−
ns
t9
DMA_ACK active pulse width
20
−
−
ns
DMA INTERFACE WRITE/READ TIMING FOR MASTER MODE 2; note 1; see Fig.13
t0
cycle time
40
−
−
ns
t1
DMA_REQ de-assert from DMA_ACK assert
(single word DMA)
−
−
30
ns
t2
DMA_REQ assert after DMA_ACK de-assert
0
−
−
ns
t3
write data set-up
20
−
−
ns
t4
write data hold
0
−
−
ns
t5
DMA_ACK active pulse duration during data write
20
−
−
ns
t6
read data stable after DMA_ACK assert
−
−
15
ns
t7
read data 3-state after DMA_ACK de-assert
25
−
30
ns
2000 Nov 17
21
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SYMBOL
SAA7356HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PHY-LINK INTERFACE TIMING; see Figs 14 and 15
t1
PHY-Link set-up time
6
−
−
ns
t2
PHY-Link hold time
0
−
−
ns
t3
PHY-Link output delay
2
−
10
ns
10
−
−
ns
REGISTER INTERFACE TIMING; see Figs 16, 17, 18, 19, 20, 21 and 22
t1
address set-up to MICRO_ALE LOW
t2
address hold from MICRO_ALE LOW
t3
MICRO_ALE pulse width
t4
MICRO_ALE LOW to MICRO_CS LOW
note 2
note 3
10
−
−
ns
20
−
−
ns
10
−
−
ns
−
−
280
ns
0
−
−
ns
0
−
−
ns
t5
MICRO_CS LOW to data valid
t6
MICRO_CS HIGH to MICRO_ALE HIGH
t7
MICRO_CS set-up to MICRO_READ LOW
t8
MICRO_READ pulse width
note 5
280
−
−
ns
t9
MICRO_READ HIGH to MICRO_CS HIGH
note 4
0
−
−
ns
t10
MICRO_READ LOW to data valid
note 6
−
−
280
ns
t11
MICRO_READ HIGH to data bus disable
t12
MICRO_CS set-up to MICRO_WRITE LOW
t13
MICRO_WRITE pulse width
note 4
note 7
2
−
30
ns
0
−
−
ns
30
−
−
ns
t14
MICRO_WRITE HIGH to MICRO_CS HIGH
0
−
−
ns
t15
data set-up to MICRO_WRITE HIGH
15
−
−
ns
t16
data hold from MICRO_WRITE HIGH
4
−
−
ns
t17
MICRO_WRITE HIGH to MICRO_ALE HIGH
note 8
tCP + 5 −
−
ns
t18
MICRO_WRITE HIGH to MICRO_WRITE HIGH
note 9
280
−
−
ns
note 10
460
−
−
ns
note 7
t19
MICRO_READ LOW to MICRO_WAIT LOW
−
−
4
ns
t20
data valid to MICRO_WAIT HIGH
−
−
20
ns
Notes
1. ATA Multi-word Direct Memory Access (MDMA) protocol with all timing based on an internal DMA interface 50 MHz
system clock.
2. MICRO_ALE must pulse to capture a new register address for the Intel 8031 and the NEC V851 modes.
3. t10 must also be satisfied.
4. If MICRO_READ is held LOW, the time from MICRO_CS LOW to stable data is t5 and the data release time from
MICRO_CS HIGH is t11.
5. This is larger than the typical read strobe timing. To meet these requirements, either the microcontroller clock will be
stopped by the buffer manager device, or the microcontroller must insert its own wait states.
6. t5 must also be satisfied.
7. If MICRO_WRITE is held LOW, data set-up to MICRO_CS HIGH is t15 and data hold from MICRO_CS is t16.
8. t3 minimum = 2 × 3tCP + 5 for successive FIFO reads or a FIFO read or write followed by a read of the FIFO flag
registers.
9. This time relates to accesses to addresses other than RAM.Next and RAM.Current.
10. This time relates to accesses to the addresses RAM.Next and RAM.Current.
2000 Nov 17
22
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
t0
handbook, full pagewidth
DMA_REQ
t4
t1
DMA_ACK
t2
t10
t7
DMA_WRITE
t5
t6
write data
DMA_DATA [15:0]
t3
t10
DMA_READ
t8
t9
DMA_DATA [15:0]
read data
GSA044
DMA_REQ is configured active HIGH.
DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.8 DMA interface write/read timing diagram for slave mode 0.
t0
handbook, full pagewidth
DMA_REQ
t3
t1
t2
DMA_ACK
t5
t4
read data
DMA_DATA [15:0]
t8
DMA_WRITE
t6
DMA_DATA [15:0]
t7
write data
GSA045
DMA_REQ is configured active HIGH.
DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.9 DMA interface write/read timing diagram for slave mode 1.
2000 Nov 17
23
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
t0
handbook, full pagewidth
DMA_REQ
t2
t1
t5
DMA_ACK
t4
t3
write data
DMA_DATA [15:0]
t6
t7
DMA_DATA [15:0]
read data
GSA046
DMA_REQ is configured active HIGH.
DMA_ACK is configured active LOW.
Fig.10 DMA interface write/read timing diagram for slave mode 2.
t0
handbook, full pagewidth
DMA_REQ
t1
t4
t10
DMA_ACK
t2
t7
DMA_WRITE
t5
t6
write data
DMA_DATA [15:0]
t3
t10
DMA_READ
t8
t9
DMA_DATA [15:0]
read data
GSA047
DMA_REQ is configured active HIGH.
DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW.
Fig.11 DMA interface write/read timing diagram for master mode 0.
2000 Nov 17
24
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
t0
handbook, full pagewidth
DMA_REQ
t1
t3
t9
t2
DMA_ACK
t5
t4
read data
DMA_DATA [15:0]
t8
DMA_WRITE
t7
t6
DMA_DATA [15:0]
write data
GSA048
DMA_REQ is configured active HIGH.
DMA_ACK and DMA_WRITE are configured active LOW.
Fig.12 DMA interface write/read timing diagram for master mode 1.
t0
handbook, full pagewidth
DMA_REQ
t2
t1
t5
DMA_ACK
t3
t4
write data
DMA_DATA [15:0]
t6
t7
DMA_DATA [15:0]
read data
GSA049
DMA_REQ is configured active HIGH.
DMA_ACK is configured active LOW.
Fig.13 DMA interface write/read timing diagram for master mode 2.
2000 Nov 17
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
handbook, full pagewidth
SAA7356HL
PHY_SCLK
t1
t2
PHY_DATA [7:0]
PHY_CTRL [1:0]
GSA050
Fig.14 Data and control input set-up and hold timing waveforms.
handbook, full pagewidth
PHY_SCLK
PHY_DATA [7:0]
PHY_CTRL [1:0]
PHY_LREQ
t3
GSA051
Fig.15 Data, control and PHY_LREQ output delay timing waveforms.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
handbook, full pagewidth
MICRO_ADDR [7:0]
SAA7356HL
UPPER ADDRESS
(16-bit mode only)
UPPER ADDRESS
t3
MICRO_ALE
t6
t4
MICRO_CS
t7
t8
t9
MICRO_READ
t1
MICRO_DATA [7:0]
t10
t2
t11
t5
DATA
ADDRESS
GSA052
Fig.16 8 or 16-bit addressed 8031 register read timing diagram.
handbook,MICRO_ADDR
full pagewidth [7:0]
ADDRESS
(16-bit mode only)
ADDRESS
t3
MICRO_ALE
t6
t17
t4
MICRO_CS
t12
t14
t13
MICRO_WRITE
t18
t1
MICRO_DATA [7:0]
t2
t15
ADDRESS
t16
DATA
ADDRESS
DATA
GSA053
Fig.17 8 or 16-bit addressed 8031 register write timing diagram.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
handbook, full pagewidth
MICRO_ADDR
ADDRESS
t6
MICRO_CS
t7
t8
t9
MICRO_READ
t10
t11
t5
MICRO_DATA
DATA
GSA054
Fig.18 8-bit addressed H8 register read timing diagram.
handbook, full pagewidth
MICRO_ADDR
ADDRESS
t6
MICRO_CS
t7
t8
t9
MICRO_READ
t10
t11
t5
MICRO_DATA
DATA
t19
MICRO_WAIT
t 20
GSA055
Fig.19 8-bit addressed H8 register read timing diagram with MICRO_WAIT asserted.
2000 Nov 17
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
handbook, full pagewidth
MICRO_ADDR
SAA7356HL
ADDRESS
ADDRESS
MICRO_CS
t12
t14
t13
MICRO_WRITE
t15
MICRO_DATA
t18
t16
DATA
DATA
GSA056
Fig.20 8-bit addressed H8 register write timing diagram.
handbook, full pagewidth
MICRO_ADDR [7:0]
ADDRESS
t3
MICRO_ALE
t6
t4
MICRO_CS
t7
t8
t9
MICRO_READ
t1
t2
t11
t10
t5
MICRO_DATA [7:0]
DATA
ADDRESS
GSA057
Fig.21 16-bit addressed V851 register read timing diagram.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
handbook, full pagewidth
MICRO_ADDR [7:0]
SAA7356HL
ADDRESS
ADDRESS
t3
MICRO_ALE
t6
t17
t4
MICRO_CS
t12
t14
t13
MICRO_WRITE
t18
t1
MICRO_DATA [7:0]
t2
t15
t16
DATA
ADDRESS
DATA
ADDRESS
GSA058
Fig.22 16-bit addressed V851 register write timing diagram.
13 APPLICATION INFORMATION
handbook, full pagewidth
DRAM
CD-RW ENGINE
I2S-bus
CD-RW
LOADER
SPI
BUFFER MANAGER
DMA
SAA7391
SBP-2 LINK
SAA7356HL
PHY
1394 bus
1394 PHY
GSA059
MICROCONTROLLER
Fig.23 Application diagram.
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
14 PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
c
y
X
A
60
41
40 Z E
61
e
E HE
A A2
(A 3)
A1
w M
θ
bp
L
pin 1 index
80
Lp
21
detail X
20
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.16
0.04
1.5
1.3
0.25
0.27
0.13
0.18
0.12
12.1
11.9
12.1
11.9
0.5
HD
HE
14.15 14.15
13.85 13.85
L
Lp
v
w
y
1.0
0.75
0.30
0.2
0.15
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT315-1
136E15
MS-026
2000 Nov 17
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
If wave soldering is used the following conditions must be
observed for optimal results:
15 SOLDERING
15.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
15.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
15.3
15.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Nov 17
Manual soldering
32
Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
15.5
SAA7356HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Nov 17
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Philips Semiconductors
Preliminary specification
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SAA7356HL
16 DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
17 DEFINITIONS
18 DISCLAIMERS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Nov 17
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Philips Semiconductors
Preliminary specification
1394 SBP-2 link layer controller
SAA7356HL
NOTES
2000 Nov 17
35
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Internet: http://www.semiconductors.philips.com
SCA 70
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp36
Date of release: 2000
Nov 17
Document order number:
9397 750 06181