INTEGRATED CIRCUITS 80C562/83C562 Single-chip 8-bit microcontroller Product specification IC20 Data Handbook 1992 Jan 08 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM DESCRIPTION The 80C562/83C562 (hereafter generically referred to as 8XC562) Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 83C562/83C562 has the same instruction set as the 80C51. The 8XC562 contains a non-volatile 256 × 8 read-only program memory, a volatile 256 × 8 read/write data memory (83C562) (the 80C562 is ROMless), a volatile 256 × 8 read/write data memory, six 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, two pulse width modulated outputs, standard 80C51 UART, a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 83C562 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 12MHz crystal, 58% of the instructions are executed in 1µs and 40% in 2µs. Multiply and divide instructions require 4µs. FEATURES • 80C51 instruction set • 8k × 8 ROM expandable externally to PIN CONFIGURATION 9 1 61 64k bytes • 256 × 8 RAM, expandable externally to 10 60 PLASTIC LEADED CHIP CARRIER 64k bytes • Two standard 16-bit timer/counters • An additional 16-bit timer/counter coupled 26 to four capture registers and three compare registers 44 27 43 • Capable of producing eight synchronized, timed outputs • An 8-bit ADC with eight multiplexed analog inputs • Two 8-bit resolution, pulse width modulated outputs • Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs • Full-duplex UART compatible with the standard 80C51 • On-chip watchdog timer • Three temperature ranges – 0 to +70°C – –40 to +85°C – –40 to +125°C Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function P5.0/ADC0 VDD STADC PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6 P1.7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC XTAL2 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function XTAL1 VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref– AVref+ AVSS AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 SU00224 1992 Jan 08 2 853–1463 05128 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING ROMless ROM ROM Drawing Number EPROM Drawing Number S83C562-4A68 SOT188 S87C552-4A682 SOT188-3 0 to +70, Plastic Leaded Chip Carrier 16 S87C552-4K682 1473A 0 to +70, Plastic Leaded Chip Carrier w/Window 16 S87C552-5A682 SOT188-3 S87C552-5K682 1473A ROMless PCB80C562- PCB83C562S80C562-4A68 16WP 16WP/xxx PCF80C56212WP TEMPERATURE RANGE °C PHILIPS NORTH AMERICA PART ORDER NUMBER PCF83C56212WP/xxx S80C562-2A68 S83C562-2A68 SOT188 PCA80C562- PCA83C562- S80C562-6A68 S83C562-6A68 SOT188 12WP 12WP/xxx NOTES: 1. 80C562 and 83C562 frequency range is 1.2MHz–12MHz or 1.2MHz–16MHz. 2. 87C552 frequency range is 3.5MHz–16MHz. For full specification, see the 87C552 data sheets. 3. xxx denotes the ROM code number. LOGIC SYMBOL LOW ORDER ADDRESS AND DATA BUS CT0I CT1I CT2I CT3I T2 RT2 PORT 1 XTAL1 XTAL2 EA ALE PSEN AVSS AVDD AVref+ AVref– STADC PWM0 PWM1 PORT 0 VSS VDD PORT 2 PORT 5 ADC0-7 HIGH ORDER ADDRESS AND DATA BUS CMT0 CMT1 RST EW RxD TxD PORT 3 PORT 4 CMSR0-5 INT0 INT1 T0 T1 WR RD SU00225 1992 Jan 08 3 AND PACKAGE –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Plastic Leaded Chip Carrier w/Window –40 to +125, Plastic Leaded Chip Carrier FREQ MHz 12 12 12 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 BLOCK DIAGRAM T0 T1 3 INT0 3 INT1 3 PWM0 VDD 3 PWM1 AVSS AVREF ADC0–7 – + VSS AVDD 5 STADC XTAL1 T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS XTAL2 PROGRAM MEMORY 8k x 8 ROM (83C562) CPU EA ALE DUAL PWM ADC 80C51 CORE EXCLUDING ROM/RAM PSEN 3 DATA MEMORY 256 x 8 RAM WR 8-BIT INTERNAL BUS 3 RD 16 0 AD0–7 PARALLEL I/O PORTS AND EXTERNAL BUS 2 SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES A8–15 3 P0 0 1 2 P1 P2 P3 TxD 3 RxD 1 P5 P4 CT0I–CT3I ALTERNATE FUNCTION OF PORT 0 3 ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 1 4 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 2 5 ALTERNATE FUNCTION OF PORT 5 T2 16-BIT TIMER/ EVENT COUNTERS 1 16 1 T2 RT2 T2 16-BIT COMPARATORS WITH REGISTERS COMPARATOR OUTPUT SELECTION T3 WATCHDOG TIMER 4 CMSR0–CMSR5 CMT0, CMT1 RST EW SU00226 1992 Jan 08 4 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 PIN DESCRIPTION PIN NO. TYPE VDD MNEMONIC 2 I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. STADC 3 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). PWM0 4 O Pulse Width Modulation: Output 0. PWM1 5 O Pulse Width Modulation: Output 1. EW 6 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. P0.0–P0.7 57–50 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. P1.0–P1.7 16–23 16–23 16–19 20 21 I/O I/O I/O I I Port 1: 8-bit I/O port. Alternate functions include: (P1.0–P1.7): Quasi-bidirectional port pins. CT0I–CT3I (P1.0–P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input RT2 (P1.5): T2 timer reset signal. Rising edge triggered. P2.0–P2.7 39–46 I/O Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08–A15). P3.0–P3.7 24–31 24 25 26 27 28 29 30 31 I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. P4.0–P4.7 7–14 7–12 13, 14 I/O O O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: CMSR0–CMSR5 (P4.0–P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. P5.0–P5.7 68–62, 1 I RST 15 I/O XTAL1 35 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. XTAL2 34 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open–circuit when an external clock is used. 36, 37 I Digital ground. PSEN 47 O Program Store Enable: Active-low read strobe to external program memory. ALE 48 O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. EA 49 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. AVREF– 58 I Analog to Digital Conversion Reference Resistor: Low-end. AVREF+ 59 I Analog to Digital Conversion Reference Resistor: High-end. AVSS 60 I Analog Ground AVDD 61 I Analog Power Supply VSS NAME AND FUNCTION Port 5: 8-bit input port. ADC0–ADC7 (P5.0–P5.7): Alternate function: Eight input channels to ADC. Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows. NOTE: 1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD +0.5V or VSS – 0.5V, respectively. 1992 Jan 08 5 Philips Semiconductors Product specification Single-chip 8-bit microcontroller OSCILLATOR CHARACTERISTICS RESET XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Table 1. 80C562/83C562 A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. IDLE MODE In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register PCON. Table 1 shows the state of the I/O ports during low current operating modes. External Pin Status During Idle and Power-Down Modes PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PWM0/ PWM1 Idle Internal 1 1 Data Data Data Data Data High Idle External 1 1 Float Data Address Data Data High Power-down Internal 0 0 Data Data Data Data Data High Power-down External 0 0 Float Data Data Data Data High MODE ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER RATING UNIT –0.5 to +6.5 V Input, output DC current on any single I/O pin 5.0 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W –65 to +150 °C Voltage on any other pin to VSS Storage temperature range NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1992 Jan 08 6 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 DC ELECTRICAL CHARACTERISTICS VSS, AVSS = 0V TEST SYMBOL VDD IDD IID IPD PARAMETER CONDITIONS Supply voltage PCB8XC562 PCF8XC562 PCA8XC562 LIMITS MIN MAX UNIT 4.0 4.0 4.5 6.0 6.0 5.5 V V V Supply current operating: PCB8XC562 PCF8XC562 PCA8XC562 See notes 1 and 2 fOSC = 16MHz fOSC = 12MHz fOSC = 12MHz 45 34 30 mA mA mA Idle mode: PCB8XC562 PCF8XC562 PCA8XC562 See notes 1 and 3 fOSC = 16MHz fOSC = 12MHz fOSC = 12MHz 10 8 7 mA mA mA 50 50 100 µA µA µA Power-down current: See notes 1 and 4; 2V < VPD < VDD max PCB8XC562 PCF8XC562 PCA8XC562 Inputs VIL Input low voltage, except EA –0.5 0.2VDD–0.1 V VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V VIH Input high voltage, except XTAL1, RST 0.2VDD+0.9 VDD+0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V IIL Logical 0 input current, ports 1, 2, 3, 4 VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4 See note 5 –650 µA +IIL1 Input leakage current, port 0, EA, STADC, EW 0.45V < VI < VDD 10 µA IOL = 1.6mA6 0.45 V 3.2mA6 0.45 V Outputs VOL Output low voltage, ports 1, 2, 3, 4 VOL1 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 VOH Output high voltage, ports 1, 2, 3, 4 VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)7 VOH2 Output high voltage (RST) RRST Internal reset pull-down resistor CIO Pin capacitance 1992 Jan 08 IOL = VDD + 5V+10% –IOH = 60µA –IOH = 25µA –IOH = 10µA 2.4 0.75VDD 0.9VDD V V V VDD + 5V+10% –IOH = 400µA –IOH = 150µA –IOH = 40µA 2.4 0.75VDD 0.9VDD V V V –IOH = 400µA –IOH = 120µA 2.4 0.8VDD V V 50 Test freq = 1MHz, Tamb = 25°C 7 150 kΩ 10 pF Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 DC ELECTRICAL CHARACTERISTICS (Continued) TEST SYMBOL PARAMETER LIMITS CONDITIONS MIN MAX UNIT Analog supply voltage: PCB8XC562 PCF8XC562 PCA8XC562 AVDD = VDD±0.2V AVDD = VDD±0.2V AVDD = VDD±0.2V 4.0 4.0 4.5 6.0 6.0 5.5 V V V AIDD Analog supply current: operating: Port 5 = 0 to AVDD 1.2 mA AIID Idle mode: PCB8XC562 PCF8XC562 PCA8XC562 50 50 100 µA µA µA 50 50 100 µA µA µA AVDD+0.2 V AVDD+0.2 V V 25 kΩ 15 pF Analog Inputs AVDD AIPD Power-down mode: PCB8XC562 PCF8XC562 PCA8XC562 2V < AVPD < AVDD max AVIN Analog input voltage AVSS–0.2 AVREF Reference voltage: AVREF– AVREF+ AVSS–0.2 RREF Resistance between AVREF+ and AVREF– CIA Analog input capacitance 5 tADS Sampling time 6tCY µs tADC Conversion time (including sampling time) 24tCY µs DLe Differential non-linearity8, 9, 10 ±1 LSB ILe Integral non-linearity8, 11 ±1 LSB error8, 12 OSe Offset Ge Gain error8, 13 MCTC Channel to channel matching Ct Crosstalk between inputs of port 514 0–100kHz ±1 LSB 0.4 % ±1 LSB –60 dB NOTES: 1. See Figures 8 through 12 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 7. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 8. Conditions: AVREF– = 0V; AVDD = 5.0V, AVREF+ = 5.12V. ADC is monotonic with no missing codes. 9. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 10. The ADC is monotonic; there are no missing codes. 11. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.) 12. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 1.) 13. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.) 14. This should be considered when both analog and digital signals are simultaneously input to port 5. 1992 Jan 08 8 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 Offset error OSe Gain error Ge 255 254 253 252 251 250 (2) 7 (1) Code Out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 250 251 252 253 254 255 256 AVIN (LSBideal) Offset error OSe 1 LSB = AVREF+ – AVREF– 256 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve. SU00227 Figure 1. ADC Conversion Characteristic 1992 Jan 08 9 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 AC ELECTRICAL CHARACTERISTICS1, 2 12MHz CLOCK PARAMETER MIN VARIABLE CLOCK SYMBOL FIGURE MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency 1.2 16 MHz tLHLL 2 ALE pulse width 127 2tCLCL–40 ns tAVLL 2 Address valid to ALE low 28 tCLCL–55 ns tLLAX 2 Address hold after ALE low 48 tCLCL–35 ns tLLIV 2 ALE low to valid instruction in tLLPL 2 ALE low to PSEN low 43 tCLCL–40 ns tPLPH 2 PSEN pulse width 205 3tCLCL–45 ns tPLIV 2 PSEN low to valid instruction in tPXIX 2 Input instruction hold after PSEN tPXIZ 2 Input instruction float after PSEN 59 tCLCL–25 ns tAVIV 2 Address to valid instruction in 312 5tCLCL–105 ns tPLAZ 2 PSEN low to address float 10 10 ns tAVLL 3, 4 Address valid to ALE low 43 tCLCL–35 ns tRLRH 3 RD pulse width 400 6tCLCL–100 ns tWLWH 4 WR pulse width 400 6tCLCL–100 ns tRLDV 3 RD low to valid data in tRHDX 3 Data hold after RD tRHDZ 3 Data float after RD 97 2tCLCL–70 ns tLLDV 3 ALE low to valid data in 517 8tCLCL–150 ns tAVDV 3 Address to valid data in 585 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 200 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 203 tQVWX 4 Data valid to WR transition tDW 4 Data before WR tWHQX 4 Data hold after WR 33 tRLAZ 3 RD low to address float tWHLH 3, 4 234 4tCLCL–100 145 3tCLCL–105 0 0 ns ns ns Data Memory 252 5tCLCL–165 0 0 300 3tCLCL–50 ns ns 4tCLCL–130 ns 23 tCLCL–60 ns 433 7tCLCL–150 ns tCLCL–50 ns 0 RD or WR high to ALE high 43 123 tCLCL–40 0 ns tCLCL+40 ns External Clock tCHCX 5 High time3 20 20 ns tCLCX 5 Low time3 20 20 ns tCLCH 5 Rise time3 20 20 ns tCHCL 5 Fall time3 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. 1992 Jan 08 10 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 INSTR IN tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 2. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A0–A15 FROM PCH SU00007 Figure 3. External Data Memory Read Cycle 1992 Jan 08 11 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 ALE tWHLH PSEN tWLWH tLLWL WR tAVLL tLLAX tWHQX tQVWX tDW PORT 0 A0–A7 FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH SU00213 Figure 4. External Data Memory Write Cycle tr tHIGH VIH1 VIH1 0.8V tf VIH1 0.8V VIH1 0.8V 0.8V tLOW tCK SU00228 Figure 5. External Clock Drive XTAL1 2.4V 2.0V 2.0V Test Points 0.8V 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’. SU00215 Figure 6. AC Testing Input/Output Float 2.4V 0.45V 2.4V 2.0V 2.0V 0.8V 0.8V 0.45V NOTE: The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels. SU00216 Figure 7. AC Testing Input, Float Waveform 1992 Jan 08 12 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 50 (1) 40 30 IDD mA 20 (2) 10 (3) (4) 0 NOTE: These values are valid only within the frequency specifications of the device under test. 0 4 8 12 16 f (MHz) (1) (2) (3) (4) Maximum operating mode; VDD = 6V Maximum operating mode; VDD = 4V Maximum idle mode; VDD = 6V Maximum idle mode; VDD = 4V SU00229 Figure 8. Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC) VDD IDD VDD VDD VDD P0 RST EA (NC) XTAL2 CLOCK SIGNAL XTAL1 EW VSS STADC SU00230 Figure 9. IDD Test Condition, Active Mode All other pins are disconnected VDD IDD VDD RST VDD STADC P0 EW (NC) XTAL2 CLOCK SIGNAL XTAL1 EA AVSS VSS AVref SU00231 Figure 10. IDD Test Condition, Idle Mode All other pins are disconnected 1992 Jan 08 13 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 VDD–0.5 0.5V tCHCL tCHCX tCLCH tCLCX tCLCL SU00232 Figure 11. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 10ns VDD IDD VDD VDD RST STADC P0 EW (NC) XTAL2 EA XTAL1 AVSS VSS AVref SU00233 Figure 12. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V 1992 Jan 08 14 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 PLCC68: plastic leaded chip carrier; 68 leads; pedestal 1992 Jan 08 15 SOT188-3 1992 Jan 08 853-1473A 05854 16 SEE DETAIL A 11.94 (0.470) 11.18 (0.440) 11.94 (0.470) 11.18 (0.440) 20.32 (0.800) NOMINAL 64X 1.27 (0.050) 25.27 (0.995) 25.02 (0.985) 3 X 0.63 (0.025) R MIN. 3 4.83 (0.190) 3.94 (0.155) SEATING PLANE 6 0.51 (0.02) X 45 ° 6 0.38 (0.015) 0.482 (0.019 + 0.002) BASE PLANE 45 ° TYP. 4 PLACES 0.73 + 0.08 (0.029 + 0.003) SEATING PLANE DETAIL A TYP. ALL SIDES mm/(inch) 1.02 + 0.25 (0.040 + 0.010) 1.52 (0.060) REF. 1.27 (0.050) TYP. 24.51 (0.965) 23.62 (0.930) 25.27 (0.995) 25.02 (0.985) 3.05 (0.120) 2.29 (0.090) 0.25 (0.010) 0.15 (0.006) 0.15 (0.006) MIN. 0.25 (0.010) R MIN. + 5° –10 ° DETAIL B mm/(inch) 90° 0.508 (0.020) R MIN. 0.076 (0.003) MIN. 6. Backside solder relief is optional and dimensions are for reference only. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum on each side. 4. Controlling dimension millimeters. 2. UV window is optional. NOTES: 1. All dimensions and tolerances to conform to ANSI Y14.5–1982. Single-chip 8-bit microcontroller SEE DETAIL B SEATING PLANE 4.83 (0.190) 3.94 (0.155) 2 CHAMFER 45 24.51 (0.965) 3 23.62 (0.930) 1473A 1.02 (0.040) X 45° 25.27 (0.995) 25.02 (0.985) Philips Semiconductors Product specification 80C562/83C562 68-PIN CERQUAD J-BEND (K) PACKAGE Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 NOTES 1992 Jan 08 17 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 NOTES 1992 Jan 08 18 Philips Semiconductors Product specification Single-chip 8-bit microcontroller 80C562/83C562 NOTES 1992 Jan 08 19 Philips Semiconductors Microcontroller Products Product specification Single-chip 8-bit microcontroller 80C562/83C562 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1992 All rights reserved. Printed in U.S.A.