Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML FEATURES • Programmable Macro Logic device • Full connectivity • TTL compatible • SNAP development system: PLHS501/PLHS501I PIN CONFIGURATION A Package (52-pin PLCC) I17 I16 I15 I14 I13 I12 I11 I10 I9 7 6 5 4 3 2 1 I8 I7 I6 I5 52 51 50 49 48 47 VCC 8 46 VCC – Supports third-party schematic entry formats I18 9 45 I4 I19 10 44 I3 – Macro library I20 11 43 I2 – Versatile netlist format for design portability I21 12 42 I1 I22 13 41 I0 – Logic, timing, and fault simulation I23 14 40 B3 B4 15 39 B2 B5 16 38 B1 B6 17 37 B0 B7 18 36 X7 O0 19 35 X6 • Delay per internal NAND function = 6.5ns (typ) • Testable in unprogrammed state • Security fuse allows protection of proprietary designs GND 20 34 GND 21 22 23 24 25 26 27 28 29 30 31 32 33 O1 O2 O3 O4 O5 O6 O7 X0 X1 X2 X3 X4 X5 STRUCTURE • NAND gate based architecture – 72 foldback NAND terms • 136 input-wide logic terms • 44 additional logic terms • 24 dedicated inputs (I0 – I23) • 8 bidirectional I/Os with individual 3-State enable: – 4 Active-High (B4 – B7) – 4 Active-Low (B0 – B3) • 16 dedicated outputs: – 4 Active-High outputs O0, O1 with common 3-State enable O2, O3 with common 3-State enable – 4 Active-Low outputs: O4, O5 with common 3-State enable O6, O7 with common 3-State enable – 8 Exclusive-OR outputs: X0, X1 with common 3-State enable X2, X3 with common 3-State enable DESCRIPTION ARCHITECTURE The PLHS501 is a high-density Bipolar Programmable Macro Logic device. PML incorporates a programmable NAND structure. The NAND architecture is an efficient method for implementing any logic function. The SNAP software development system provides a user friendly environment for design entry. SNAP eliminates the need for a detailed understanding of the PLHS501 architecture and makes it transparent to the user. PLHS501 is also supported on the Philips Semiconductors SNAP software development systems. The core of the PLHS501 is a programmable fuse array of 72 NAND gates. The output of each gate folds back upon itself and all other NAND gates. In this manner, full connectivity of all logic functions is achieved in the PLHS501. Any logic function can be created within the core of the device without wasting valuable I/O pins. Furthermore, a speed advantage is acquired by implementing multi-level logic within a fast internal core without incurring any delays from the I/O buffers. The PLHS501 is ideal for a wide range of microprocessor support functions, including bus interface and control applications. The PLHS501 is also processed to industrial requirements for operation over an extended temperature range of –40°C to +85°C and supply voltage of 4.5V to 5.5V. X4, X5 with common 3-State enable X6, X7 with common 3-State enable PML is a trademark of Philips Semiconductors October 22, 1993 1 853–1207 11164 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I ORDERING INFORMATION DESCRIPTION OPERATING CONDITIONS ORDER CODE DRAWING NUMBER 52-Pin Plastic Leaded Chip Carrier Commercial Temperature Range ±5% Power Supply PLHS501A 0397E 52-Pin Plastic Leaded Chip Carrier Industrial Temperature Range ±10% Power Supply PLHS501IA 0397E DESIGN DEVELOPMENT TOOLS SNAP The SNAP Software Development System provides the necessary tools for designing with PML. SNAP provides the following: • Schematic entry netlist generation from third-party schematic design packages such as OrCAD/SDT III and FutureNet. • Macro library for standard TTL functions and user defined functions • Boolean equation entry • State equation entry • Syntax and design entry checking • Simulator includes logic simulation, fault SNAP operates on an IBM PC/XT, PC/AT, PS/2, or any compatible system with DOS 2.1 or higher. The minimum system configuration for SNAP is 640K bytes of RAM and a hard disk. SNAP provides primitive PML function libraries for third-party schematic design packages. Custom macro function libraries can be defined in schematic or equation form. After the completion of a design, the software compiles the design for syntax and completeness. Complete simulation can be carried out using the different simulation tools available. The programming data is generated in JEDEC format. Using the Device Programmer Interface (DPI) module of SNAP, simulation and timing simulation. FutureNet is a trademark of FutureNet Corporation. OrCAD/SDT is a trademark of OrCAD, Inc. IBM is a registered trademark of International Business Machines Corporation. October 22, 1993 2 the JEDEC fusemap is sent from the host computer to the device programmer. DESIGN SECURITY The PLHS501 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I PLHS501 FUNCTIONAL BLOCK DIAGRAM 24 DEDICATED INPUTS I N T E R C O N N E C T NAND ARRAY 16 DEDICATED OUTPUTS 8 BIDIRECTIONAL I/OS October 22, 1993 3 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I FUNCTIONAL DIAGRAM 71 0 I0 I23 x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 x4 B4 – B7 x4 x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 x2 O0, O2 x2 x2 x2 O1, O3 O4, O6 O5, O7 DETAIL A October 22, 1993 4 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I DETAIL A 40 B3 39 B2 38 B1 37 B0 15 B4 16 B5 17 B6 18 B7 28 X0 29 X1 30 X2 31 X3 32 X4 33 X5 35 X6 36 X7 19 O0 21 O1 22 O2 23 O3 24 O4 25 O5 26 O6 27 O7 October 22, 1993 5 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I ABSOLUTE MAXIMUM RATINGS1 RATINGS SYMBOL PARAMETER MIN MAX UNIT +7 VDC VCC Supply voltage VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents +30 mA IOUT Output currents Tamb Operating temperature range Tstg Storage temperature range –30 +100 mA 0 +75 °C –65 +150 °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS VIRGIN STATE Maximum junction 150°C A factory shipped virgin device contains all fusible links open, such that: 1. All product terms are enabled. Maximum ambient 75°C 2. All bidirectional (B) pins are outputs. Allowable thermal rise ambient to junction 75°C TEMPERATURE October 22, 1993 3. All outputs are enabled. 4. All outputs are Active-High except B0 – B3 (fusible I/O) and O4 – O7 which are Active-Low. 6 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I DC ELECTRICAL CHARACTERISTICS Commercial= 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V Industrial = –40°C ≤ Tamb ≤ +85°C, 4.5V ≤ VCC ≤ 5.5V LIMITS SYMBOL Input PARAMETER TEST CONDITION MIN VCC = MIN VCC = MAX VCC = MIN, IIN = –12mA 2.0 TYP1 MAX UNIT 0.8 V V V voltage2 VIL VIH VIC Low High Clamp2, 3 –0.8 –1.2 Output voltage VCC = MIN IOL = 10mA IOH = –2mA Low2, 4 High2, 5 VOL VOH 0.45 V V VCC = MAX VIN = 0.45V VIN = 5.5V –100 40 µA µA VCC = MAX VOUT = 5.5V VOUT = 0.45V VOUT = 0V 80 –140 –70 µA mA 295 mA 2.4 Input current IIL IIH Low High Output current IO(OFF) Hi-Z state9 IOS Short circuit3, 5, 6 ICC VCC supply current8 VCC = MAX 225 Input I/O VCC = 5V VIN = 2.0V VOUT = 2.0V 8 15 –15 Capacitance CIN CB pF pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. For Pins 15 – 19, 21 – 27 and 37 – 40, VOL is measured with Pins 5 and 41 = 8,75V, Pin 43 = 0V and Pins 42 and 44 = 4.5V. For Pins 28 – 33 and 35 – 36, VOL is measured under same conditions EXCEPT Pin 44 = 0V. 5. VOH is measured with Pins 5 and 41 = 8.75V, Pins 42 and 43 = 4.5V and Pin 44 = 0V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with all dedicated inputs at 0V and bidirectional and output pins open. 8. Measured at VT = VOL + 0.5V. 9. Leakage values are a combination of input and output leakage. TEST LOAD CIRCUITS VOLTAGE WAVEFORMS VCC C1 +5V +3.0V S1 90% 10% C2 R1 BY I0 INPUTS I10 BW GND 2.5ns R2 DUT BZ BX CL tR tF 2.5ns +3.0V 90% 10% OUTPUTS OX 0V 2.5ns 2.5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. NOTE: C1 and C2 are to bypass VCC to GND. October 22, 1993 0V Input Pulses 7 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I SNAP RESOURCE SUMMARY DESIGNATIONS 71 I0 0 DIN501 NIN501 I23 FBNAND NAND x2 x2 x2 x2 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 B0 – B3 OUT501 B4 – B7 NOU501 x4 X0, X2, X4, X6 x4 X1, X3, X5, X7 EXO501 x2 O0, O2 x2 x2 x2 October 22, 1993 8 NOU501 O1, O3 O4, O6 O5, O7 TOU501 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I MACRO CELL SPECIFICATIONS1 (SNAP Resource Summary Designations in Parantheses) Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Industrial: Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Input Buffer (DIN501 [Non-inverting], NIN501 [Inverting]) X I Y LIMITS SYMBOL MIN ∆tHL ∆tLH 0.05 –0.02 TYP PARAMETER MAX UNIT 0.1 0.15 ns/p-term –0.05 –0.08 ns/p-term LIMITS SYMBOL To (Output) From (Input) MIN TYP MAX UNIT NOTES tPHL tPLH X X I I 4.5 5 5.5 6 6.5 7.5 ns ns With 0 p-terms load tPHL tPLH Y Y I I 2.5 4 3 4 3.5 4.5 ns ns With 0 p-terms load Input Pins: 1 – 7, 9 – 14, 41 – 45, 48 – 52. Bidirectional Pins: 15 – 18, 37 – 40. Maximum internal fan-out: 16 p-terms on X or Y. NAND Output Buffer with 3-State Control (TOU501) Tri–Ctrl In Out PARAMETER LIMITS SYMBOL To (Output) From (Input) MIN TYP MAX UNIT tPHL tPLH Out Out In In 8.5 8.5 14.0 14.0 17.5 16 ns ns tOE2 tOD2 Out Out Tri-Ctrl Tri-Ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns Output Pins: 24 – 27. Internal Foldback NAND (FBNAND) Input Output LIMITS SYMBOL ∆tPHL ∆tPLH MIN TYP MAX UNIT 0.05 0.1 0.15 ns/p-term –0.0 –0.05 –0.1 ns/p-term PARAMETER SYMBOL tPHL tPLH LIMITS To (Output) From (Input) MIN TYP MAX Out Any 4.0 5.5 4.5 6.5 6.8 8 Maximum internal loading of 16 terms. Notes are on following page. October 22, 1993 9 UNIT NOTES ns ns With 0 p-terms load Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I MACRO CELL SPECIFICATIONS1 (Continued) (SNAP Resource Summary Designations in Parantheses) Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω Industrial: Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω AND Output Buffer with 3-State Control (NOU501) Tri–Ctrl In Out PARAMETER LIMITS SYMBOL To (Output) From (Input) MIN TYP MAX UNIT tPHL tPLH Output Output In In 8.0 8.0 11 11 13 13 ns ns tOE2 tOD2 Out Out Tri-Ctrl Tri-Ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns Bidirectional and Output Pins: 19, 21, 22, 23, 15 – 18. NAND Output Buffer (OUT501) In Out PARAMETER LIMITS SYMBOL To (Output) From (Input) MIN TYP MAX tPHL tPLH Out Out In In 8.5 8.5 14 14 17.5 16.0 UNIT ns ns Bidirectional Pins: 37 – 40. Ex–OR Output Buffer (EXO501) Tri–Ctrl A Out B PARAMETER LIMITS SYMBOL To (Output) From (Input) MIN TYP MAX UNIT tPHL tPLH Out Out A or B A or B 8.5 8.5 14 14 17.5 16.0 ns ns tOE2 tOD2 Out Out Tri-Ctrl Tri-Ctrl 8.5 8.5 15 12.5 18.5 17.0 ns ns Ex-OR Output Pins: 28 – 33. NOTES: 1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. October 22, 1993 10 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I PLHS501 GATE AND SPEED ESTIMATE TABLE FUNCTION INTERNAL NAND EQUVALENT TYPICAL tPD 1 1 1 1 6.5ns 6.5ns 6.5ns 6.5ns For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables For 1 to 32 input variables 8 16 32 11ns 11ns 11ns Inverted inputs available Inverted inputs available Inverted inputs available (24 chip outputs only) 15 32 41 11ns 11ns 11ns Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels Inverted inputs, 2 logic levels, factored solution. 5 9 17 28 11ns 11ns 11ns 11ns Inverted inputs available fMAX COMMENTS Gates NANDs ANDs NORs ORs Decoders 3-to-8 4-to-16 5-to-32 Encoders 8-to-3 16-to-4 32-to-5 Multiplexers 4-to-1 8-to-1 16-to-1 27-to-1 Can address only 27 external inputs - more if internal Flip-Flops D-type Flip-Flop T-type Flip-Flop J-K-type Flip-Flop 6 6 10 30MHz 30MHz 30MHz With asynchronous S-R With asynchronous S-R With asynchronous S-R Adders 8-bit 45 15.5ns 72 11ns Full carry-lookahead (four levels of logic) Barrel Shifters 8-bit 2 levels of logic Latches D-latch October 22, 1993 3 2 levels of logic with one shared gate 11 Philips Semiconductors Programmable Logic Devices Product specification Programmable macro logic PML PLHS501/PLHS501I APPLICATIONS MASTER SLAVE MODULE SPECIFIC MODULE SPECIFIC ARBITRATION BUS CONTROL PLHS501 CLOCK ORIGINATION SLOT ID SLOT ID CLOCK ADDRESS, DATA, CONTROL AND PARITY NUBUS ARBITRATION Simplified NUBUS Diagram (10MHz Operating Frequency) BUFEN TRANSCEIVER CONTROL –ADL –CDSETUP –M/–IO –S1 –S0 –A2 –A1 –A0 7-BIT LATCH DIR 7 POS BYTE 2 DATA OUTPUT 8-BIT LATCH –CMD D07 | D00 8 8 CHRESET POS BYTE 2 CARD I.D. OCTAL 3 to 1 MULTIPLEXER 8 POS BYTE 1 CARD I.D. 8 3-STATE DRIVER 8 POS BYTE 0 Block Diagram of Basic POS Implementation in PLHS501 NuBus is a trademark of Texas Instruments, Inc. October 22, 1993 12 8