INTEGRATED CIRCUITS 74LV259 8-bit addressable latch Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 FEATURES DESCRIPTION • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV259 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT259. The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is a multifunction device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporate an active LOW common reset (MR) for resetting all latches, as well as an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. Tamb = 25°C • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Output from each storage bit available • Random (addressable) data entry • Easily expandable • Common reset input • Useful as a 3-to-8 active HIGH decoder • Output capability: standard • ICC category: MSI In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and date (D) input. When operating the 74LV259 as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the 74LV259. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL CONDITIONS tPHL/tPLH Propagation delay D, An to Qn LE to Qn MR to Qn CL = 15 pF; VCC = 3.3 V CI Input capacitance CPD Power dissipation capacitance per latch TYPICAL 17 16 14 VI = GND to VCC1 UNIT ns 3.5 pF 19 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40°C to +125°C 74LV259 N 74LV259 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV259 D 74LV259 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV259 DB 74LV259 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV259 PW 74LV259PW DH SOT403-1 1998 May 20 2 853-1988 19420 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 PIN CONFIGURATION PIN DESCRIPTION A0 1 16 VCC A1 2 15 MR A2 3 14 Q0 4 Q1 5 FUNCTION A0 to A2 Address inputs LE 4, 5, 6, 7, 9, 10, 11, 12 Q0 to Q7 Latch outputs 13 D 8 GND Ground (0 V) 12 Q7 13 D Data input 14 LE Latch enable input (active LOW) 15 MR Conditional reset input (active LOW) 16 VCC Positive supply voltage 6 11 Q6 Q3 7 10 Q5 8 SYMBOL 1, 2, 3 Q2 GND PIN NUMBER 9 Q4 SV01602 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 15 13 14 LE 13 D Q0 4 Q1 5 6 1 7 2 3 9 Q4 2 A1 Q5 10 3 A2 Q6 11 Q7 12 MR 9, 10D 0 Q2 A0 Z9 DX Q3 1 G8 14 0 0 G 7 2 1 C10 8R 4 5 1 6 2 7 3 9 4 10 5 15 SV01601 11 6 12 7 SV01603 FUNCTIONAL DIAGRAM MODE SELECT TABLE Q0 1 A0 2 A1 1-of–8 DECODER 3 A2 4 Q1 5 Q2 6 Q3 7 Q4 9 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 8 LATCHES SV01604 1998 May 20 3 LE MR MODE L H Addressable latch H H Memory L L Active HIGH 8-channel demultiplexer H L Reset Philips Semiconductors Product specification 8-bit addressable latch 74LV259 FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS MR LE D A0 A1 A2 L H X X X L L d L L L L d H L L d L L L d H L L d L L d L L d L L d H H X H L d H L d H L H L H Master reset Demultiplex ((active HIGH)) decoder (when D = H) Store (do nothing) Addressable latch Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 X L L L L L L L L L Q=d L L L L L L L L L L Q=d L L L L L L H L L L Q=d L L L L L H L L L L Q=d L L L L L L H L L L L Q=d L L L H L H L L L L L Q=d L L L H H L L L L L L Q=d L H H H L L L L L L L Q=d X X X q0 q1 q2 q3 q4 q5 q6 q7 L L L Q=d q1 q2 q3 q4 q5 q6 q7 H L L q0 Q=d q2 q3 q4 q5 q6 q7 d L H L q0 q1 Q=d q3 q4 q5 q6 q7 d H H L q0 q1 q2 Q=d q4 q5 q6 q7 L d L L H q0 q1 q2 q3 Q=d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q=d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q=q q7 H L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d NOTES: H = HIGH voltage level L = LOW voltage level X = don’t care d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition q = lower case letters indicate the state of the referenced output established during the last cycle established during the last cycle in which it was addressed or cleared RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP MAX UNIT See Note 1 1.0 3.3 3.6 V DC supply voltage VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 May 20 4 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). PARAMETER SYMBOL CONDITIONS RATING UNIT VCC DC supply voltage –0.5 to +4.6 V IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 mA 50 mA –65 to +150 °C IGND, ICC Tstg PTOT DC VCC or GND current for types with – standard outputs Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level l l Input I t voltage LOW level l l Input I t voltage HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs VOL O LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs 1998 May 20 -40°C to +125°C MAX MIN VCC = 1.2 V 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0.25 0.40 0.50 5 V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA VCC = 3.0 V; VI = VIH or VIL; IO = 6mA UNIT MAX VCC = 1.2 V VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VOH O TYP1 V V Philips Semiconductors Product specification 8-bit addressable latch 74LV259 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS TYP1 MIN II ICC ∆ICC -40°C to +125°C MAX MIN UNIT MAX Input leakage current VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA Quiescent supply current; MSI VCC = 3.6 V; VI = VCC or GND; IO = 0 20.0 160 µA Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA –40 to +125 °C UNIT NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM VCC(V) tPHL//tPLH tPHL//tPLH tPHL//tPLH tPHL Propagation g delayy D to Qn Propagation g delayy An to Qn Propagation delayy g LE to Qn Propagation delayy g MR to Qn LIMITS CONDITION –40 to +85 °C MIN tw LE pulse l width idth HIGH or LOW MR pulse l width idth LOW Set-up time D, An to LE 1998 May 20 Hold time D to LE MAX 105 36 49 61 2.7 26 36 45 3.0 to 3.6 202 29 36 1.2 105 2.0 36 49 61 2.7 26 36 45 3.0 to 3.6 202 29 36 1.2 100 2.0 34 48 60 2.7 25 35 44 3.0 to 3.6 192 28 35 1.2 90 2.0 31 43 53 2.7 23 31 39 172 25 Figure 2 Figure 3 Figure 1 Figure 4 2.0 34 41 2.7 25 8 30 20 62 24 2.0 34 10 41 2.7 25 8 30 3.0 to 3.6 20 62 24 Figure 4 24 12 29 2.7 18 9 21 3.0 to 3.6 14 72 17 5 –10 5 2.7 5 –8 5 3.0 to 3.6 5 –62 5 6 ns ns ns ns ns –30 2.0 Figure 5 ns 35 2.0 Figure 5 and 6 ns 31 10 3.0 to 3.6 Figure 1 1.2 th MIN 2.0 1.2 tsu MAX 1.2 3.0 to 3.6 tw TYP1 ns Philips Semiconductors Product specification 8-bit addressable latch 74LV259 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM –40 to +85 °C CONDITION VCC(V) MIN 1.2 Hold time An to LE th TYP1 –40 to +125 °C MAX MIN –20 2.0 5 –7 5 2.7 5 –5 5 3.0 to 3.6 5 –42 5 Figure 6 UNIT MAX ns NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load. VCC An INPUT VM GND VCC tPHL Dn INPUT tPLH VOH GND Qn OUTPUT VCC LE INPUT VM VOL VM SV01607 GND tW tPHL Figure 3. Address inputs (An) to output (Qn) propagation delays. tPLH VOH Qn OUTPUT VM VCC VOL SV01605 MR INPUT Figure 1. Enable input (LE) to output (Qn) propagation delays and the enable input pulse width. VM GND tW tPHL VOH VCC Qn OUTPUT Dn INPUT VM VM VOL SV001606 GND tPHL tPLH Figure 4. Conditional reset input (MR) to output (Qn) propagation delays. VOH Qn OUTPUT VM VOL SV01608 Figure 2. Data input (D) to output (Qn) propagation delays. 1998 May 20 7 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 AC WAVEFORMS (Continued) TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V. VOL and VOH are the typical output voltage drop that occur with the output load. S1 VCC 2 * VCC Open GND 1k LE INPUT PULSE GENERATOR VM tsu D.U.T. 50pF RT GND tsu th CL 1k th VCC DEFINITIONS Dn INPUT RL = Load resistor VM CL = Load capacitance includes jig and probe capacitance GND RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION VOH Qn OUTPUT VO VI VCC Q=D VM TEST Q=D tPLH/tPHL VOL The shaded areas indicate when the input is permitted to change for predictable output performance S1 Open VCC VI < 2.7V VCC 2.7–3.6V 2.7V SV01609 SV00905 Figure 5. Data set-up and hold times for D input to LE input. Figure 7. Load circuitry for switching times. VCC An INPUT ADDRESS STABLE VM GND tsu th VCC LE INPUT VM GND The shaded areas indicate when the input is permitted to change for predictable output performance. SV01610 Figure 6. Address set-up and hold times for An inputs to LE input. 1998 May 20 8 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 DIP16: plastic dual in-line package; 16 leads (300 mil) 1998 May 20 9 SOT38-4 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 May 20 10 SOT109-1 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 May 20 11 SOT338-1 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 May 20 12 SOT403-1 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 NOTES 1998 May 20 13 Philips Semiconductors Product specification 8-bit addressable latch 74LV259 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 May 20 14 Date of release: 05-96 9397-750-04442