PHILIPS PCA9633DP2

PCA9633
4-bit Fm+ I2C-bus LED driver
Rev. 03 — 20 December 2006
Product data sheet
1. General description
The PCA9633 is an I2C-bus controlled 4-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own
8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at
97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set
to a specific brightness value. A fifth 8-bit resolution (256 steps) Group PWM controller
has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once
every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to
either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem-pole with a 25 mA sink, 10 mA source capability at 5 V. The PCA9633 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers and a minimum amount of discrete components for larger current or higher voltage
LEDs.
The PCA9633 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)
family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus
operation (up to 4000 pF).
The active LOW Output Enable input pin (OE) allows asynchronous control of the LED
outputs and can be used to set all the outputs to a defined I2C-bus programmable logic
state. The OE can also be used to externally PWM the outputs, which is useful when
multiple devices need to be dimmed or blinked together using software control. This
feature is available for the 16-pin version only.
Software programmable LED Group and three Sub Call I2C addresses allow all or defined
groups of PCA9633 devices to respond to a common I2C address, allowing for example,
all red LEDs to be turned on or off at the same time or marquee chasing effect, thus
minimizing I2C-bus commands.
The PCA9633 is offered with 3 different I2C-bus address options: fixed I2C-bus address
(8-pin version), 4 different I2C-bus addresses from 2 programmable address pins (10-pin
version), and 126 different I2C-bus addresses from 7 programmable address pins (16-pin
version). They are software identical except for the different number of address
combinations.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9633
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
2. Features
n 4 LED drivers. Each output programmable at:
u Off
u On
u Programmable LED brightness
u Programmable group dimming/blinking mixed with individual LED brightness
n 1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA
output for driving high capacitive buses
n 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 97 kHz PWM signal
n 256-step group brightness control allows general dimming (using a 190 Hz PWM
signal) from fully off to maximum brightness (default)
n 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and
duty cycle from 0 % to 99.6 %
n Four totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at totem-pole). No input
function.
n Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
n Active LOW Output Enable (OE) input pin. LED outputs programmable to ‘1’, ‘0’ or
‘high-impedance’ (default at power-up) when OE is HIGH, thus allowing hardware
blinking and dimming of the LEDs (16-pin version only).
n 2 hardware address pins (10-pin version) and 7 hardware address pins (16-pin
version) allow respectively up to 4 and 126 PCA9633 devices to be connected to the
same I2C-bus. No hardware address pins in the 8-pin version.
n 4 software programmable I2C-bus addresses (one LED Group Call address and three
LED Sub Call addresses) allow groups of devices to be addressed at the same time in
any combination (for example, one register used for ‘All Call’ so that all the PCA9633s
on the I2C-bus can be addressed at the same time and the second register used for
three different addresses so that 1⁄3 of all devices on the bus can be addressed at the
same time in a group). Software enable and disable for I2C-bus address.
n Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
n Up to 126 possible hardware adjustable individual I2C-bus addresses per device so
that each device can be programmed individually.
n 25 MHz internal oscillator requires no external components
n Internal power-on reset
n Noise filter on SDA/SCL inputs
n Edge rate control on outputs
n No glitch on power-up
n Supports hot insertion
n Low standby current
n Operating power supply voltage range of 2.3 V to 5.5 V
n 5.5 V tolerant inputs
n −40 °C to +85 °C operation
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
2 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO, TSSOP (MSOP), HVQFN, HVSON
3. Applications
n
n
n
n
n
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9633D16
PCA9633
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
PCA9633DP1
9633
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA9633DP2
9633
TSSOP10
plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
PCA9633PW
PCA9633
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9633BS
9633
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads; SOT629-1
16 terminals; body 4 × 4 × 0.85 mm
PCA9633TK
9633
HVSON8
plastic thermal enhanced very thin small outline package;
no leads; 8 terminals; body 3 × 3 × 0.85 mm
PCA9633_3
Product data sheet
SOT908-1
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
3 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
5. Block diagram
16-pin version
10-pin version
A0
A1
A2
A3
A4
A5
A6
PCA9633
SCL
INPUT FILTER
SDA
I2C-BUS
CONTROL
POWER-ON
RESET
VDD
VDD
VSS
LED
STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
97 kHz
24.3 kHz
25 MHz
OSCILLATOR
LEDn
GRPFREQ
REGISTER
MUX/
CONTROL
GRPPWM
REGISTER
190 Hz
'0' – permanently OFF
'1' – permanently ON
OE
(16-pin
version
only)
002aab283
Fig 1. Block diagram of PCA9633
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
4 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
6. Pinning information
6.1 Pinning
LED0
1
LED1
2
LED2
3
LED3
4
PCA9633DP1
8
VDD
7
SDA
6
SCL
5
VSS
10 VDD
9 SDA
LED0
1
LED1
2
LED2
3
8
SCL
LED3
4
7
A1
A0
5
6
VSS
PCA9633DP2
002aab314
002aab315
Fig 2. Pin configuration for TSSOP8
A0
1
16 VDD
A1
2
15 A6
LED0
3
14 A5
LED1
4
LED2
5
LED3
6
11 A4
A2
7
10 OE
A3
8
13 SDA
PCA9633PW
12 SCL
9
VSS
Fig 3. Pin configuration for TSSOP10
A0
1
16 VDD
A1
2
15 A6
LED0
3
14 A5
LED1
4
LED2
5
12 SCL
LED3
6
11 A4
A2
7
10 OE
A3
8
002aab316
13 A6
14 VDD
15 A0
16 A1
LED0
1
12 A5
LED1
2
11 SDA
LED2
3
10 SCL
LED3
4
9
5
6
7
8
A2
A3
VSS
OE
VSS
Fig 5. Pin configuration for SO16
terminal 1
index area
PCA9633BS
A4
002aab317
Transparent top view
Fig 6. Pin configuration for HVQFN16
PCA9633_3
Product data sheet
9
002aab313
Fig 4. Pin configuration for TSSOP16
terminal 1
index area
13 SDA
PCA9633D16
LED0
1
LED1
2
8
VDD
7
SDA
PCA9633TK
LED2
3
6
SCL
LED3
4
5
VSS
002aab807
Transparent top view
Fig 7. Pin configuration for HVSON8
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
5 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
6.2 Pin description
Table 2.
Pin description for TSSOP8 and HVSON8
Symbol
Pin
Type
Description
LED0
1
O
LED driver 0
LED1
2
O
LED driver 1
LED2
3
O
LED driver 2
LED3
4
O
LED driver 3
VSS
5
power supply
supply ground
SCL
6
I
serial clock line
SDA
7
I/O
serial data line
VDD
8
power supply
supply voltage
Table 3.
Pin description for TSSOP10
Symbol
Pin
Type
Description
LED0
1
O
LED driver 0
LED1
2
O
LED driver 1
LED2
3
O
LED driver 2
LED3
4
O
LED driver 3
A0
5
I
address input 0
VSS
6
power supply
supply ground
A1
7
I
address input 1
SCL
8
I
serial clock line
SDA
9
I/O
serial data line
VDD
10
power supply
supply voltage
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
6 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
Table 4.
Pin description for SO16 and TSSOP16
Symbol
Pin
Type
Description
A0
1
I
address input 0
A1
2
I
address input 1
LED0
3
O
LED driver 0
LED1
4
O
LED driver 1
LED2
5
O
LED driver 2
LED3
6
O
LED driver 3
A2
7
I
address input 2
A3
8
I
address input 3
VSS
9
power supply
supply ground
OE
10
I
active LOW Output Enable
A4
11
I
address input 4
SCL
12
I
serial clock line
SDA
13
I/O
serial data line
A5
14
I
address input 5
A6
15
I
address input 6
VDD
16
power supply
supply voltage
Table 5.
Pin description for HVQFN16
Symbol
Pin
Type
Description
LED0
1
O
LED driver 0
LED1
2
O
LED driver 1
LED2
3
O
LED driver 2
LED3
4
O
LED driver 3
A2
5
I
address input 2
6
I
address input 3
7
power supply
supply ground
A3
VSS
[1]
OE
8
I
active LOW Output Enable
A4
9
I
address input 4
SCL
10
I
serial clock line
SDA
11
I/O
serial data line
A5
12
I
address input 5
A6
13
I
address input 6
VDD
14
power supply
supply voltage
A0
15
I
address input 0
A1
16
I
address input 1
[1]
HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
7 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCA9633”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 128 possible programmable addresses using the 7 hardware
address pins. Two of these addresses, Software Reset and LED All Call, cannot be used
because their default power-up state is ON, leaving a maximum of 126 addresses. Using
other reserved addresses, as well as any other subcall address, will reduce the total
number of possible addresses even further.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9633 is shown in Figure 8. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW (10-pin and 16-pin versions).
Remark: For the 16-pin version, reserved I2C-bus addresses must be used with caution
since they can interfere with:
•
•
•
•
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX).
slave address
slave address
1
1
0
0
0
fixed
a. 8-pin version
1
1
0
R/W
1
0
0
0
fixed
002aab318
A1
slave address
A0 R/W
hardware
selectable
A6
A4
A3
A2
A1
hardware selectable
002aab295
b. 10-pin version
A5
A0 R/W
002aab319
c. 16-pin version
Fig 8. Slave address
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2C-bus address
• Default power-up value (ALLCALLADR register): E0h or 1110 000
• Programmable through I2C-bus (volatile programming)
• At power-up, LED All Call I2C-bus address is enabled. PCA9633 sends an ACK when
E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.8 “LED All Call I2C-bus address, ALLCALLADR” for more detail.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
8 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All the
PCA9633s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED Sub Call I2C-bus addresses
• 3 different I2C-bus addresses can be used
• Default power-up values:
– SUBADR1 register: E2h or 1110 001
– SUBADR2 register: E4h or 1110 010
– SUBADR3 register: E8h or 1110 100
• Programmable through I2C-bus (volatile programming)
• At power-up, Sub Call I2C-bus addresses are disabled. PCA9633 does not send an
ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or
E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.
See Section 7.3.7 “I2C-bus subaddress 1 to 3, SUBADRx” for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
7.1.4 Software Reset I2C-bus address
The address shown in Figure 9 is used when a reset of the PCA9633 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W = 0. If R/W = 1, the PCA9633 does not acknowledge the SWRST. See Section 7.6
“Software Reset” for more detail.
R/W
0
0
0
0
0
1
1
0
002aab416
Fig 9. Software Reset address
Remark: The Software Reset I2C-bus address is a reserved address and cannot be used
as a regular I2C-bus slave address (16-pin version) or as an LED All Call or LED Sub Call
address.
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9633, which will be
stored in the Control register.
The lowest 4 bits are used as a pointer to determine which register will be accessed
(D[3:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]). Bit 4 is unused and must be programmed with zero (0) for proper device
operation.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
9 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
register address
AI2 AI1 AI0
0
D3
D2
D1
D0
002aab296
Auto-Increment options
Auto-Increment flag
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 10. Control register
When the Auto-Increment flag is set (AI2 = 1), the four low order bits of the Control
register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values.
Table 6.
Auto-Increment options
AI2
AI1
AI0
Function
0
0
0
no Auto-Increment
1
0
0
Auto-Increment for all registers. D3, D2, D1, D0 roll over to ‘0000’ after
the last register (1100) is accessed.
1
0
1
Auto-Increment for individual brightness registers only. D3, D2, D1, D0
roll over to ‘0010’ after the last register (0101) is accessed.
1
1
0
Auto-Increment for global control registers only. D3, D2, D1, D0 roll over
to ‘0110’ after the last register (0111) is accessed.
1
1
1
Auto-Increment for individual and global control registers only. D3, D2,
D1, D0 roll over to ‘0010’ after the last register (0111) is accessed.
Remark: Other combinations not shown in Table 6 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a
single I2C-bus communication, for example, changes the brightness of a single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with
different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different
settings during the same I2C-bus communication, for example, global brightness or
blinking change.
AI[2:0] = 111 is used when individual and global changes must be performed during the
same I2C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 4 least significant bits D[3:0] are affected by the AI[2:0] bits.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
10 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
When the Control register is written, the register entry point determined by D[3:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0000 and 1100 (as defined in Table 7). When AI[2] = 1, the Auto-Increment flag
is set and the rollover value at which the point where the register increment stops and
goes to the next one is determined by AI[2:0]. See Table 6 for rollover values. For
example, if the Control register = 1110 1000 (E8h), then the register addressing sequence
will be (in hex):
08 → … → 0C → 00 → … → 07 → 02 → … → 07 → 02 → … → 07 → 02 → … as long
as the master keeps sending or reading data.
7.3 Register definitions
Table 7.
Register summary[1][2]
Register number (hex)
D3
D2
D1
D0
Name
Type
Function
00h
0
0
0
0
MODE1
read/write
Mode register 1
01h
0
0
0
1
MODE2
read/write
Mode register 2
02h
0
0
1
0
PWM0
read/write
brightness control LED0
03h
0
0
1
1
PWM1
read/write
brightness control LED1
04h
0
1
0
0
PWM2
read/write
brightness control LED2
05h
0
1
0
1
PWM3
read/write
brightness control LED3
06h
0
1
1
0
GRPPWM
read/write
group duty cycle control
07h
0
1
1
1
GRPFREQ
read/write
group frequency
08h
1
0
0
0
LEDOUT
read/write
LED output state
09h
1
0
0
1
SUBADR1
read/write
I2C-bus subaddress 1
0Ah
1
0
1
0
SUBADR2
read/write
I2C-bus subaddress 2
0Bh
1
0
1
1
SUBADR3
read/write
I2C-bus subaddress 3
0Ch
1
1
0
0
ALLCALLADR
read/write
LED All Call I2C-bus address
[1]
Only D[3:0] = 0000 to 1100 are allowed and will be acknowledged. D[3:0] = 1101, 1110, or 1111 are reserved and will not be
acknowledged.
[2]
When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
11 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.3.1 Mode register 1, MODE1
Table 8.
MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
AI2
read only
0
Register Auto-Increment disabled
1*
Register Auto-Increment enabled
0*
Auto-Increment bit 1 = 0
1
Auto-Increment bit 1 = 1
0*
Auto-Increment bit 0 = 0
1
Auto-Increment bit 0 = 1
0
Normal mode[1].
1*
Low power mode. Oscillator off[2].
0*
PCA9633 does not respond to I2C-bus subaddress 1.
1
PCA9633 responds to I2C-bus subaddress 1.
0*
PCA9633 does not respond to I2C-bus subaddress 2.
1
PCA9633 responds to I2C-bus subaddress 2.
0*
PCA9633 does not respond to I2C-bus subaddress 3.
1
PCA9633 responds to I2C-bus subaddress 3.
0
PCA9633 does not respond to LED All Call I2C-bus address.
1*
PCA9633 responds to LED All Call I2C-bus address.
6
AI1
5
read only
AI0
4
read only
SLEEP
3
SUB1
2
R/W
SUB2
1
R/W
SUB3
0
R/W
R/W
ALLCALL
R/W
[1]
It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window.
[2]
No blinking or dimming is possible when the oscillator is off.
7.3.2 Mode register 2, MODE2
Table 9.
MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit
Symbol
Access
Value
Description
7
-
read only
0*
reserved
6
-
read only
0*
reserved
5
DMBLNK
R/W
4
INVRT[1]
3
OCH
2
OUTDRV[1]
R/W
R/W
R/W
0*
Group control = dimming
1
Group control = blinking
0*
Output logic state not inverted. Value to use when no external driver used.
Applicable when OE = 0 for PCA9633 16-pin version.
1
Output logic state inverted. Value to use when external driver used.
Applicable when OE = 0 for PCA9633 16-pin version.
0*
Outputs change on STOP command.[2]
1
Outputs change on ACK.
0
The 4 LED outputs are configured with an open-drain structure.
1*
The 4 LED outputs are configured with a totem-pole structure.
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
Table 9.
MODE2 - Mode register 2 (address 01h) bit description …continued
Legend: * default value.
Bit
Symbol
Access
Value
Description
1 to 0
OUTNE[1:0]
R/W
00
When OE = 1 (output drivers not enabled), LEDn = 0.
01*
When OE = 1 (output drivers not enabled):
[3][4]
LEDn = 1 when OUTDRV = 1
LEDn = high-impedance when OUTDRV = 0 (same as OUTNE[1:0] = 10)
10
When OE = 1 (output drivers not enabled), LEDn = high-impedance.
11
reserved
[1]
See Section 7.7 “Using the PCA9633 with and without external drivers” for more details.
[2]
Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9633. Applicable to registers from
02h (PWM0) to 08h (LEDOUT) only.
[3]
See Section 7.4 “Active LOW output enable input” for more details.
[4]
OUTNE[1:0] is only for PCA9633 16-pin version.
7.3.3 PWM registers 0 to 3, PWMx—Individual brightness control registers
Table 10. PWM0 to PWM3 - PWM registers 0 to 3 (address 02h to 05h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access Value
Description
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000* PWM0 Individual Duty Cycle
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000* PWM1 Individual Duty Cycle
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000* PWM2 Individual Duty Cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000* PWM3 Individual Duty Cycle
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT register).
IDC [ 7:0 ]
duty cycle = -----------------------256
7.3.4 Group duty cycle control, GRPPWM
Table 11. GRPPWM - Group duty cycle control register (address 06h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
06h
GRPPWM
7:0
GDC[7:0]
R/W
1111 1111
GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 4 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
When DMBLNK bit is programmed with 1, GRPPWM and GRPFREQ registers define a
global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to
10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
GDC [ 7:0 ]
duty cycle = --------------------------256
7.3.5 Group frequency, GRPFREQ
Table 12. GRPFREQ - Group Frequency register (address 07h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
07h
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000*
GRPFREQ register
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT register).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
GFRQ [ 7:0 ] + 1
global blinking period = ---------------------------------------- (in seconds)
24
7.3.6 LED driver output state, LEDOUT
Table 13. LEDOUT - LED driver output state register (address 08h) bit description
Legend: * default value.
Address
Register
Bit
Symbol
Access
Value
Description
08h
LEDOUT
7:6
LDR3
R/W
00*
LED3 output state control
5:4
LDR2
R/W
00*
LED2 output state control
3:2
LDR1
R/W
00*
LED1 output state control
1:0
LDR0
R/W
00*
LED0 output state control
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
PCA9633_3
Product data sheet
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Rev. 03 — 20 December 2006
14 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.3.7 I2C-bus subaddress 1 to 3, SUBADRx
SUBADR1 to SUBADR3 - I2C-bus subaddress registers 0 to 3 (address 09h to
0Bh) bit description
Legend: * default value.
Table 14.
Address
Register
Bit
Symbol
Access Value
Description
09h
SUBADR1
7:1
A1[7:1]
R/W
1110 001*
I2C-bus subaddress 1
0
A1[0]
R only
0*
reserved
7:1
A2[7:1]
R/W
1110 010*
I2C-bus subaddress 2
0
A2[0]
R only
0*
reserved
7:1
A3[7:1]
R/W
1110 100*
I2C-bus subaddress 3
0
A3[0]
R only
0*
reserved
0Ah
SUBADR2
0Bh
SUBADR3
Subaddresses are programmable through the I2C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2C-bus subaddress can be used during either
an I2C-bus read or write sequence.
7.3.8 LED All Call I2C-bus address, ALLCALLADR
ALLCALLADR - LED All Call I2C-bus address register (address 0Ch) bit
description
Legend: * default value.
Table 15.
Address
Register
Bit
Symbol
Access Value
Description
0Ch
ALLCALLADR
7:1
AC[7:1]
R/W
1110 000*
ALLCALL I2C-bus
address register
0
AC[0]
R only
0*
reserved
The LED All Call I2C-bus address allows all the PCA9633s in the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1, power-up default
state). This address is programmable through the I2C-bus and can be used during either
an I2C-bus read or write sequence. The register address can be programmed as a
sub call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a Read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.4 Active LOW output enable input
The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
This control signal is only available for the 16-pin version and does not apply to the 8-pin
or 10-pin versions.
• When a LOW level is applied to OE pin, all the LED outputs are enabled and follow the
output state defined in the LEDOUT register with the polarity defined by INVRT bit
(MODE2 register).
• When a HIGH level is applied to OE pin, all the LED outputs are programmed to the
value that is defined by OUTNE[1:0] in the MODE2 register.
Table 16.
LED outputs when OE = 1
OUTNE1
OUTNE0
LED outputs
0
0
0
0
1
1 if OUTDRV = 1, high-impedance if OUTDRV = 0
1
0
high-impedance
1
1
reserved
The OE pin can be used as a synchronization signal to switch on/off several PCA9633
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
7.5 Power-on reset
When power is applied to VDD, an internal Power-on reset holds the PCA9633 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9633 registers and I2C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.6 Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved SWRST I2C-bus address ‘0000 011’ with the R/W bit set to 0 (write) is
sent by the I2C-bus master.
3. The PCA9633 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2C-bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends
2 bytes with 2 specific values (SWRST data byte 1 and byte 2):
a. Byte 1 = A5h: the PCA9633 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9633 does not acknowledge it.
b. Byte 2 = 5Ah: the PCA9633 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9633 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9633 does not acknowledge any more.
5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the SWRST Call:
the PCA9633 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
The I2C-bus master must interpret a non-acknowledge from the PCA9633 (at any time) as
a ‘SWRST Call Abort’. The PCA9633 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.7 Using the PCA9633 with and without external drivers
The PCA9633 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5 V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
• INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determined by LEDOUT register value) independently of the
type of external driver. This bit allows LED output polarity inversion/non-inversion only
when OE = 0.
• OUTDRV bit (MODE2 register) allows minimizing the amount of external components
required to control the external driver (N-type or P-type device).
Table 17.
Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE = 0[1]
INVRT OUTDRV Direct connection to LEDn
Firmware
External
pull-up
resistor
External N-type driver
External P-type driver
Firmware
Firmware
External
pull-up
resistor
External
pull-up
resistor
0
0
formulas and LED
output state values
apply[2]
LED current formulas and LED required
limiting R[2] output state
values inverted
0
1
formulas and LED
output state values
apply[2]
LED current formulas and LED not required formulas and LED not
limiting R[2] output state
output state values required[4]
values inverted
apply[4]
1
0
formulas and LED
output state values
inverted
LED current formulas and LED required
limiting R
output state
values apply
formulas and LED required
output state values
inverted
1
1
formulas and LED
output state values
inverted
LED current formulas and LED not
limiting R
output state
required[3]
[3]
values apply
formulas and LED not required
output state values
inverted
formulas and LED required
output state values
apply
[1]
OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
[2]
Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
[3]
Optimum configuration when external N-type (NPN, NMOS) driver used.
[4]
Optimum configuration when external P-type (PNP, PMOS) driver used.
PCA9633_3
Product data sheet
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
Table 18.
Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE = 0[1]
LEDOUT
INVRT
OUTDRV Upper transistor Lower transistor
(VDD to LEDn)
(LEDn to VSS)
LEDn state
00
0
0
off
off
high-Z[2]
LED driver off
0
1
on
off
VDD
1
0
off
on
VSS
1
1
off
on
VSS
01
0
0
off
on
VSS
LED driver on
0
1
off
on
VSS
1
0
off
off
high-Z[2]
1
1
on
off
VDD
10
0
0
off
VSS or high-Z[2] = PWMx value
Individual
brightness
control
Individual PWM
(non-inverted)
0
1
Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
VSS or VDD = PWMx value
1
0
off
Individual PWM
(inverted)
high-Z[2] or VSS = 1 − PWMx value
1
1
Individual PWM
(inverted)
Individual PWM
(inverted)
VDD or VSS = 1 − PWMx value
0
0
off
Individual +
Group
dimming/blinking 0
Individual + Group VSS or high-Z[2] = PWMx/GRPPWM values
PWM
(non-inverted)
1
Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
1
0
off
Individual + Group high-Z[2] or VSS = (1 − PWMx) or
(1 − GRPPWM) values
PWM (inverted)
1
1
Individual PWM
(inverted)
Individual PWM
(inverted)
11
VSS or VDD = PWMx/GRPPWM values
VDD or VSS = (1 − PWMx) or
(1 − GRPPWM) values
[1]
OE applies to 16-pin version only. When OE = 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
[2]
External pull-up or LED current limiting resistor connects LEDn to VDD.
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
7.8 Individual brightness control with group dimming/blinking
A 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
• A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 24 Hz to 1⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
1
2
3
4
5
6
7
8
9 10 11 12
507
508
509
510
511
512
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11
Brightness Control signal (LEDn)
N × 40 ns
with N = (0 to 255)
(PWMx Register)
M × 256 × 2 × 40 ns
with M = (0 to 255)
(GRPPWM Register)
256 × 40 ns = 10.24 µs
(97.6 kHz)
Group Dimming signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
1
2
3
4
5
6
7
8
resulting Brightness + Group Dimming signal
002aab417
Minimum pulse width for LEDn Brightness Control is 40 ns.
Minimum pulse width for Group Dimming is 20.48 µs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 2 pulses
of the LED Brightness Control signal (pulse width = N × 40 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 4 (8 pulses).
Fig 11. Brightness + Group Dimming signals
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 12).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 12. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 13.)
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mba608
Fig 13. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 14).
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PCA9633
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4-bit Fm+ I2C-bus LED driver
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 14. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
S
START
condition
2
8
9
clock pulse for
acknowledgement
002aaa987
Fig 15. Acknowledgement on the I2C-bus
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PCA9633
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4-bit Fm+ I2C-bus LED driver
9. Bus transactions
slave address(1)
data for register D3, D2, D1, D0(2)
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
X
X
X
0 D3 D2 D1 D0 A
Auto-Increment options
Auto-Increment flag
R/W
A
acknowledge
from slave
P
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aab418
(1) 16-pin version only.
(2) See Table 7 for register definition.
Fig 16. Write to a specific register
slave address(1)
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
0
0
0
0
0
acknowledge
from slave
SUBADR3 register
0
0
MODE1
register
selection
Auto-Increment
on all registers
R/W
(cont.)
1
MODE1 register
A
acknowledge
from slave
MODE2 register
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
ALLCALLADR register
A
A
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aab419
(1) 16-pin version only.
Fig 17. Write to all registers using the Auto-Increment feature
PCA9633_3
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PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
slave address(1)
control register
S A6 A5 A4 A3 A2 A1 A0 0
START condition
A
1
0
1
0
0
0
acknowledge
from slave
1
0
PWM0
register
selection
increment
on Individual
brightness
registers only
R/W
PWM0 register
PWM1 register
A
acknowledge
from slave
A
A
acknowledge
from slave
acknowledge
from slave
(cont.)
Auto-Increment on
PWM2 register
PWM3 register
(cont.)
PWM0 register
PWMx register
A
A
A
A
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
P
STOP
condition
002aab420
(1) 16-pin version only.
Fig 18. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
slave address(1)
S A6 A5 A4 A3 A2 A1 A0 0
START condition
ReSTART
condition
control register
A
1
0
0
0
acknowledge
from slave
data from MODE2 register
0
0
MODE1
register
selection
Auto-Increment
on all registers
R/W
(cont.)
0
0
slave address(1)
A Sr A6 A5 A4 A3 A2 A1 A0 1
acknowledge
from slave
A (cont.)
A
acknowledge
from master
R/W
acknowledge
from slave
Auto-Increment on
data from
ALLCALLADR register
data from PWM0
data from MODE1 register
data from
MODE1 register
A
A
A
acknowledge
from master
acknowledge
from master
acknowledge
from master
A (cont.)
acknowledge
from master
data from last read byte
(cont.)
A
not acknowledge
from master
P
STOP
condition
002aab423
(1) 16-pin version only.
Fig 19. Read all registers using the Auto-Increment feature
PCA9633_3
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24 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
slave address(1)
sequence (A) S
1
1
0
0
new LED All Call I2C address(2)
control register
0 A1 A0 0
START condition
A
R/W
acknowledge
from slave
X
X
X
0
1
1
0
0
A
1
0
1
0
1
ALLCALLADR
register selection acknowledge
from slave
Auto-Increment on
0
1
X
A
P
acknowledge
from slave
STOP
condition
the 16 LEDs are on at the acknowledge(3)
LED All Call I2C address
sequence (B) S
1
0
1
0
1
0
control register
1
START condition
0
A
X
X
X
0
1
0
LEDOUT register (LED fully ON)
0
0
A
0
1
0
1
0
LEDOUT
register selection acknowledge
from the
4 devices
R/W
acknowledge
from the
4 devices
1
0
1
A
P
acknowledge
from the
4 devices
STOP
condition
002aab424
(1) 10-pin version is used for this figure. Four PCA9633DP2 are used and the same sequence (A) (above) is sent to each of
them. A[1:0] = 00 to 11.
(2) ALLCALL bit in MODE1 register is equal to 1 for this example.
(3) OCH bit in MODE2 register is equal to 1 for this example.
Fig 20. LED All Call I2C-bus address programming and LED All Call sequence example
SWRST data
Byte 1 = 0xA5
SWRST Call I2C address
S
0
0
0
0
START condition
0
1
1
0
A
1
0
1
0
0
1
SWRST data
Byte 2 = 0x5A
0
1
A
0
1
0
acknowledge
from slave(s)
R/W
acknowledge
from slave(s)
1
1
0
1
0
A
P
acknowledge
from slave(s)
PCA9633 is(are) reset.
Registers are set to default power-up values.
002aab425
Fig 21. Software Reset (SWRST) Call sequence
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
25 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
10. Application design-in information
5V
12 V
VDD = 2.5 V, 3.3 V or 5.0 V
I2C-BUS/SMBus
MASTER
SDA
10 kΩ
10 kΩ
10 kΩ(1)
VDD
SDA
SCL
SCL
OE
OE
LED0
LED1
LED2
LED3
PCA9633
A0
A1
A2
A3
A4
A5
A6
VSS
002aab286
(1) OE requires pull-up resistor if control signal from the master is open-drain.
I2C-bus address = 0010 101x.
Fig 22. Typical application
11. Limiting values
Table 19. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
Conditions
−0.5
+6.0
V
VI/O
voltage on an input/output pin
VSS − 0.5
5.5
V
IO(LEDn)
output current on pin LEDn
-
25
mA
ISS
ground supply current
-
100
mA
Ptot
total power dissipation
-
400
mW
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
operating
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
26 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
12. Static characteristics
Table 20. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
-
5.5
V
VDD = 2.3 V
-
2.5
10
mA
VDD = 3.3 V
-
2.5
10
mA
VDD = 5.5 V
-
2.5
10
mA
VDD = 2.3 V
-
2.3
11
µA
VDD = 3.3 V
-
2.9
12
µA
Supply
VDD
supply voltage
IDD
supply current
Istb
standby current
operating mode; no load; fSCL = 1 MHz
no load; fSCL = 0 Hz; I/O = inputs; VI = VDD
VDD = 5.5 V
VPOR
power-on reset voltage
no load; VI = VDD or VSS
[1]
-
3.8
15.5
µA
-
1.70
2.0
V
−0.5
-
+0.3VDD V
Input SCL; input/output SDA
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
IOL
LOW-level output current VOL = 0.4 V; VDD = 2.3 V
20
-
-
mA
VOL = 0.4 V; VDD = 5.0 V
30
-
-
mA
IL
leakage current
VI = VDD or VSS
−1
-
+1
µA
Ci
input capacitance
VI = VSS
-
6
10
pF
LED driver outputs
IOL
LOW-level output current VOL = 0.5 V; VDD = 2.3 V
[2]
12
-
-
mA
VOL = 0.5 V; VDD = 3.0 V
[2]
17
-
-
mA
25
-
-
mA
-
-
100
mA
VOL = 0.5 V; VDD = 4.5 V
[2]
IOL(tot)
total LOW-level output
current
VOL = 0.5 V; VDD = 4.5 V
[2]
IOH
HIGH-level output
current
open-drain; VOH = VDD
−50
-
+50
µA
VOH
HIGH-level output
voltage
IOH = −10 mA; VDD = 2.3 V
1.6
-
-
V
IOH = −10 mA; VDD = 3.0 V
2.3
-
-
V
IOH = −10 mA; VDD = 4.5 V
4.0
-
-
V
output capacitance
-
2.5
5
pF
VIL
LOW-level input voltage
−0.5
-
+0.8
V
VIH
HIGH-level input voltage
2
-
5.5
V
ILI
input leakage current
−1
-
+1
µA
Ci
input capacitance
-
3.7
5
pF
Co
OE input
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
27 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
Table 20. Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
−0.5
-
+0.3VDD V
Address inputs
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
-
5.5
V
ILI
input leakage current
−1
-
+1
µA
Ci
input capacitance
-
3.7
5
pF
[1]
VDD must be lowered to 0.2 V in order to reset part.
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 100 mA due to internal busing limits.
13. Dynamic characteristics
Table 21.
Dynamic characteristics
Symbol Parameter
Conditions
Standard- mode
I2C-bus
[1]
Fast-mode
I2C-bus
Fast-mode
Plus I2C-bus
Min
Max
Min
Max
Min
Max
0
100
0
400
0
1000
Unit
fSCL
SCL clock frequency
tBUF
bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
µs
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
µs
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
µs
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
µs
tHD;DAT
data hold time
0
-
0
-
0
-
ns
tVD;ACK
data valid acknowledge time
[2]
0.3
3.45
0.1
0.9
0.05
0.45
µs
tVD;DAT
data valid time
[3]
0.3
3.45
0.1
0.9
0.05
0.45
µs
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
µs
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
µs
tf
fall time of both SDA and
SCL signals
-
300
20 + 0.1Cb[4]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[4]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-
50
-
50
-
50
ns
[5][6]
[7]
kHz
[1]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[2]
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[3]
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[4]
Cb = total capacitance of one bus line in pF.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
28 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
[5]
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[7]
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
SDA
tr
tBUF
tf
tHD;STA
tSP
tLOW
SCL
tHD;STA
P
tSU;STA
tHD;DAT
S
tHIGH
tSU;DAT
tSU;STO
Sr
P
002aaa986
Fig 23. Definition of timing
protocol
START
condition
(S)
tSU;STA
bit 7
MSB
(A7)
tLOW
bit 6
(A6)
tHIGH
bit 7
(D1)
bit 8
(D0)
acknowledge
(A)
STOP
condition
(P)
1/f
SCL
SCL
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab285
Rise and fall times refer to VIL and VIH.
Fig 24. I2C-bus timing diagram
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
29 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
14. Test information
VDD
PULSE
GENERATOR
VI
VO
RL
500 Ω
VDD
open
GND
DUT
RT
CL
50 pF
002aab284
RL = Load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse
generators.
Fig 25. Test circuitry for switching times
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
30 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
15. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 26. Package outline SOT109-1 (SO16)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
31 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Fig 27. Package outline SOT505-1 (TSSOP8)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
32 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
D
E
SOT552-1
A
X
c
y
HE
v M A
Z
6
10
A2
(A3)
A1
A
pin 1 index
θ
Lp
L
1
5
detail X
e
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.15
0.23
0.15
3.1
2.9
3.1
2.9
0.5
5.0
4.8
0.95
0.7
0.4
0.1
0.1
0.1
0.67
0.34
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-07-29
03-02-18
SOT552-1
Fig 28. Package outline SOT552-1 (TSSOP10)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
33 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 29. Package outline SOT403-1 (TSSOP16)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
34 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT629-1
terminal 1
index area
A A
1
E
c
detail X
e1
C
1/2 e
e
8
y
y1 C
v M C A B
w M C
b
5
L
9
4
e
e2
Eh
1/2 e
1
12
terminal 1
index area
16
13
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.38
0.23
c
D (1)
Dh
E (1)
Eh
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
e
e1
0.65
1.95
e2
L
v
w
y
y1
1.95
0.75
0.50
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT629-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-22
Fig 30. Package outline SOT629-1 (HVQFN16)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
35 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT908-1
0
1
2 mm
scale
X
B
D
A
E
A
A1
c
detail X
terminal 1
index area
e1
terminal 1
index area
e
v
w
b
1
4
M
M
C
C A B
C
y1 C
y
L
exposed tie bar (4×)
Eh
exposed tie bar (4×)
8
5
Dh
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
E(1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.3
0.2
0.2
3.1
2.9
2.25
1.95
3.1
2.9
1.65
1.35
0.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
SOT908-1
REFERENCES
IEC
JEDEC
JEITA
MO-229
EUROPEAN
PROJECTION
ISSUE DATE
05-09-26
05-10-05
Fig 31. Package outline SOT908-1 (HVSON8)
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
36 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
37 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 22 and 23
Table 22.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 23.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
38 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 24.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
NMOS
Negative-channel Metal Oxide Semiconductor
PCB
Printed-Circuit Board
PMOS
Positive-channel Metal Oxide Semiconductor
PWM
Pulse Width Modulation
RGB
Red/Green/Blue
RGBA
Red/Green/Blue/Amber
SMBus
System Management Bus
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
39 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
19. Revision history
Table 25.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9633_3
20061220
Product data sheet
-
PCA9633_2
Modifications:
•
Section 1 “General description”:
– 2nd paragraph, last sentence: changed “... larger current LEDs or higher voltage LED strings.”
to “... larger current or higher voltage LEDs.
– 3rd paragraph, 2nd sentence: changed “... and longer more densely populated ...” to “and more
densely populated ...”
•
Section 2 “Features”, 9th bullet item: changed “... and 127 PCA9633 devices” to “... and 126
PCA9633 devices”
•
•
•
Section 3 “Applications”: deleted (old) second bullet item
Section 7.1 “Device addresses”: added new 2nd paragraph
Deleted (old) Section 10.1, Section 20.4, and Section 20.5
PCA9633_2
20061114
Product data sheet
-
PCA9633_1
PCA9633_1
(9397 750 14614)
20060123
Product data sheet
-
-
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
40 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
PCA9633_3
Product data sheet
© NXP B.V. 2006. All rights reserved.
Rev. 03 — 20 December 2006
41 of 42
PCA9633
NXP Semiconductors
4-bit Fm+ I2C-bus LED driver
22. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.4
7.5
7.6
7.7
7.8
8
8.1
8.1.1
8.2
8.3
9
10
11
12
13
14
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 8
Device addresses . . . . . . . . . . . . . . . . . . . . . . . 8
Regular I2C-bus slave address . . . . . . . . . . . . . 8
LED All Call I2C-bus address . . . . . . . . . . . . . . 8
LED Sub Call I2C-bus addresses . . . . . . . . . . . 9
Software Reset I2C-bus address . . . . . . . . . . . 9
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register definitions . . . . . . . . . . . . . . . . . . . . . 11
Mode register 1, MODE1 . . . . . . . . . . . . . . . . 12
Mode register 2, MODE2 . . . . . . . . . . . . . . . . 12
PWM registers 0 to 3, PWMx—Individual
brightness control registers . . . . . . . . . . . . . . 13
Group duty cycle control, GRPPWM . . . . . . . 13
Group frequency, GRPFREQ . . . . . . . . . . . . . 14
LED driver output state, LEDOUT . . . . . . . . . 14
I2C-bus subaddress 1 to 3, SUBADRx . . . . . . 15
LED All Call I2C-bus address, ALLCALLADR. 15
Active LOW output enable input . . . . . . . . . . . 16
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . 17
Using the PCA9633 with and without external
drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 20
Characteristics of the I2C-bus. . . . . . . . . . . . . 21
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
START and STOP conditions . . . . . . . . . . . . . 21
System configuration . . . . . . . . . . . . . . . . . . . 21
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 23
Application design-in information . . . . . . . . . 26
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26
Static characteristics. . . . . . . . . . . . . . . . . . . . 27
Dynamic characteristics . . . . . . . . . . . . . . . . . 28
Test information . . . . . . . . . . . . . . . . . . . . . . . . 30
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31
Handling information. . . . . . . . . . . . . . . . . . . . 37
17
17.1
17.2
17.3
17.4
18
19
20
20.1
20.2
20.3
20.4
21
22
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
37
38
39
40
41
41
41
41
41
41
42
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]nxp.com
Date of release: 20 December 2006
Document identifier: PCA9633_3